Winbond Electronics W83627HF-PW, W83627HF-AW Datasheet

W83627HF/F
WINBOND I/O
W83627HF/F Data Sheet Revision History
1 n.a. 09/25/98 0.50
2 88-93,102,105,
3 90-93;113-115 01/11/9
4
5
6
7
8
Pages Dates Version
11/10/9
139,151,153
90,91,113-115, 119-123,133,136, 137,140,141
8
9
07/26/9
9
0.51
0.52 Pinout and register correction.
0.53
Version on Web
Main Contents
Not released For internal use only
First published. Explanation of H/W Monitor function
and register correction.
Typo and data correction. H/W Monitor register explanation.
9
1 0
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such
W83627HF/F
PRELIMINARY
applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date:Sep 1998
-II - Revision 0.50
W83627HF/F
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION.......................................................................................................1
PIN CONFIGURATION FOR 627F..........................................................................................5
PIN CONFIGURATION FOR 627HF......................................................................................6
1. PIN DESCRIPTION................................................................................................................7
1.1 LPC INTERFACE...................................................................................................................................................7
1.2 FDC INTERFACE...................................................................................................................................................8
1.3 MULTI-MODE PARALLEL PORT......................................................................................................................9
1.4 SERIAL PORT INTERFACE..............................................................................................................................14
1.5 KBC INTERFACE................................................................................................................................................15
1.6 ACPI INTERFACE...............................................................................................................................................15
1.7 HARDWARE MONITOR INTERFACE............................................................................................................15
(FOR W83627HF ONLY, ALL THESE PINS IN W83627F ARE NC.)........................................................15
1.8 GAME PORT & MIDI PORT..............................................................................................................................16
1.9 GENERAL PURPOSE I/O PORT.....................................................................................................................18
1.9.1 General Purpose I/O Port 1 (Power source is Vcc)......................................................................................18
1.9.2 General Purpose I/O Port 2 (Power source is Vcc)......................................................................................18
1.9.3 General Purpose I/O Port 3 (Power souce is VSB).....................................................................................19
1.10 POWER PINS .....................................................................................................................................................19
2. LPC (LOW PIN COUNT) INTERFACE............................................................................20
3. FDC FUNCTIONAL DESCRIPTION................................................................................21
3.1 W83627HF FDC...................................................................................................................................................21
3.1.1 AT interface .....................................................................................................................................................21
3.1.2 FIFO (Data).....................................................................................................................................................21
3.1.3 Data Separator...............................................................................................................................................22
3.1.4 Write Precompensation..................................................................................................................................22
3.1.5 Perpendicular Recording Mode....................................................................................................................22
3.1.6 FDC Core .......................................................................................................................................................23
Publication Release Date:Sep 1998
-I - Preliminary Revision 0.50
W83627HF/F
PRELIMINARY
3.1.7 FDC Commands ............................................................................................................................................23
3.2 REGISTER DESCRIPTIONS..............................................................................................................................34
3.2.1 Status Register A (SA Register) (Read base address + 0)...........................................................................34
3.2.2 Status Register B (SB Register) (Read base address + 1)...........................................................................36
3.2.3 Digital Output Register (DO Register) (Write base address + 2) ..............................................................38
3.2.4 Tape Drive Register (TD Register) (Read base address + 3).....................................................................38
3.2.5 Main Status Register (MS Register) (Read base address + 4) ...................................................................39
3.2.6 Data Rate Register (DR Register) (Write base address + 4) ......................................................................39
3.2.7 FIFO Register (R/W base address + 5)........................................................................................................41
3.2.8 Digital Input Register (DI Register) (Read base address + 7)...................................................................43
3.2.9 Configuration Control Register (CC Register) (Write base address + 7).................................................44
4. UART PORT...........................................................................................................................45
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................45
4.2 REGISTER ADDRESS........................................................................................................................................45
4.2.1 UART Control Register (UCR) (Read/Write)................................................................................................45
4.2.2 UART Status Register (USR) (Read/Write)...................................................................................................47
4.2.3 Handshake Control Register (HCR) (Read/Write) ......................................................................................48
4.2.4 Handshake Status Register (HSR) (Read/Write)..........................................................................................49
4.2.5 UART FIFO Control Register (UFR) (Write only) ......................................................................................50
4.2.6 Interrupt Status Register (ISR) (Read only) .................................................................................................51
4.2.7 Interrupt Control Register (ICR) (Read/Write)............................................................................................52
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)........................................................................52
4.2.9 User-defined Register (UDR) (Read/Write)..................................................................................................53
5. CIR RECEIVER PORT ........................................................................................................54
5.1 CIR REGISTERS...................................................................................................................................................54
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)................................................................................54
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ...........................................................................................54
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)...............................................................................................54
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)........................55
5.1.5 Bank0.Reg4 - CIR Control Register (CTR)...................................................................................................55
5.1.6 Bank0.Reg5 - UART Line Status Register (USR)........................................................................................56
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)......................................................................57
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR)....................................................................................58
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)...............................................................................59
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)...............................................................................................60
Publication Release Date:Sep 1998
-II - Revision 0.50
W83627HF/F
PRELIMINARY
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3).....................60
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL).......................................................................................60
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH).....................................................................................60
6. PARALLEL PORT ...............................................................................................................61
6.1 PRINTER INTERFACE LOGIC..........................................................................................................................61
6.2 ENHANCED PARALLEL PORT (EPP).............................................................................................................62
6.2.1 Data Swapper.................................................................................................................................................63
6.2.2 Printer Status Buffer .......................................................................................................................................63
6.2.3 Printer Control Latch and Printer Control Swapper..................................................................................64
6.2.4 EPP Address Port............................................................................................................................................64
6.2.5 EPP Data Port 0-3 ..........................................................................................................................................65
6.2.6 Bit Map of Parallel Port and EPP Registers.................................................................................................65
6.2.7 EPP Pin Descriptions ....................................................................................................................................66
6.2.8 EPP Operation................................................................................................................................................66
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ...............................................................................67
6.3.1 ECP Register and Mode Definitions..............................................................................................................67
6.3.2 Data and ecpAFifo Port................................................................................................................................68
6.3.3 Device Status Register (DSR)........................................................................................................................68
6.3.4 Device Control Register (DCR)......................................................................................................................69
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.............................................................................................70
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011.....................................................................................................70
6.3.7 tFifo (Test FIFO Mode) Mode = 110...........................................................................................................70
6.3.8 cnfgA (Configuration Register A) Mode = 111...........................................................................................70
6.3.9 cnfgB (Configuration Register B) Mode = 111..........................................................................................70
6.3.10 ecr (Extended Control Register) Mode = all..............................................................................................71
6.3.11 Bit Map of ECP Port Registers...................................................................................................................72
6.3.12 ECP Pin Descriptions..................................................................................................................................73
6.3.13 ECP Operation.............................................................................................................................................74
6.3.14 FIFO Operation...........................................................................................................................................74
6.3.15 DMA Transfers.............................................................................................................................................75
6.3.16 Programmed I/O (NON-DMA) Mode ........................................................................................................75
6.4 EXTENSION FDD MODE (EXTFDD)..............................................................................................................75
6.5 EXTENSION 2FDD MODE (EXT2FDD)..........................................................................................................75
7. KEYBOARD CONTROLLER............................................................................................76
7.1 OUTPUT BUFFER................................................................................................................................................77
Publication Release Date:Sep 1998
-III - Revision 0.50
W83627HF/F
PRELIMINARY
7.2 INPUT BUFFER....................................................................................................................................................77
7.3 STATUS REGISTER ............................................................................................................................................77
7.4 COMMANDS.........................................................................................................................................................78
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC.............................................................80
7.5.1 KB Control Register (Logic Device 5, CR-F0) .............................................................................................80
7.5.2 Port 92 Control Register (Default Value = 0x24)........................................................................................80
8. GENERAL PURPOSE I/O....................................................................................................81
9. PLUG AND PLAY CONFIGURATION ............................................................................84
9.1 COMPATIBLE PNP..............................................................................................................................................84
9.1.1 Extended Function Registers..........................................................................................................................84
9.1.2 Extended Functions Enable Registers (EFERs)............................................................................................85
9.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)......................85
9.2 CONFIGURATION SEQUENCE........................................................................................................................85
9.2.1 Enter the extended function mode..................................................................................................................85
9.2.2 Configurate the configuration registers........................................................................................................85
9.2.3 Exit the extended function mode ....................................................................................................................86
9.2.4 Software programming example....................................................................................................................86
10. ACPI REGISTERS FEATURES.......................................................................................87
11. HARDWARE MONITOR...................................................................................................88
11.1 GENERAL DESCRIPTION ...............................................................................................................................88
11.2 ACCESS INTERFACE.......................................................................................................................................88
11.2.1 LPC interface.................................................................................................................................................88
11.2.2 I2C interface..................................................................................................................................................90
11.3 ANALOG INPUTS..............................................................................................................................................94
11.3.1 Monitor over 4.096V voltage:......................................................................................................................94
11.3.2 Monitor negative voltage:............................................................................................................................95
11.3.3 Temperature Measurement Machine...........................................................................................................96
11.4 FAN SPEED COUNT AND FAN SPEED CONTROL...................................................................................97
11.4.1 Fan speed count............................................................................................................................................97
11.4.2 Fan speed control .........................................................................................................................................99
11.5 SMI# INTERRUPT MODE................................................................................................................................99
11.5.1 Voltage SMI# mode :....................................................................................................................................99
11.5.2 Fan SMI# mode :..........................................................................................................................................99
Publication Release Date:Sep 1998
-IV - Revision 0.50
W83627HF/F
PRELIMINARY
11.5.3 The W83627HF temperature sensor 1 SMI# interrupt has two modes: ............................................... 100
11.5.4 The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is
programmed at CR[4Ch] bit 6..............................................................................................................101
11.6 OVT# INTERRUPT MODE............................................................................................................................ 102
11.6.1 The W83627HF temperature sensor 2 and 3 Over-Temperature (OVT#) has the following modes. 102
11.7 REGISTERS AND RAM.................................................................................................................................103
11.7.1 Address Register (Port x5h) ...................................................................................................................... 103
11.7.2 Data Register (Port x6h) ........................................................................................................................... 106
11.7.3 Configuration Register ¾ Index 40h ......................................................................................................... 106
11.7.4 Interrupt Status Register 1¾ Index 41h..................................................................................................... 107
11.7.5 Interrupt Status Register 2 ¾ Index 42h.................................................................................................... 108
11.7.6 SMI# Mask Register 1 ¾ Index 43h........................................................................................................... 108
11.7.7 SMI# Mask Register 2 ¾ Index 44h........................................................................................................... 109
11.7.8 Reserved Register ¾ Index 45h................................................................................................................... 109
11.7.9 Chassis Clear Register -- Index 46h......................................................................................................... 109
11.7.10 VID/Fan Divisor Register ¾ Index 47h................................................................................................... 110
11.7.11 Serial Bus Address Register ¾ Index 48h................................................................................................ 110
11.7.12 Value RAM ¾ Index 20h- 3Fh or 60h - 7Fh (auto-increment).............................................................111
11.7.13 Voltage ID (VID4) & Device ID Register - Index 49h.......................................................................... 112
11.7.14 Temperature 2 and Temperature 3 Serial Bus Address Register--Index 4Ah....................................113
11.7.15 Pin Control Register - Index 4Bh...........................................................................................................113
11.7.16 IRQ/OVT# Property Select Register- Index 4Ch................................................................................... 114
11.7.17 FAN IN/OUT and BEEP Control Register- Index 4Dh........................................................................ 115
11.7.18 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (No Auto Increase)......................................... 116
11.7.19 Winbond Vendor ID Register - Index 4Fh (No Auto Increase)............................................................ 116
11.7.20 Winbond Test Register -- Index 50h - 55h (Bank 0)............................................................................ 117
11.7.21 BEEP Control Register 1-- Index 56h (Bank 0).................................................................................... 117
11.7.22 BEEP Control Register 2-- Index 57h (Bank 0).................................................................................... 117
11.7.23 Chip ID -- Index 58h (Bank 0)................................................................................................................118
11.7.24 Reserved Register -- Index 59h (Bank 0) .............................................................................................. 119
11.7.25 PWMOUT1 Control -- Index 5Ah (Bank 0)........................................................................................... 119
11.7.26 PWMOUT2 Control -- Index 5Bh (Bank 0)........................................................................................... 119
11.7.27 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)................................................................................ 120
11.7.28 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ...................................................................... 120
11.7.29 Reserved Register -- 5Eh (Bank 0) ....................................................................................................... 121
11.7.30 Reserved Register -- Index 5Fh (Bank 0).............................................................................................. 121
11.7.31 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1)............................... 121
Publication Release Date:Sep 1998
-V - Revision 0.50
W83627HF/F
PRELIMINARY
11.7.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1) ................................ 122
11.7.33 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1)................................................. 122
11.7.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)....................................123
11.7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1)..................................... 123
11.7.36 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)....................... 124
11.7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1)........................ 124
11.7.38 Temperature Sensor 3 Temperature (High Byte) Register - Index 50h (Bank 2)............................... 125
11.7.39 Temperature Sensor 3 Temperature (Low Byte) Register - Index 51h (Bank 2) ................................ 125
11.7.40 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2)................................................. 125
11.7.41 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2)....................................126
11.7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2)..................................... 126
11.7.43 Temperature Sensor 3 Over-temperature (High Byte) Register - Index 55h (Bank 2)....................... 127
11.7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h(Bank 2)......................... 127
11.7.45 Interrupt Status Register 3 -- Index 50h (BANK4)................................................................................ 128
11.7.46 SMI# Mask Register 3 -- Index 51h (BANK 4)..................................................................................... 128
11.7.47 Reserved Register -- Index 52h (Bank 4) ............................................................................................... 128
11.7.48 BEEP Control Register 3-- Index 53h (Bank 4).................................................................................... 129
11.7.49 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4).............................................................. 129
11.7.50 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4).............................................................. 130
11.7.51 Temperature Sensor 3 Offset Register -- Index 56h (Bank 4).............................................................. 130
11.7.52 Reserved Register -- Index 57h--58h...................................................................................................... 130
11.7.53 Real Time Hardware Status Register I -- Index 59h (Bank 4) ............................................................. 131
11.7.54 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)............................................................ 131
11.7.55 Real Time Hardware Status Register III -- Index 5Bh (Bank 4).......................................................... 132
11.7.56 Reserved Register -- Index 5Ch-5Dh (Bank 4)...................................................................................... 133
11.7.57 Value RAM 2¾ Index 50h - 5Ah (auto-increment) (BANK 5).............................................................. 133
11.7.58 Winbond Test Register -- Index 50h (Bank 6).......................................................................................133
12. SERIAL IRQ.......................................................................................................................134
12.1 START FRAME................................................................................................................................................ 134
12.2 IRQ/DATA FRAME......................................................................................................................................... 134
12.3 STOP FRAME .................................................................................................................................................. 135
13. CONFIGURATION REGISTER....................................................................................136
13.1 CHIP (GLOBAL) CONTROL REGISTER ................................................................................................... 136
13.2 LOGICAL DEVICE 0 (FDC)..........................................................................................................................142
13.3 LOGICAL DEVICE 1 (PARALLEL PORT)................................................................................................. 145
Publication Release Date:Sep 1998
-VI - Revision 0.50
W83627HF/F
PRELIMINARY
13.4 LOGICAL DEVICE 2 (UART A)¢)................................................................................................................ 146
13.5 LOGICAL DEVICE 3 (UART B)................................................................................................................... 147
13.6 LOGICAL DEVICE 5 (KBC) ......................................................................................................................... 148
13.7 LOGICAL DEVICE 6 (CIR)........................................................................................................................... 149
13.8 LOGICAL DEVICE 7 (GAME PORT AND MIDI PORT AND GPIO PORT 1).................................... 150
13.9 LOGICAL DEVICE 8 (GPIO PORT 2).......................................................................................................... 150
13.10 LOGICAL DEVICE 9 (GPIO PORT 3 THIS POWER OF THE PORT IS STANDBY SOURCE (VSB) )152
13.11 LOGICAL DEVICE A (ACPI) ..................................................................................................................... 153
13.12 LOGICAL DEVICE B (HARDWARE MONITOR)..................................................................................160
14. SPECIFICATIONS...........................................................................................................161
14.1 ABSOLUTE MAXIMUM RATINGS............................................................................................................ 161
14.2 DC CHARACTERISTICS..............................................................................................................................161
15. APPLICATION CIRCUITS............................................................................................164
15.1 PARALLEL PORT EXTENSION FDD........................................................................................................ 164
15.2 PARALLEL PORT EXTENSION 2FDD...................................................................................................... 165
15.3 FOUR FDD MODE......................................................................................................................................... 165
16. ORDERING INSTRUCTION.........................................................................................166
17. HOW TO READ THE TOP MARKING .....................................................................166
18. PACKAGE DIMENSIONS..............................................................................................167
Publication Release Date:Sep 1998
-VII - Revision 0.50
W83627HF/F
PRELIMINARY
GENERAL DESCRIPTION
The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC ( next generation Intel chip-set. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83627F/HF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration.
The disk drive adapter functions of W83627F/HF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627F/HF greatly reduces the number of components required for interfacing with floppy disk drives. The W83627F/HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83627F/HF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates
230k, 460k
of provides IR functions: RC-5, extended RC-5, and RECS-80 protocols).
The W83627F/HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95/98TM, which makes system resource allocation more efficient than ever.
The W83627F/HF provides functions that complies with
Interface
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up. The W83627F/HF also has auto power management to reduce the power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY MultiKey/42TM, or customer code.
The W83627F/HF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off).
), which includes support of legacy and ACPI power management through
, or
921k bps
which support higher speed modems. In addition, the W83627F/HF
IrDA 1.0 (SIR
for 1.152K bps) and TV remote IR (
Low Pin Count
ACPI (Advanced Configuration and Power
) interface, which will be supported in the
Consumer IR
, supporting NEC,
PSOUT#
or
PME#
TM
-
2, Phoenix
Publication Release Date: Jul 1999
- 1 - Revision 0.53
W83627HF/F
PRELIMINARY
The W83627F/HF is made to fully comply with Moreover W83627F/HF is made to meet the specification of PC98/PC99's requirement in the power management:
The W83627F/HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer.
Only the W83627HF support hardware status monitoring
monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly.
ACPI
and
DPM
(Device Power Management).
FEATURES
General
£» Meet LPC Spec. 1.0 £» Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) £» Include all the features of Winbond I/O W83977TF and W83977EF £» Integrate Hardware Monitor functions £» Compliant with Microsoft PC98/PC99 Hardware Design Guide £» Support DPM (Device Power Management), ACPI £» Programmable configuration settings £» Single 24 or 48 MHz clock input
FDC
£» Compatible with IBM PC AT disk drive systems £» Variable write pre-compensation with track selectable capability £» Support vertical recording format £» DMA enable logic £» 16-byte data FIFOs £» Support floppy disk drives and tape drives £» Detects all overrun and underrun conditions £» Built-in address mark detection circuit to simplify the read electronics £» FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive) £» Support up to four 3.5-inch or 5.25-inch floppy disk drives £» Completely compatible with industry standard 82077 £» 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate £» Support
3-mode FDD, and its Win95/98 driver
Microsoft PC98 and PC99 Hardware Design Guide
for personal computers. It can be used to
.
Publication Release Date: Jul 1999
- 2 - Revision 0.53
W83627HF/F
PRELIMINARY
UART
£» Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs £» MIDI compatible £» Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
£» Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation £» Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) £» Maximum baud rate up to
Infrared
£» Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps £» Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps £» Support Consumer IR
Parallel Port
£» Compatible with IBM parallel port £» Support PS/2 compatible bi-directional parallel port £» Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification £» Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification £» Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B
through parallel port
£» Enhanced printer port back-drive current protection
Keyboard Controller
£» 8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42
bytes of programmable ROM, and 256 bytes of RAM £» Asynchronous Access to Two Data Registers and One status Register £» Software compatibility with the 8042 £» Support PS/2 mouse £» Support port 92 £» Support both interrupt and polling modes
£» Fast Gate A20 and Hardware Keyboard Reset
£» 8 Bit Timer/ Counter £» Support binary and BCD arithmetic £» 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
921k bps
for 14.769 MHz and 1.5M bps for 24 MHz
TM
or customer code with 2K
Publication Release Date: Jul 1999
- 3 - Revision 0.53
W83627HF/F
PRELIMINARY
Game Port
£» Support two separate Joysticks £» Support every Joystick two axis (X,Y) and two button (A,B) controllers
MIDI Port
£» The baud rate is 31.25 Kbaud £» 16-byte input FIFO £» 16-byte output FIFO
General Purpose I/O Ports
£» 22 programmable general purpose I/O ports £» General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch dog timer
output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST#
signal, PWROK signal, Beep output £» Functional in power down mode (GP1 only)
OnNow Functions
£» Keyboard Wake-Up by programmable keys £» Mouse Wake-Up by programmable buttons £» CIR Wake-Up by programmable keys £» On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Hardware Monitor Functions ( Only for W83627HF)
£» 5 VID input pins for CPU Vcore identification £» 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II
(Deschutes) thermal diode output £» 7 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, VcoreA, VcoreB) £» 2 intrinsic voltage monitoring (typical for Vbat, +5VSB) £» 3 fan speed monitoring inputs £» 2 fan speed control £» Build in Case open detection circuit £» WATCHDOG comparison of all monitored values £» Programmable hysteresis and setting points for all monitored items £» Over temperature indicate output £» Automatic Power On voltage detection Beep £» Issue SMI#, IRQ, OVT# to activate system protection £» Intel LDCMTM / Acer ADMTM compatible
Package
£» 128-pin PQFP
Publication Release Date: Jul 1999
- 4 - Revision 0.53
PIN CONFIGURATION FOR 627F
G
G
A
P
P
G
2
2
N
1
2
D
C
9 1
2
W83627F
1011121
8 9
NC NC NC NC NC NC NC NC NC NC NC
VCC
NC NC
VSS
NC
MSI/GP20
MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16
GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12
GPSB1/P13/GP11 GPSA1/P12/GP10
103 104
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
125 126 127
128
NCNCNCNCN
NCNCN
C
1
1
1
9
0
0
0
998
2
1
0
1 2 3 4 567
A V C C
9
969594939
7
I
W
P
R
D
L
R
T
E
X
O
D
/
/
/
G
G
G
P
P
P
2
2
2
5
4
3
9089888
1 415161718
3
I R T X / G P 2 6
786
V S S
D
S
R
C
O
S
I
D
U
I
B
B
T
N
#
#
B
B
8
8
8
5
3828180797877
4
192
2
0
1222324252627
W83627HF/F
PRELIMINARY
P
R
S
W
S
L
R
M
P
C
P
C
R
W
I
_
T
S
R
S X
# / G P 3 0
7 3
L
O
#
K
/
/
G
G
P
P
3
3
1
2
7 27170
R
T
R
#
X
P
/
/
S
G
G
P
O
M P 3 3
3 3
M
P
S
U
D
C
3
I
T
A
L
4
N
#
T
K
6
6
6
6
9
6
867
5
64
SUSLED/GP35 KDAT
63 62
KCLK
61
VSB
60
KBRST
59
A20GATE
KBLOCK#
58
RIA#
57 56
DCDA# VSS
55 54
SOUTA
53
SINA
52
DTRA# 51 50
49 48 47
46 45 44 43 42 41 40
3
3
5
4
39
3
373
6
8
RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
S U
D
R
T
T
R
S
B
B
#
#
S
D
C
C S R B #
V
T
L
S
V
K
B A
B
C
I
N
T
#
C
N
C
7
7
6
574
2
2
8
9303132
P
L
S
L
L
L
L
V
D
D
I
M
D
D
R
R
V
V
D
D
E
E
N
N
0
1 / S M I #
/ G P 2 7
M
N
O
S
S
O
D
A
B
A
B
E
#
#
#
# X #
V
D
S
W
W
T
W
C
I
T
D
E
R
P
C
R
E
#
#
A
#
P #
# K 0 #
P
C
R D A T A #
V
H
D
C
D
E
M
L
E
S
E
K
A
K
#
I
D
C
N
#
H G #
A
S
I
R
R
D
S
C
Q
I
3
L
#
R
K
Q
L
L
S
PEB
A
P
P
P
A
A
A
C
F
R
L
D
D
D
C
2
1
0
3 V
U
R
E
C
S
A
S
T
Y
M
E
E
T
#
#
P
C
D
D
D
D
K
7
6
5
4
#
Publication Release Date: Jul 1999
- 5 - Revision 0.53
PIN CONFIGURATION FOR 627HF
P
S
S
L
C
D
E
L
A
D
/
/
/
­G
G
G
5
A
P
P
P
V
G
2
2
2
I
N
1
2
3
N
D
9
9089888
1
2
W83627HF
1
9
0111213
VTIN2 VTIN1
OVT#
VID4 VID3 VID2
VID1
VID0 FANIO3 FANIO2
FANIO1
VCC
FANPWM2 FANPWM1
VSS
BEEP
MSI/GP20
MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16
GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12
GPSB1/P13/GP11 GPSA1/P12/GP10
103 104
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
125 126 127
128
+
V
V
3
+
-
1
C O R E B
9 998
. 3 V I N
5 6
A V C C
9 7
1
2
2
V
V
I
I
N
N
969594939
7
8
V
C
V
T
O
R
I
R
E
N
E
F
3
A
1
1
1
0
0
0
2
1
0
3 4
1 2
I
I
W
R
R
D
R
T
T
X
X
O
/
/
/
G
G
G
P
P
V
P
2
2
S
2
5
6
S
4
786
141516171
D
S
R
C
O
S
I
D
U
I
B
B
T
N
#
#
B
B
8
8
8
5
3828180797877
4
2
2
0
819
122
D
R
D
T
T
S
R
S
R
B
B
B
#
#
#
232425262
W83627HF/F
PRELIMINARY
P
R
S
W
S
L
R
M
P
C
P
C
R
W
_ S X
# / G P 3 0
7
7
3
27170
30313
I
T
S
R
R
L
T
O
R
#
#
K
X / G P 3 1
P
/
/
/
S
G
G
G
P
O
M P 3 4
6 9
3 435
S I N
6 867
M
U
D
C
T
A
L
#
T
K
6
6
6
5
64
SUSLED/GP35
63
KDAT
62
KCLK
61
VSB
60
KBRST
59
A20GATE
KBLOCK#
58
RIA#
57 56
DCDA# VSS
55 54
SOUTA
53
SINA
52
DTRA#
51
RTSA#
50
DSRA#
49
CTSA#
48
VCC
47
STB#
46
AFD#
45
ERR#
44
INIT#
43
SLIN#
42
PD0
41
PD1
40
PD2
39
3
373
6
8
PD3
P
P
3
3
3
2
3 3
2
C A
S
S
U
E
S
C
O
C
T
P
L
V
S
V
E
K
B
B
C
N
I
A T
#
C
#
N
7
7
6
574
72829
P
L
S
L
L
L
L
V
D
D
I
M
D
D
R
R
V
V
D
D
E
E
N
N
0
1 / S M I #
/ G P 2 7
M
N
O
S
S
O
D
A
B
A
B
E
#
#
#
# X #
V
D
S
W
W
T
W
C
I
T
D
E
R
P
C
R
E
#
#
A
#
P #
# K 0 #
P
C
R D A T A #
V
H
D
C
D
E
M
L
E
S
E
K
A
K
#
I
D
C
N
#
H G #
A
S
I
R
R
D
S
C
Q
I
3
L
#
R
K
Q
L
L
S
PEB
A
P
P
P
A
A
A
C
F
R
L
D
D
D
C
2
1
0
3 V
U
R
E
C
S
A
S
T
Y
M
E
E
T
#
#
P
C
D
D
D
D
K
7
6
5
4
#
Publication Release Date: Jul 1999
- 6 - Revision 0.53
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O
- TTL level bi-directional pin with 12 mA source-sink capability
12t
I/O
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
12tp3
I/OD
- TTL level bi-directional pin open drain output with 12 mA sink capability
12t
I/O
- TTL level bi-directional pin with 24 mA source-sink capability
24t
OUT
- TTL level output pin with 12 mA source-sink capability
12t
OUT OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INcs - CMOS level Schmitt-trigger input pin INt - TTL level input pin INtd - TTL level input pin with internal pull down resistor INts - TTL level Schmitt-trigger input pin IN
- 3.3V TTL level output pin with 12 mA source-sink capability
12tp3
- 3.3V TTL level Schmitt-trigger input pin
tsp3
W83627HF/F
PRELIMINARY
1.1 LPC Interface
SYMBOL PIN I/O FUNCTION
CLKIN 18 INt System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
19 OD12 Generated PME event.
PME# PCICLK 21 IN
LDRQ# 22 O SERIRQ 23 I/OD LAD[3:0] 24-27 I/O
LFRAME# LRESET#
29 IN
30 IN
SUSCLKIN 75 INts 32khz clock input , for CIR only.
PCI clock input.
tsp3
Encoded DMA Request signal.
12tp3
12t
Serial IRQ input/Output.
These signal lines communicate address, control, and data
12tp3
information over the LPC bus between a host and a peripheral.
Indicates start of a new cycle or termination of a broken cycle.
tsp3
Reset signal. It can connect to PCIRST# signal on the host.
tsp3
Publication Release Date: Jul 1999
- 7 - Revision 0.53
W83627HF/F
PRELIMINARY
1.2 FDC Interface
SYMBOL PIN I/O FUNCTION
DRVDEN0 1 OD24 Drive Density Select bit 0. DRVDEN1 2 OD12 Drive Density Select bit 1. (Default) SMI# (IRQIN1) GP27
INDEX#
MOA#
DSB#
DSA#
MOB#
DIR#
STEP#
WD#
WE# TRAK0#
WP#
RDATA#
3 INcs This Schmitt-triggered input from the disk drive is active low when
4 OD24 Motor A On. When set to 0, this pin enables disk drive 0. This is
5 OD24 Drive Select B. When set to 0, this pin enables disk drive B. This
6 OD24 Drive Select A. When set to 0, this pin enables disk drive A. This
7 OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is
8 OD24 Direction of the head step motor. An open drain output.
9 OD24 Step output pulses. This active low open drain output produces a
10 OD24 Write data. This logic low open drain writes pre-compensation
11 OD24 Write enable. An open drain output.
13 INcs Track 0. This Schmitt-triggered input from the disk drive is active
14 INcs Write protected. This active low Schmitt input from the disk drive
15 INcs The read data input signal from the FDD. This input pin is pulled
In
t
I/OD12
System Management Interrupt (Interrupt channel input. For C version only) General purpose I/O port 3 bit 6.
the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
an open drain output.
is an open drain output.
is an open drain output.
an open drain output.
Logic 1 = outward motion Logic 0 = inward motion
pulse to move the head to another track.
serial data to the selected FDD. An open drain output.
low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
Publication Release Date: Jul 1999
- 8 - Revision 0.53
W83627HF/F
PRELIMINARY
1.2 FDC Interface, continued
SYMBOL PIN I/O FUNCTION
HEAD#
DSKCHG#
1.3 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SLCT 31 INt PRINTER MODE:
OD12
OD12
PE
OD12
16 OD24 Head select. This open drain output determines which disk drive
head is active. Logic 1 = side 0 Logic 0 = side 1
17 INcs Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
SYMBOL PIN I/O FUNCTION
An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WE2#
32 INt PRINTER MODE:
OD
This pin is for Extension FDD B; its function is the same as the
12
pin of FDC.
WE# EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the
An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the
WD# EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the
pin of FDC.
WE#
pin of FDC.
pin of FDC.
WD#
Publication Release Date: Jul 1999
- 9 - Revision 0.53
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
BUSY 33 INt
OD12
OD
PRINTER MODE: An active high input indicates that the printer is not ready to receive
data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the
MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2#
12
This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC.
ACK# 34 INt
OD12
OD
PRINTER MODE: ACK# An active low input on this pin indicates that the printer has
received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the
DSB# pin of FDC.
12
EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as
the DSB# pin of FDC.
ERR#
45
INt
OD12
OD12
PRINTER MODE: ERR# An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.
W83627HF/F
PRELIMINARY
Publication Release Date: Jul 1999
- 10 - Revision 0.53
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
SLIN# 43 OD12
OD12
OD12
PRINTER MODE: SLIN# Output line for detection of printer selection. Refer to the
description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.
INIT#
44 OD12
OD12
OD12
PRINTER MODE: INIT# Output line for the printer initialization. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.
AFD# 46 OD12
OD12
OD12
PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a
line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.
W83627HF/F
PRELIMINARY
Publication Release Date: Jul 1999
- 11 - Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
STB# 47 OD12 PRINTER MODE: STB#
An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
- EXTENSION FDD MODE: This pin is a tri-state output.
- EXTENSION 2FDD MODE: This pin is a tri-state output. 42 I/O
PD0
INt EXTENSION FDD MODE: INDEX2#
INt EXTENSION 2FDD MODE: INDEX2#
41 I/O
PD1
40 I/O
PD2
PRINTER MODE: PD0
12t
Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally.
This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally.
PRINTER MODE: PD1
12t
INt
INt
Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the
TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as
the TRAK0# pin of FDC. It is pulled high internally. PRINTER MODE: PD2
12t
INt
INt
Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the
WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as
the WP# pin of FDC. It is pulled high internally.
Publication Release Date: Jul 1999
- 12 - Revision 0.53
W83627HF/F
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
PD3
38 I/O
PD4
PD5
PD6
PD7
39 I/O
INt
INt
INt
INt
37 I/O
36 I/OD
OD12
35 I/OD
OD12
PRINTER MODE: PD3
12t
Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the
RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as
the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD4
12t
Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same
as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the
same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD5
12t
Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: This pin is a tri-state output.
-
EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6
12t
Parallel port data bus bit 6. Refer to the description of the parallel
-
port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC. PRINTER MODE: PD7
12t
Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.
Publication Release Date: Jul 1999
- 13 - Revision 0.53
1.4 Serial Port Interface
SYMBOL PIN I/O FUNCTION
CTSA# CTSB#
DSRA# DSRB#
RTSA#
HEFRAS
RTSB#
DTRA# PNPCSV#
DTRB# SINA
SINB SOUTA
PENKBC
SOUTB
PEN48
DCDA# DCDB# RIA# RIB#
49
78
50
79
51
During power-on reset, this pin is pulled down internally and is
80 I/O8t UART B Request To Send. An active low signal informs the
52
81
53
82
54
During power-on reset, this pin is pulled down internally and is
83
56
84
57
85
INt Clear To Send. It is the modem control input.
The function of these pins can be tested by reading bit 4 of the handshake status register.
INt Data Set Ready. An active low signal indicates the modem or data
set is ready to establish a communication link and transfer data to the UART.
I/O8t UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 4EH as configuration I/O port′s address)
modem or data set that the controller is ready to send data.
I/O8t UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is
defined as bit 0 ( (clear the default value of FDC, UARTs, PRT, Game port and MIDI port)
I/O8t UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
INt Serial Input. It is used to receive serial data through the
communication link.
I/O8t UART A Serial Output. It is used to transmit serial data out to the
communication link.
defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if intends to pull up. (enable KBC)
I/O8t UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is recommended if intends to pull up.
INt Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.
INt Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
PNPCSV#
PNPCSV#
, which provides the power-on value for CR24
). A 4.7 kΩ is recommended if intends to pull up.
W83627HF/F
PRELIMINARY
Publication Release Date: Jul 1999
- 14 - Revision 0.53
W83627HF/F
PRELIMINARY
1.5 KBC Interface
SYMBOL PIN I/O FUNCTION
KBLOCK# 58 INt Keyboard inhibit control input. This pin is after system reset.
Internal pull high. (KBC P17) A20GATE 59 O12 Gate A20 output. This pin is high after system reset. (KBC P21) KBRST 60 O12 Keyboard reset. This pin is high after system reset. (KBC P20)
KDATA 63 I/OD16 Keyboard Data. MDATA 66 I/OD16 PS2 Mouse Data. KCLK 62 I/OD16 Keyboard Clock. MCLK 65 I/OD16 PS2 Mouse Clock.
1.6 ACPI Interface
SYMBOL PIN I/O FUNCTION
VBAT 74 PWR Battery voltage input. PSOUT# 67 OD12 Panel Switch Output. This signal is used for Wake-Up system from
S5 PSIN 68 INtd Panel Switch Input. This pin is high active with an internal pull
down resistor.
state. This pin is pulse output, active low.
cold
1.7 Hardware Monitor Interface (For W83627HF only, all these pins in W83627F are NC.)
SYMBOL PIN I/O FUNCTION
CASEOPEN#
-5VIN 94 AIN 0V to 4.096V FSR Analog Inputs.
-12VIN 95 AIN 0V to 4.096V FSR Analog Inputs. +12VIN 96 AIN 0V to 4.096V FSR Analog Inputs. +3.3VIN 98 AIN 0V to 4.096V FSR Analog Inputs. VCOREB 99 AIN 0V to 4.096V FSR Analog Inputs. VCOREA 100 AIN 0V to 4.096V FSR Analog Inputs. VREF 101 AOUT Reference Voltage for temperature measuration. VTIN3 102 AIN Temperature sensor 3 input. It is used for CPU2 temperature
76 INt CASE OPEN. An active low input from an external device when
case is opened. This signal can be latched if pin VBAT is connect to battery, even W83627HF is power off.
measuration.
Publication Release Date: Jul 1999
- 15 - Revision 0.53
W83627HF/F
PRELIMINARY
1.7 Hardware Monitor Interface, continued
SYMBOL PIN I/O FUNCTION
VTIN2 103 AIN Temperature sensor 2 input. It is used for CPU1 temperature
measuration.
VTIN1 104 AIN Temperature sensor 1 input. It is used for system temperature
measuration.
OVT# 105 OD12 Over temperature Shutdown Output. It indicated the VTIN2 or
VTIN3 is over temperature limit.
VID[4:0] 106-
110
FANIO[3:1] 111-
113
FANPWM1 FANPWM2
BEEP
116 115 118 OD12 Beep function for hardware monitor. This pin is low after system
INt Voltage Supply readouts from Pentium II .
I/O
0V to +5V amplitude fan tachometer input.
12ts
Alternate Function: Fan on-off control output. These multifunctional pins can be programmable input or output.
O12
Fan speed control. Use the Pulse Width Modulatuion ( technic knowledge to control the Fan's RPM.
reset.
PWM
)
1.8 Game Port & MIDI Port
SYMBOL PIN I/O FUNCTION
GPSA1 GP10 P12 I/OD12 Alternate Function Output:KBC P12 I/O port. GPSB1 GP11 P13 I/OD12 Alternate Function Output:KBC P13 I/O port. GPX1
GP12 P14 I/OD12 Alternate Function Output:KBC P14 I/O port.
128 INcs
I/OD12
127 INcs
I/OD12
126 I/OD12
I/OD12
Active-low, Joystick I switch input 1. (Default)
General purpose I/O port 1 bit 0.
Active-low, Joystick II switch input 1. (Default)
General purpose I/O port 1 bit 1.
Joystick I timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 2.
Publication Release Date: Jul 1999
- 16 - Revision 0.53
1.8 Game Port & MIDI Port, continued
SYMBOL PIN I/O FUNCTION
W83627HF/F
PRELIMINARY
GPX2
GP13 P15 I/OD12 Alternate Function Output:KBC P15 I/O port. GPY2
GP14 P16 I/OD12 Alternate Function Output:KBC P16 I/O port. GPY1 123 I/OD12 Joystick I timer pin. this pin connect to Y positioning variable
GP15
GPSB2 122 INcs Active-low, Joystick II switch input 2. This pin has an internal pull-
GP16
GPSA2 121 INcs Active-low, Joystick I switch input 2. This pin has an internal pull-
GP17 I/OD12 General purpose I/O port 1 bit 7. MSI
GP20 MSO
IRQIN0
125 I/OD12
I/OD12
124 I/OD12
I/OD12
I/OD12 General purpose I/O port 1 bit 5.
I/OD12 General purpose I/O port 1 bit 6.
119 INt
I/OD
120 OUT
INt
Joystick II timer pin. this pin connect to X positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 3.
Joystick II timer pin. this pin connect to Y positioning variable
resistors for the Josystick. (Default)
General purpose I/O port 1 bit 4.
resistors for the Josystick. (Default)
up resistor. (Default)
up resistor. (Default)
MIDI serial data input .(Default)
General purpose I/O port 2 bit 0.
12t 12t
MIDI serial data output. (Default)
Alternate Function input: Interrupt channel input.
Publication Release Date: Jul 1999
- 17 - Revision 0.53
1.9 General Purpose I/O Port
1.9.1 General Purpose I/O Port 1 (Power source is Vcc) see 1.8 Game Port
1.9.2 General Purpose I/O Port 2 (Power source is Vcc) SYMBOL PIN I/O FUNCTION
W83627HF/F
PRELIMINARY
GP20
MSI
GP21 (SCL) GP22 (SDA)
GP23 PLED
119 I/OD
INt
92 I/OD
IN
91 I/OD
I/OD
90 I/OD
OD GP24 89 I/OD WDTO OD GP25 IRRX GP26 IRTX GP27 DRVDEN1 IRQIN1
88 I/OD
IN
87 I/OD
OUT
2 I/OD
OD
IN
General purpose I/O port 2 bit 0.
12t
MIDI serial data input. Schmitt trigger input with internal pull-up register. (Default) General purpose I/O port 2 bit 1.
12t
(Alternate Function: Serial Bus Clock. For W83627HF Only)
ts
General purpose I/O port 2 bit 2.
12t
12ts
(Alternate Function: Serial Bus bi-directional Data. For W83627HF Only) General purpose I/O port 2 bit 3.
24t
24t
Power LED output, this signal is low after system reset. (Default)
General purpose I/O port 2 bit 4.
12t
Watch dog timer output. (Default)
12t
General purpose I/O port 2 bit 5.
12t
Alternate Function Input: Infrared Receiver input. (Default)
ts
General purpose I/O port 2 bit 6.
12t
Alternate Function Output: Infrared Transmitter Output. (Default)
12t
General purpose I/O port 2 bit 7.
24t
Drive Density Select bit 0. (Default)
24t
Alternate Function Input: Interrupt channel input.
t
Publication Release Date: Jul 1999
- 18 - Revision 0.53
W83627HF/F
PRELIMINARY
1.9.3 General Purpose I/O Port 3 (Power souce is VSB) SYMBOL PIN I/O FUNCTION
GP30 73 I/OD SLP_SX# INt Chpset suspend C status input. GP31 72 I/OD
PWRCTL# OD
GP32 71 I/OD
PWROK OD
GP33 70 I/OD
RSMRST# OD
GP34 69 I/OD
CIRRX# OD
GP35 64 I/OD
SUSLED OD
1.10 POWER PINS
SYMBOL PIN FUNCTION
VCC 12, 48, 77, 114 +5V power supply for the digital circuitry. VSB 61 +5V stand-by power supply for the digital circuitry.
VCC3V 28 +3.3V power supply for driving 3V on host interface.
AVCC 97 Analog VCC input. Internally supplier to all analog circuitry. AGND 93 Internally connected to all analog circuitry. The ground reference
VSS 20, 55, 86, 117 Ground.
12t
General purpose I/O port 3 bit 0.
General purpose I/O port 3 bit 1.
12t
This pin generates the PWRCTL# signal while the power failure.
12t
(Default)
General purpose I/O port 3 bit 2.
12t
This pin generates the PWROK signal while the VCC come in.
12t
(Default)
General purpose I/O port 3 bit 3.
12t
This pin generates the RSMRST signal while the VSB come in.
12t
(Default)
General purpose I/O port 3 bit 4.
12t
Consumer IR receiving input. This pin can Wake-Up system from
12t
S5
General purpose I/O port 3 bit 5.
24t
Suspend LED output, it can program to flash when suspend state.
24t
cold.
(Default)
This function can work without VCC. (Default)
for all analog inputs..
Publication Release Date: Jul 1999
- 19 - Revision 0.53
W83627HF/F
PRELIMINARY
2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of the interface implemented in Winbond LPC I/O are:
One control line, namely LFRAME#, which is used by the host to start or stop transfers. No peripherals drive this signal.
The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type, cycle direction, chip selection, address, data, and wait states.
MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in Winbond LPC I/O.
An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization.
DMA requests are issued through LDRQ#.
Interrupt requests are issued through SERIRQ.
Power management events are issued through PME#.
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts (see table below) free for integrating more devices on a single chip.
Winbond I/O
W83977TF D[7:0], SA[15:0], DRQ[3:0], DACK#[3:0], TC, IOR#, IOW#, IOCHRDY, IRQs 49
W83627HF LAD[3:0], LFRAME#, PCICLK, LDRQ#, SERIRQ, PME# 9
save 40
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration.
Interface pins count
Publication Release Date: Jul 1999
- 20 - Revision 0.53
Loading...
+ 155 hidden pages