Winbond Electronics W83626F, W83626D Datasheet
Winbond W83626F
LPC-to-ISA Bridge
W83626F/W83626D
W83626F/W83626D Data Sheet Revision History
Pages Dates Version
1 n.a. 02/25/00 0.50 0.50 First published.
2
3
4
5
6
7
8
9
Version
on Web
Main Contents
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.
Publication Release Date:Feb. 2000
-I - Preliminary Revision 0.50
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
GENERAL DESCRIPTION
W83626F/W83626D is a transparent LPC-to-ISA bus conversion IC.
For the new generation Intel chipset Camino and Whitney, SiS Super South 960,
featuring LPC bus, there is no support for ISA bus and slots. However the demand of
ISA devices still exist. For such case, W83626F is the best companion solution for the
non-ISA chipset. Also the packages of W83626F had been chosen to be the most
economic solution for save the M/B board layout size and cost.
For the new generation chipset featuring LPC interface and support no ISA bus,
W83627HF (Winbond LPC I/O) together with the set of W83626F is the complete
solution.
FEATURES
LPC to ISA Bridge
•
Meet LPC Spec. 1.1
•
Support LDRQ# (LPC DMA), SERIRQ (serial IRQ)
•
Full ISA Bus Support except ISA Bus Masters
•
5V ISA and 3.3V LPC interfaces
•
All Software Transparent
•
IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ
Supports 3 fully ISA Compatible Slots without Buffering
•
•
LPC Bus at 33MHz
•
Supports Programmable ISA Bus Divide the PCI Clock into 3 or 4
•
All ISA Signals can be Isolate
•
14.318MHz in to generate two 14.318MHz buffer out and one 24.576MHz
•
Specific Keyboard Functions supported
Support 8 programmable general purpose I/O pins
•
Supports Configuration registers for programming performance
•
PACKAGE
• 128-pin PQFP for W83626F
Publication Release Date: Feb 2000
- 1 - Revision 0.50
Block diagram OF W83626F
LFRAM#
PCIRST#
LAD[3:0]
PCICLK
LDRQ#
SERIRQ
ISOLATE#
3.3V
5V
Interface
Signal
Isolation
Control
Power
SuppIy
LPC
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
SA[19:0]
SD[15:0]
BALE
AEN
IOCHRDY
IOCS16#
IOCHK#
ISA
Interface
IOR#
IOW#
LA[23:17]
SBHE#
MEMCS16#
MEMR#
MEMW#
SMEMR#
SMEMW#
ZEROWS#
MASTER#
REFRESH#
ROMCS#
RSTDRV
SYSCLK
IRQ[3:7,9:12,14,15]
DRQ[0:3,5:7]
DACK[0:3,5:7]
14.318M
CLOCK
GEN. / BUF.
- 2 - Revision 0.50
14MOUT1
14MOUT2
24.576M
Publication Release Date: Feb 2000
PIN CONFIGURATION FOR 626F
TC
BALE
IRQ3
IRQ4
DACK2#
SBHE#
IRQ5
GND
IRQ6
IRQ7
REFRESH#
SYSCLK
DACK1#
DRQ1
IOR#
DACK3#
DRQ3
VCC5
IOW#
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
SD0
SD1
SD2
VCC5
SD3
SD5
SD4
SD6
SD7
IOCHCK#
IRQ9
OWS#
GND
SMEMW#
DRQ2
SMEMR#
RSTDRV
GPIO6/RTCCS#
GPIO7/IOHCS#
MEMR#
MEMW#
MASTER#/RTCEN
DACK7#
DACK6#/HEFRAS
LA23
LA22
VCC5
LA21
LA20
LA19
LA18
GND
LA17
SD8
SD9
SD10
SD11
SD12
SD13
VCC5
SD14
SD15
DRQ7
GND
DRQ6
1
0101099
2 1
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1 2 3 4 5 6 7 8 9
DRQ5
989
0
DRQ0
DACK5#
DACK0#
969594939
7
9
1
2
9089888
868
7
8
4838281
5
8
07978777675
W83626F
LPC to ISA
101112131415161718192021222324252627282930313233343536373
GND
LAD3
LAD2
LAD1
PCIRST#
LAD0
VCC3
LDRQ#
PCICLK
SERIRQ
AVCC3
14.318M
PWRDN#
14MOUT1
VCC5
IRQ14
IRQ15
IRQ12
IRQ11
IRQ10
LFRAM#
IOCS16#
MEMCS16#
747
7
7
1
2
3
SA0
AGND
24.576M
14MOUT2
706
SA1
9
SA2
6
867
SA3
6
6
6
5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
8
SA4
ROMCS#
GPIO0/IRQ1
80PCS#/KBEN#
GPIO5/IRQ8
GPIO4/PLED
GPIO3/IRQIN
IOCHRDY
GND
AEN
SA19
SA18
SA17
VCC5
SA16
SA15
SA14
SA13
GND
SA12
SA11
SA10
SA9
VCC5
SA8
SA7
SA6
SA5
GPIO2/MCCS#
GPIO1/KBCS#
Publication Release Date: Feb 2000
- 3 - Revision 0.50
1. PIN DESCRIPTION
I/O
- TTL level bi-directional pin with 12 m A source-sink capability
12t
I/O
- TTL level bi-directional pin with 24 m A source-sink capability
24t
I/O
- 3.3V TTL level bi-directional pin with 12 m A source-sink capability
12tp3
I/O
- 3.3V TTL level bi-directional pin with 24 m A source-sink capability
24tp3
I/O
- TTL level bi-directional pin open drain output with 12 m A sink capability
D12t
I/O
- TTL level bi-directional pin with 24 m A source-sink capability
24t
OUT12 - TTL level output pin with 12 m A source-sink capability
OUT24 - TTL level output pin with 24 m A source-sink capability
O
- 3.3V TTL level output pin with 12 m A source-sink capability
12p3
O
- 3.3V TTL level output pin with 24 m A source-sink capability
24p3
O
- Open-drain output pin with 12 m A sink capability
D12
O
- Open-drain output pin with 24 m A sink capability
D24
INcs - CMOS level Schmitt-trigger input pin
INt - TTL level input pin
INtd - TTL level input pin with internal pull down resistor
INtu - TTL level input pin with internal pull up resistor
INts - TTL level Schmitt-trigger input pin
IN
- 3.3V TTL level Schmitt-trigger input pin
tsp3
W83626F PIN DESCRIPTION
LPC Interface
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
SYMBOL PIN I/O FUNCTION
LAD[3:0] 16-19 I/O
These signal lines communicate address, control and data
12tp3
information over the LPC bus between a host and a peripheral.
LFRAME# 13 IN
PCICLK
21
PCIRST# 14 IN
SERIRQ 23 I/O
LDRQ# 22 O
Indicates start of a new cycle or termination of a broken cycle.
tsp3
PCICLK provides timing for all transactions on the LPC bus. All
INt
tsp3
D12t
12tp3
LPC signals are sampled on the rising edge of PCICLK, and all
timing parameters are defined with respect to this edge.
Reset signal. It can connect to PCIRST# signal on the host.
Serial IRQ Input/Output.
Encoded DMA Request signal.
Publication Release Date: Feb 2000
- 4 - Revision 0.50
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
LPC Interface, continued
SYMBOL PIN I/O FUNCTION
PWRDN# 24 INtu Power Down. The signal is active low according to CR 44 Bit 7and
wake-up enable by hardware setting. There are eight different
power-down states (Power down Mode 3).
ISA Interface Signals
SYMBOL PIN I/O FUNCTION
SA[19:17] 58-56 OUT24 System Address Bus. These are the upper address lines that
define the ISA’s byte granular address space (up to 1 M byte).
SA[19:17] are at an unknown state upon PCIRST#.
SA[16:0] 54-51
SD[15:0] 122-1
AEN 59 OUT24 Address Enable. AEN is asserted during DMA cycles. This signal
IOR# 86 OUT24 I/O Read. IOR# is the command to an ISA I/O slave device that the
IOW# 84 OUT24 I/O Write. IOW# is the command to an ISA I/O slave device that
IOCHRDY
SYSCLK 92 OUT24 ISA System Clock. SYSCLK is the reference clock for the ISA
RSTDRV
IOCS16# 11 INt 16-bit I/O Chip Select. This signal is driven by I/O devices on the
49-46
44-41
35-31
21
119-1
14
75-71
69-67
61
77 OUT24
OUT24 System Address Bus. These are the bi-directional lower address
lines that define the ISA’s byte granular address space (up to 1 M
byte). SA[16:0] are at an unknown state upon PCIRST#.
OUT24 System Data. SD[15:0] provide the 16-bit data path for devices
residing on the ISA Bus. The W83626F tri-states SD[15:0] during
PCIRST#.
is also driven high during W83626F initiated refresh cycles. AEN is
driven low upon PCIRST#.
slave may drive data on to the ISA data bus (SD[15:0]).
the slave may latch data from the ISA data bus (SD[15:0]).
INt
I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY
to indicate that additional time (wait states) is required to complete
the cycle.
bus. The SYSCLK is generated by dividing PCICLK by 3 or 4.
Reset Drive. W83628F asserts RSTDRV to reset devices that
reside on the ISA Bus. The W83628F asserts this signal while the
PCIRST# is asserted.
ISA Bus to indicate that they support 16-bit I/O bus cycles.
Publication Release Date: Feb 2000
- 5 - Revision 0.50
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
ISA Interface Signals , continued
SYMBOL PIN I/O FUNCTION
MEMCS16# 12 INt
IOCHCK# 76 INt I/O Channel Check. IOCHK# can be driven by any resource on
OWS# 81 INt
LA[23:17]
SMEMW# 82 OUT24
SMEMR# 83 OUT24
REFRESH# 91 OUT24
BALE 101 OUT24
SBHE# 102 OUT24 System Byte High Enable. SBHE# asserted indicates that a byte
MEMR# 112 OUT24
MEMW# 113 OUT24
MASTER#
RTCEN#
IRQ3 98
103-1
04
106-1
09
111
123 INt
OUT24
INt Parallel Interrupt Requested Input 3.
Memory Chip Select 16. MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
the ISA bus during on detection of an error.
Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate that
the current cycle can be executed as an ISA zero wait state cycle.
ZEROWS# has no effect during 16-bit I/O cycles.
Unlatched Address. The LA[23:17] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
Standard Memory Write. SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address below
1 Mbyte.
Standard Memory Read. SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address below
1 Mbyte.
Refresh. REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83626F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
Bus Address Latch Enable. BALE is an active high signal
asserted by the W83626F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
is being transferred on the upper byte (SD[15:8]) of the data bus.
SBHE# is at an unknown state upon PCIRST#.
Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write. MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER#. This signal is used with a DREQ line by an ISA master
to gain control of the ISA Bus.
RTC Function Enable.The pin applies a pull-down resistor (4.7K
ohm) to enable RTC functions ( RTCCS#,and IRQ8)
Publication Release Date: Feb 2000
- 6 - Revision 0.50
LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
ISA Interface Signals , continued
SYMBOL PIN I/O FUNCTION
IRQ4 97
IRQ5 96
IRQ6 94
IRQ7 93
IRQ9 78
IRQ10 10
IRQ11 9
IRQ12 8
IRQ14 6
IRQ15 7
DRQ0 3
DRQ1 90
DRQ2 79
DRQ3 88
DRQ5 1
DRQ6 127
DRQ7 124
DACK0# 4 OUT24 DMA Acknowledge 0. The DACK# signal indicates that either a
DACK1# 89 OUT24 DMA Acknowledge 1.
DACK2# 99 OUT24 DMA Acknowledge 2.
DACK3# 87 OUT24 DMA Acknowledge 3.
DACK5# 2 OUT24 DMA Acknowledge 5.
DACK6#
HERFRA
DACK7# 126 OUT24 DMA Acknowledge 7.
TC 100 OUT24 Terminal Count. The W83628F asserts TC to DMA slaves as a
127 I/O
INt Parallel Interrupt Requested Input 4.
INt Parallel Interrupt Requested Input 5.
INt Parallel Interrupt Requested Input 6.
INt Parallel Interrupt Requested Input 7.
INt Parallel Interrupt Requested Input 9.
INt Parallel Interrupt Requested Input 10.
INt Parallel Interrupt Requested Input 11.
INt Parallel Interrupt Requested Input 12.
INt Parallel Interrupt Requested Input 14.
INt Parallel Interrupt Requested Input 15.
INt
INt
INt
INt
INt
INt
INt
D24t
DMA Request 0. The DREQ signal indicates that either a slave
DMA device is requesting DMA services, or an ISA bus master is
requesting use of the ISA bus.
DMA Request 1.
DMA Request 2.
DMA Request 3.
DMA Request 5.
DMA Request 6.
DMA Request 7.
DMA channel or an ISA bus master has been granted the ISA bus.
DMA Acknowledge 6.
During power-on reset,this is pulled-hi internally(Select 4Eh) and
is defined as HEFRAS which provides the power-on value for
CR3 bit4 .A 4.7k ohm is recommended if intends to pull down
.(Select 2Eh)
terminal count indicator.
Publication Release Date: Feb 2000
- 7 - Revision 0.50
LPC TO ISA BRIDGE SET
K/B , GPIO AND 80h PCS# Function
SYMBOL PIN I/O FUNCTION
80PCS#
KBEN#
ROMCS# 37 I/O
GPIO0
IRQ1
GPIO1
KBCS#
GPIO2
MCCS#
GPIO3
IRQIN
GPIO4
PLED
GPIO5
IRQ8
GPIO6
RTCCS#
GPIO7
IOHCS#
36 I/O
38 I/O
39 I/O
40 I/O
62 I/O
63 I/O
64 I/O
65 I/O
66 I/O
80h PORT Chip Select.(Default)
D12t
K/B Functions Enable. During power-on reset this pin is weak
pulled-up internally. The pin applied a pull-down resistor (4.7K
ohm) to enable K/B functions. (IRQ1,KBCS#,and MCCS#)
ROMCS#, this pin enable positive decoder of BIOS address range
D12t
D12t
D12t
D12t
D12t
D12t
D12t
D12t
[depend on CR03 ,bit 1 or external weak pulled-up during PCIRST
is asserted] .
General purpose I/O pin 0.
Parallel Interrupt Requested Input 1. This interrupt request is used
for specific K/B functions.
General purpose I/O pin 1.
12t
Decode the address 60h and 64h to output chip selected signal.
Enable by KBEN# power-on setting.
General purpose I/O pin 2.
Decode the address 62h and 66h to output chip selected signal
Enable by KBEN# power-on setting
General purpose I/O pin 3.
Programmable parallel IRQ input transfers to serial IRQ
Enable by KBEN# power-on setting
General purpose I/O pin 4.
Power LED output, this signal is low after system reset.
General purpose I/O pin 5.
Parallel Interrupt Requested Input 8. This interrupt request is used
for specific RTC functions. Enable by RTCEN# power-on setting
General purpose I/O pin 6.
Decode the address 70h and 71h to output chip selected signal
Enable by RTCEN# power-on setting
General purpose I/O pin 7.
Decode SA[15-11] are all 0 and setting by CR04 Bit 6.
W83626F/W83626D
PRELIMINARY
Publication Release Date: Feb 2000
- 8 - Revision 0.50
LPC TO ISA BRIDGE SET
64 and 65 will do IRQ8 and RTCCS#
W83626F/W83626D
Clock Buffer and Generator
SYMBOL PIN I/O FUNCTION
14.318M 26 INt Main 14.318 MHz Clock Input.
14MOUT 1 27 OUT
14MOUT 2 28 OUT
24.576M
25.000M
Power Signals
SYMBOL PIN I/O FUNCTION
VCC5 5, 45, 55, 70, 85, 105, 120, PWR Digital 5V Supply.
VCC3 20 PWR Digital 3.3V Supply.
GND 15, 50, 60, 80, 95, 110, 125 PWR Digital Ground.
AVCC3 25 PWR Analog 3.3V Supply.
AGND 30 PWR Analog Ground.
Power-on strapping Signals
SYMBOL PIN I/O FUNCTION
80PCS#/KBEN# 36 I/O
ROMCS# 37 I/O
MASTER/RTCEN# 123 INt
29 OUT
14.318 MHz Buffer Output 1.
12t
14.318 MHz Buffer Output 2.
12t
This pin is weak pull-up during 3 VDD ramp-up period. The default
12t
setting is 24.576 MHz and selected 25.000 MHz by external
pull-down with 4.7K ohm (recommended) during power ramp-up
period.
24.576 MHz Clock Output for Audio Codec or selected 25.000
MHz Clock Output for LAN on board solution.
D12t
D12t
Power-on strapping with
pulled-down register will enable
K/B and mouse functions. When it
is set, pin 38 , 39 and 40 will do
IRQ1, KBCS# and MCCS# signals.
If there is a boot-ROM (BIOS) ,the
signal must power-on with a weak
pulled-high register.
Power-on strapping with
pulled-down register will enable
RTC functions. When it is set, pin
PRELIMINARY
DACK6#/HEFRAS 128 I/O
signals.
D24t
- 9 - Revision 0.50
Set this function will change the
port that is used to access
configuration-registers . Default
setting is 4Eh ,but by power-on
strapping with a pulled-down
register change to 2Eh.
Publication Release Date: Feb 2000
Loading...