Winbond Electronics W83194R-67B Datasheet

W83194R-67B

100MHZ 3-DIMM CLOCK FOR VIA MVP4

1.0 GENERAL DESCRIPTION

The W83194R-67B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67B provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67B also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.

The W83194R-67B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.

High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

•

Supports Pentium , AMD, Cyrix CPU with I2C.

•

4 CPU clocks (one free-running CPU clock)

•

13 SDRAM clocks for 3 DIMs

•

6 PCI synchronous clocks

•

Optional single or mixed supply:

(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =

3.3V, VddL1 = VdqL2 = 2.5V)

• < 250ps skew among CPU and SDRAM clocks

•

< 4ns propagation delay SDRAM from buffer input

•

Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.

•

Smooth frequency switch with selections from 60 MHz to 124 MHz CPU

•

I2C 2-Wire serial interface and I2C read back

•

0~0.5% down type or ±0.25% or ±0.5% spread spectrum function to reduce EMI

•

Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• 2ms power up clock stable time

•

MODE pin for power Management

•

One 48 MHz for USB & one 24 MHz for super I/O

•

Packaged in 48-pin SSOP

Publication Release Date: Dec. 1999

- 1 - Revision 0.50

3.0 BLOCK DIAGRAM

W83194R-67B

PRELIMINARY

Xin

Xout

BUFFER IN

4

FS(0:3)*

MODE*

*CPU_STOP#

*PCI_STOP#

SDATA*

SDCLK*

4.0 PIN CONFIGURATION

PLL2

~

XTAL
OSC

PLL1

Spread
Spectrum

LATCH

POR

Control

Config.

~

Logic

Reg.

48MHz

1/2

STOP

STOP

4

PCI

STOP

Clock
Divider

24MHz

REF(0:1)

2

CPUCLK_F

CPUCLK(0:2)

3

SDRAM_F
SDRAM(0:11)

12

PCICLK(0:4)

5

PCICLK_F

* PCI_STOP#/REF0

PCICLK_F/ *MODE

Vddq1

Vss
Xin

Xout

Vddq2

PCICLK0/ *FS3

Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4

Vddq2

BUFFER IN

Vss
SDRAM11
SDRAM10

Vddq3
SDRAM 9
SDRAM 8

Vss

*SDATA

*SCLK

1
2
3
4
5
6

7
8
9
10
11
12

13
14
15

16

17
18
19
20

21

22
23
24

48
47
46
45
44
43
42
41
40
39
38

37
36
35
34
33
32
31
30
29
28
27

26
25

REF1/ *FS2
VddL1
CPUCLK_F
CPUCLK0
Vss

CPUCLK1

CPUCLK2
*CPU_STOP#

Vss
SDRAM_F
SDRAM 0

SDRAM 1
Vddq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vddq4
48MHz/ *FS0
24MHz/ *FS1

Publication Release Date: Dec.. 1999

- 2 - Revision 0.50

W83194R-67B

PCICLK0/*FS3

Low skew (< 250ps) PCI clock outputs. Synchronous

PRELIMINARY

5.0 PIN DESCRIPTION

IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up

5.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 4 IN Crystal input with internal loading capacitors and

feedback resistors.

Xout 5 OUT Crystal output at 14.318MHz nominally.

5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK_F 46 OUT Free running CPU clock. Not affected by

CPUCLK[0:2] 45,43,42 OUT Low skew (< 250ps) clock outputs for host

*CPU_STOP# 41 IN This asynchronous input halts CPUCLK[0:2] and

SDRAM_F 39 OUT Free running SDRAM clock. Not affected by

SDRAM [ 0:11] 17,18,20,21,28

,29,31,32,34,

35,37,38
PCICLK_F/
*MODE

PCICLK [ 1:4 ]

BUFFER IN 15 IN Inputs to fanout for SDRAM outputs.

7 I/O Free running PCI clock during normal operation.

8 I/O Low skew (< 250ps) PCI clock outputs.

10,11,12,13 OUT

CPU_STOP#

frequencies such as CPU, Chipset and Cache.
Powered by VddL2. Low if CPU_STOP# is low.

SDRAM(0:11) at logic level when driven low.

CPU_STOP#

OUT SDRAM clock outputs. Fanout buffer outputs from

BUFFER IN pin.(Controlled by chipset)

Latched Input. Mode=1, Pin 2 is REF0; Mode=0,
Pin2 is PCI_STOP#

Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

to CPU clocks with 1/-4ns skew(CPU early).

Publication Release Date: Dec.. 1999

- 3 - Revision 0.50

W83194R-67B

control interface with internal

PRELIMINARY

5.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

*SDATA 23 I/O Serial data of I2C 2-wire

*SDCLK 24 IN Serial clock of I2C 2-wire control interface with

5.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

REF0 / *PCI_STOP# 2 I/O 14.318MHz reference clock. This REF output is the

REF1 / *FS2 48 I/O 14.318MHz reference clock.

24MHz / *FS1 25 I/O 24MHz output clock.

48MHz / *FS0 26 I/O 48MHz output for USB during normal operation.

5.5 Power Pins

pull-up resistor.

internal pull-up resistor.

stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input

low (In mobile mode. MODE=0)

Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

SYMBOL PIN FUNCTION

Vddq1 1 Power supply for Ref [0:1] , Xin and Xout crystal.
VddL1 47 Power supply for CPU clock outputs, either 2.5V or

3.3V.
Vddq2 6, 14 Power supply for PCICLK_F, PCICLK[1:4], 3.3V.
Vddq3 19, 30, 36 Power supply for SDRAM_F,SDRAM[0:11], and PLL

core, nominal 3.3V.
Vddq4 27 Power for 24 & 48MHz output buffers and PLL core.
Vss 3,9,16,22,33,40,44 Circuit Ground.

Publication Release Date: Dec.. 1999

- 4 - Revision 0.50

W83194R-67B

PRELIMINARY

6.0 FREQUENCY SELECTION

FS3 FS2 FS1 FS0 CPU,SDRAM(MHz) PCI(MHz) REF,IOAPIC (MHz)

1 1 1 1 60 30(CPU/2)
1 1 1 0 66.8 33.4(CPU/2)
1 1 0 1 70 35(CPU/2)
1 1 0 0 90 30(CPU/3)

1 0 1 1 97.0 32.33(CPU/3)

1 0 1 0 83.3 27.77(CPU/3)
1 0 0 1 95.25 31.75(CPU/3)
1 0 0 0 100.2 33.3(CPU/3)

0 1 1 1 75 37.5(CPU/2)
0 1 1 0 80 40(CPU/2)
0 1 0 1 83.3 41.65(CPU/2)
0 1 0 0 105 35(CPU/3)
0 0 1 1 110 36.67(CPU/3)
0 0 1 0 115 38.33(CPU/3)

0 0 0 1 124 31(CPU/4)
0 0 0 0 133 33.3(CPU/4)

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

7.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL

MODE, Pin7 (Latched Input) PIN 2

0 PCI_STOP# (Input)
1 REF0 (Output)

Publication Release Date: Dec.. 1999

- 5 - Revision 0.50

8.0 FUNCTION DESCRIPTION

W83194R-67B

PRELIMINARY

8.1 POWER MANAGEMENT FUNCTIONS

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO? to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#), when
MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire
serial control interface and one of these pins indicate that it should be enable.

The W83194R-67B may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.

CPU_STOP# PCI_STOP# CPUCLK 0:2,

SDRAM 0:11

PCI SDRAM_F,

CPU_F,PCI_F

OTHER CLKs

0 0 LOW LOW RUNNING RUNNING
0 1 LOW RUNNING RUNNING RUNNING
1 0 RUNNING LOW RUNNING RUNNING
1 1 RUNNING

RUNNING

RUNNING

RUNNING

8.2 2-WIRE I2C CONTROL INTERFACE

The clock generator is a slave I2C component which can be read back? The data stored in the
latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2­wire control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-67B initializes with default register settings, and then it is optional to use the 2-wire control
interface.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I2C registers after the string of data. The sequence order is as
follows:

Publication Release Date: Dec.. 1999

- 6 - Revision 0.50