Winbond Electronics W83194R-630A Datasheet
W83194R-630A
166MHZ CLOCK FOR SIS CHIPSET
1. GENERAL DESCRIPTION
The W83194R-630A is a Clock Synthesizer for SiS 540/630 chipset. W83194R-630A provides all
clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium,
Pentium II and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are
externally selectable with smooth transitions. The W83194R-630A makes SDRAM in synchronous or
asynchronous frequency with CPU clocks.
The W83194R-630A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and W83194R-630A provides the 0.5%, 0.75% center type and 0~0.5% down type
spread spectrum to reduce EMI.
The W83194R-630A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
• Supports Pentium, Pentium II, AMD and Cyrix CPUs with I2C.
• 3 CPU clocks
• 14 SDRAM clocks for 3 DIMMs
• 7 PCI synchronous clocks.
• Optional single or mixed supply:
(All Vdd = 3.3V) or (Other s Vdd = 3.3V, VddLCPU=2.5V)
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
• SDRAM frequency synchronous or asynchronous to CPU clocks
• Smooth frequency switch with selections from 66 to 166mhz
• I2C 2-Wire serial interface and I2C read back
• 0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
Publication Release Date: Nov. 1999
- 1 - Revision 0.65
3. BLOCK DIAGRAM
W83194R-630A
PRELIMINARY
Xin
Xout
4
*FS(0:3)
*MODE
SEL3.3_2.5#
CPU_STOP#
PCI_STOP#
PD#
*SDATA
*SCLK
4. PIN CONFIGURATION
Vdd
REF0X2/ *FS3
PCICLK_F/ *FS1
PCICLK1/ *FS2
PCICLK2/*MODE
SDRAM 0/CPU_STOP#
SDRAM 1/PCI_STOP#
SDRAM 2/PD#
Vss
Xin
Xout
VddP
Vss
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VddP
Vss
VddSD
SDRAM 3
Vss
*SDATA
*SDCLK
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
LATCH
POR
Control
Logic
Config.
Reg.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
5
¡Ò
2
CPU_STOP#
PCI
clock
Divder
PCI_STOP#
STOP
STOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48MHz
24_48MHz
REF(0:1)
2
CPUCLK(0:2)
3
SDRAM(0:13)
14
PCICLK(0:6)
7
REF1
VddLCPU
CPUCLK_F
CPUCLK0
Vss
CPUCLK1
VddSD
SDRAM12
SDRAM_F
Vss
SDRAM11
SDRAM 10
VddSD
SDRAM 9
SDRAM 8
Vss
SDRAM 7
SDRAM 6
VddSD
SDRAM 5
SDRAM 4
VddSD
48MHz/*FS0
24_48MHz/SEL2.5_3.3#
Publication Release Date: Nov. 1999
- 2 - Revision 0.65
W83194R-630A
PRELIMINARY
5. PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN Crystal input with internal loading capacitors and
feedback resistors.
Xout 5 OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL PIN I/O FUNCTION
CPUCLK_F 46 OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
This pin will not be stopped by CPU_STOP#
CPUCLK [ 0:1 ] 45,43 OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
SDRAM_F 40 OUT SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
This pin will not be stopped by CPU_STOP#
SDRAM0/CPU_STOP#
SDRAM1/PCI_STOP#
SDRAM2/PD# 20 I/O SDRAM clock outputs which have syn. or asyn.
SDRAM[3:12]
PCICLK_F/ *FS1 7 I/O Latched input for FS1 at initial power up for H/W
17 I/O SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
CPU_STOP# input pin when MODE=0.
18 I/O SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
PCI_STOP# input pin when MODE=0.
frequencies as CPU clocks.
PD# input pin when MODE=0.
21,28,29,31,32
,34,35,37,38,
41
OUT SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Publication Release Date: Nov. 1999
- 3 - Revision 0.65
W83194R-630A
PRELIMINARY
PCI free-running clock during normal operation.
PCICLK 1/ *FS2 8 I/O Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
PCICLK 2/ *MODE 9 I/O Latched input for MODE at initial power up for input
selection of CPU_STOP#, PCI_STOP# and PD#.
When MODE=1, the above pins are SDRAM clock
outputs. When MODE=0, the pins are inputs ACPI
pins.
PCI clock during normal operation.
PCICLK [ 3:6 ] 11,12,13,14 OUT Low skew (< 250ps) PCI clock outputs.
5.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
*SDATA 23 I/O Serial data of I2C 2-wire control interface
*SDCLK 24 IN Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
REF0X2 / *FS3 2 I/O 3.3V, 14.318MHz reference clock output .
Internal 250kΩ pull-up.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
REF1 48 I/O 3.3V , 14.318MHz reference clock output.
24_48MHz/
SEL2.5_3.3#
48MHz / *FS0 26 I/O
25 I/O SEL2.5_3.3# controls the Vdd of CPU. If logic 0 at
power on, VddLCPU=3.3V. If logic 1, VddLCPU=2.5
24MHz or 48MHz selected by I2C for Super I/O.
Internal 250kΩ pull-up.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.
Publication Release Date: Nov. 1999
- 4 - Revision 0.65
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