Winbond Electronics W83194R-58A Datasheet

W83194R-58A

100MHZ AGP CLOCK FOR VIA CHIPSET

1.0 GENERAL DESCRIPTION

The W83194R-58A is a Clock Synthesizer for VIA chipset. W83194R-58A provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumII and also provides 16
different frequencies of CPU clocks by software setting. AGP and PCI clocks are externally
selectable with smooth transitions. The W83194R-58A provides AGP clocks especially for clone
chipset, and makes SDRAM in synchronous frequency with CPU or AGP clocks.

The W83194R-58A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.

The W83194R-58A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads when
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

• Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I2C.

• 4 CPU clocks

• 12 SDRAM clocks for 3 DIMs

• Two AGP clocks

• 6 PCI synchronous clocks.

• Optional single or mixed supply:

(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd = Vddq3 = Vddq2 = 3.3V, Vdq2b = 2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)

• SDRAM frequency synchronous to CPU or AGP clocks

• Smooth frequency switch with selections from 60 to 100 MHz CPU(-37) and 66 to 150MHz(-58)

• I2C 2-Wire serial interface and I2C read back

• 0~0.5% down type and 0.25%, 0.5% center type spread spectrum to reduce EMI

• Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• MODE pin for power Management

• 48 MHz for USB

• 24 MHz for super I/O

• 48-pin SSOP package

Publication Release Date: Nov. 1999

- 1 - Revision 0.30

~

3.0 BLOCK DIAGRAM

W83194R-58A

PRELIMINARY

X1
X2

3

*MODE

*SDATA

*SCLK

*FS(0:2)

CPU3.3#_2.5

*SD_SEL#

CPU_STOP#

PCI_STOP#

4.0 PIN CONFIGURATION

PLL2

~

XTAL
OSC

PLL1

Spread
Spectrum

LATCH

POR

Control

Logic

Config.

Reg.

5

¡Ò

2

CPU_STOP#

PCI
clock
Divder

PCI_STOP#

STOP

STOP

STOP

48MHz
24MHz

REF(0:1

2

AGP(0:1)

2

CPUCLK(0:3)

4

SDRAM(0:11)

12

PCICLK(0:4)

5

PCICLK_F

Publication Release Date: Nov. 1999

- 2 - Revision 0.30

W83194R-58A

PRELIMINARY

* REF0/CPU3.3#_2.5

Vddq3

PCICLK_F/*FS1

PCICLK0/*FS2

PCICLK1
PCICLK2
PCICLK3
PCICLK4

Vddq3

CPU_STOP#/SDRAM11

PCI_STOP#/SDRAM10

Vddq3
SDRAM 9
SDRAM 8

SDATA
SDCLK

5.0 PIN DESCRIPTION

IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low

Vdd

Vss

Xin

Xout

Vss

AGP0

Vss

Vss

16

1
2
3
4

5
6
7
8
9
10
11
12
13
14
15

17
18
19
20
21
22
23
24

48
47
46
45

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

26
25

Vddq2

AGP1

REF1/*SD_SEL#

Vss

CPUCLK0

CPUCLK1

Vddq2b
CPUCLK2
CPUCLK3

Vss
SDRAM 0

SDRAM 1

Vddq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vss
48MHz/*FS0

24MHz/*MODE

* - Internal 250kΩ pull-up

5.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 4 IN Crystal input with internal loading capacitors and

feedback resistors.

Xout 5 OUT Crystal output at 14.318MHz nominally.

5.2 CPU, SDRAM, PCI Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK [ 0:3 ] 40,41,43,44 OUT Low skew (< 250ps) clock outputs for host

frequencies such as CPU, Chipset and Cache.
Vddq2b is the supply voltage for these outputs.

Publication Release Date: Nov. 1999

- 3 - Revision 0.30

W83194R-58A

If MODE =1 (default), then this pin is a SDRAM clock
buffered output of the crystal. If MODE = 0 , then this

PRELIMINARY

AGP[ 0:1] 15,47 OUT Accelerate Graphic Port clock outputs
SDRAM11/
CPU_STOP#

SDRAM10/
PCI_STOP#

SDRAM [ 0:9] 20,21,28,29,31

PCICLK_F/ *FS1 7 I/O Latched input for FS1 at initial power up for H/W

17 I/O

18 I/O If MODE = 1 (default), then this pin is a SDRAM

,32,34,

35,37,38

pin is CPU_STOP# input used in power
management mode for synchronously stopping the
all CPU clocks.

clock output. If MODE = 0 , then this pin is
PCI_STOP # and used in power management mode
for synchronously stopping the all PCI clocks.

O SDRAM clock outputs which have the same

frequency as CPU clocks.

selecting the output frequency of CPU, SDRAM and
PCI clocks.

Free running PCI clock during normal operation.

Publication Release Date: Nov. 1999

- 4 - Revision 0.30