Winbond Electronics W83194R-58, W83194R-37 Datasheet
Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
• Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I
• 4 CPU clocks
• 12 SDRAM clocks for 3 DIMs
• Two AGP clocks
• 6 PCI synchronous clocks.
• Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = VDDq2 = 3.3V, VDDq2b = 2.5V)
• Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
• SDRAM frequency synchronous to CPU or AGP clocks
• Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
2
• I
C 2-Wire serial interface and I2C read back
• ±0.5% or ±1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
• Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
• MODE pin for power Management
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
2
C.
Publication Release Date: April 1999
- 1 - Revision A1
3.0 PIN CONFIGURATION
~
Preliminary W83194R-37/-58
* REF0/CPU3.3#_2.5
PCICLK_F/*FS1
PCICLK0/*FS2
CPU_STOP#/SDRAM11
PCI_STOP#/SDRAM10
4.0 BLOCK DIAGRAM
VDD
Vss
Xin
Xout
VDDq3
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDq3
AGP0
Vss
VDDq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
16
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDq2
AGP1
REF1/*SD_SEL#
Vss
CPUCLK0
CPUCLK1
VDDq2
CPUCLK2
CPUCLK3
Vss
SDRAM 0
SDRAM 1
VDDq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
VDDq3
SDRAM 6
SDRAM 7
Vss
48MHz/*FS0
24MHz/*MODE
X1
X2
*FS(0:2)
*MODE
CPU3.3#_2.5
*SD_SEL#
CPU_STOP#
PCI_STOP#
*SDATA
*SCLK
PLL2
~
¡Ò
2
XTAL
OSC
STOP
PLL1
Spread
Spectrum
3
LATCH
CPU_STOP#
5
POR
PCI
clock
Divder
STOP
STOP
48MHz
24MHz
REF(0:1
2
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
PCICLK(0:4)
5
PCICLK_F
Control
Logic
PCI_STOP#
Config.
Reg.
- 2 -
Preliminary W83194R-37/-58
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN Crystal input with internal loading capacitors and feedback
resistors.
Xout 5 OUT Crystal output at 14.318 MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL PIN I/O FUNCTION
CPUCLK [ 0:3 ] 40, 41, 43,44OUT Low skew (< 250 pS) clock outputs for host frequencies
such as CPU, Chipset and Cache. VDDq2b is the supply
voltage for these outputs.
AGP[ 0:1] 15, 47 OUT Accelerate Graphic Port clock outputs
SDRAM11/
CPU_STOP#
SDRAM10/
PCI_STOP#
SDRAM [ 0:9] 20, 21, 28,
PCICLK_F/ *FS1 7 I/O Latched input for FS1 at initial power up for H/W selecting
PCICLK 0/ *FS2 8 I/O Latched input for FS2 at initial power up for H/W selecting
17 I/O If MODE = 1 (default), then this pin is a SDRAM clock
buffered output of the crystal. If MODE = 0, then this pin is
CPU_STOP# input used in power management mode for
synchronously stopping the all CPU clocks.
18 I/O If MODE = 1 (default), then this pin is a SDRAM clock
output. If MODE = 0, then this pin is PCI_STOP # and
used in power management mode for synchronously
stopping the all PCI clocks.
O SDRAM clock outputs which have the same frequency as
29, 31, 32,
34, 35, 37,
38
CPU clocks.
the output frequency of CPU, SDRAM and PCI clocks.
Free running PCI clock during normal operation.
the output frequency of CPU, SDRAM and PCI clocks.
PCI clock during normal operation.
PCICLK [ 1:4 ] 10, 11, 12,13OUT Low skew (< 250 pS) PCI clock outputs.
Publication Release Date: April 1999
- 3 - Revision A1
Preliminary W83194R-37/-58
5.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
SDATA 23 I/O Serial data of I2C 2-wire control interface
SDCLK 24 IN Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
REF0/ CPU3.3#_2.5 2 I/O
REF1/*SD_SEL# 46 I/O
24MHz/ *MODE 25 I/O
48MHz/ *FS0 26 I/O
Internal 250 KΩ pull-up.
Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.
Latched high - VDDq2b = 2.5V
Latched low - VDDq2b = 3.3V
Internal 250 KΩ pull-up.
Latched input at Power On selects either CPU(SDSEL = 1)
or AGP(SD_SEL = 0) frequencies for SDRAM clock
outputs.
Internal 250 KΩ pull-up.
Latched input for MODE at initial power up. 24 MHz output
for super I/O during normal operation.
Internal 250 KΩ pull-up.
Latched input for FS0 at initial power up for H/W selecting
the output frequency of CPU, SDRAM and PCI clocks. 48
MHz output for USB during normal operation.
5.5 Power Pins
SYMBOL PIN FUNCTION
VDD 1 Power supply for Ref [0:1] crystal and core logic.
VDDq2 42 Power supply for AGP1 and REF1 output, either 2.5V or
3.3V.
VDDq2b 48 Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
VDDq3 6, 14, 19, 30, 36 Power supply for SDRAM, PCICLK and 48/24 MHz outputs.
Vss 3, 9, 16, 22, 27,
33, 39, 45
Circuit Ground.
- 4 -
Preliminary W83194R-37/-58
6.0 FREQUENCY SELECTION BY HARDWARE
6.1 W83194R-37 Frequency Selection Table
FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL = 1 SD_SEL = 0
0 0 0 60 60 60 30 60 14.318
0 0 1 66.8 66.8 66.8 33.4 66.8 14.318
0 1 0 68.5 68.5 68.5 34.25 68.5 14.318
0 1 1 75 75 75 37.5 75 14.318
1 0 0 75 75 60 30 60 14.318
1 0 1 83.3 83.3 66.6 33.3 66.6 14.318
1 1 0 95 95 63.4 31.7 63.4 14.318
1 1 1 100 100 66.6 33.3 66.6 14.318
6.2 W83194R-58 Frequency Selection Table
FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL = 1 SD_SEL = 0
0 0 0 112 112 74.7 37.3 74.7 14.318
0 0 1 66.8 66.8 66.8 33.4 66.8 14.318
0 1 0 124 124 82.5 41.3 82.5 14.318
0 1 1 75 75 75 37.5 75 14.318
1 0 0 133.3 133.3 88.7 44.3 88.7 14.318
1 0 1 83.3 83.3 66.6 33.3 66.6 14.318
1 1 0 95.25 95.25 63.5 31.75 63.5 14.318
1 1 1 100.2 100.2 66.8 33.4 66.8 14.318
7.0 CPU 3.3#_2.5 BUFFER SELECTION
CPU 3.3#_2.5 (Pin 2) Input Level CPU Operate at
1 VDD = 2.5V
0 VDD = 3.3V
Publication Release Date: April 1999
- 5 - Revision A1
Preliminary W83194R-37/-58
8.0 FUNCTION DESCRIPTION
8.1 Power Management Functions
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 mS for the VCO to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE = 0, pins 18 and 17 are inputs (PCI_STOP#), (CPU_STOP#),
when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2wire serial control interface and one of these pins indicate that it should be enabled.
The W83194R-37/-58 may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP# PCI_STOP# CPU & AGP PCI OTHER CLKs XTAL & VCOs
0 0 Low Low Running Running
0 1 Low Running Running Running
1 0 Running Low Running Running
1 1 Running Running Running Running
8.2 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-37/-58 initializes with default register settings, and then it optional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code
checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W
Ack
Set R/W to 1 when read back the data sequence is as follows:
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Clock Address
A(6:0) & R/W
Ack
Byte 0 Ack
- 6 -
Byte 1
Ack
Byte2, 3, 4...
until Stop
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