Winbond Electronics W83194BR-KT Datasheet
W83194BR-KT
STEP-LESS 3-DIMM K7 CLOCK
1.0 GENERAL DESCRIPTION
The W83194BR-KT is a Clock Synthesizer which provides all clocks required for AMD K7.
W83194BR-KT provides 64 CPU/PCI frequencies which are selectable with smooth transitions by
hardware or software. W83194BR-KT also provides 13 SDRAM clocks controlled by the none-delay
buffer_in pin.
The W83194BR-KT provides step-less frequency programming by controlling the VCO freq. and the
programmable PCI clock output divisor ratio. A watchdog timer is quipped and when time out, the
RESET# pin will output 4ms pulse signal.
The W83194BR-KT accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at
±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency
selection through I2C interface. The device meets the Pentium power-up stabilization, which requires
CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots (ISA,
PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
• Supports AMD CPU with I2C.
• 3 CPU clocks (one free-running chipset clock controlled by I2C)
• 13 SDRAM clocks for 3 DIMMs
• 6 PCI synchronous clocks
• Optional single or mixed supply:
(Vddq2 =2.5V, Vddq3 =3.3V)
• < 250ps skew among CPU and SDRAM clocks
• < 250ps skew among PCI clocks
• < 5ns propagation delay SDRAM from buffer input
• Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
• Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio
• I2C 2-Wire serial interface and I2C read back
• ±0.25% or ±0.5% spread spectrum function to reduce EMI
• Programmable spread spectrum in the M/N step-less mode
• Programmable registers to enable/stop each output and select modes
• MODE pin for power Management and RESET# out when Watch Dog Timer time out
• One 48 MHz for USB & one 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: June 2000
- 1 - Revision 0.43
3.0 PIN CONFIGURATION
W83194BR-KT
PRELIMINARY
Vddq3
^ REF0/FS4*
Vss
Xin
Xout
Vddq3
PCICLK_F^/MODE1*
PCICLK1^ /FS3*
Vss
PCICLK2^/SEL24_48*
PCICLK3^
PCICLK4^
PCICLK5
Vddq3
BUFFER IN
Vss
SDRAM11
SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
SDATA*
SDCLK*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
Vss
CPUT_CS
Vss
CPU_C0$
CPU_T0$
Vddq2
RESET$/^PD#
SDRAM12
Vss
SDRAM 0
SDRAM 1
Vddq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vddq3
48MHz/FS0*
24_48MHz/FS1*
* : Internal pull-up
^ : 1.5X~2X driving strength
& : Internal pull-low
$ : Open Drain
# : Active Low
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
& - Internal 120kΩ pull-down
Publication Release Date: June 2000
- 2 - Revision 0.43
* - Internal 120kΩ pull-up
CPUT_CS is the output pin for the chipset. It has the
drain. (4ms low active pulse when Watch Dog time
4.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN Crystal input with internal loading capacitors and
Xout 5 OUT Crystal output at 14.318MHz nominally.
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL PIN I/O FUNCTION
CPU_C0$
CPU_T0$
CPUT_CS
SDRAM [ 0 :12] 17,18,20,21,28,
PCICLK_F^/
*MODE1
PCICLK1^/*FS1 8 I/O Low skew (< 250ps) PCI clock outputs.
PCICLK2^/SEL24_48*
PCICLK ^[ 3 : 4 ]
PCICLK 5
BUFFER IN 15 IN Inputs to fanout for SDRAM outputs.
RESET$/*PD# 41 I/O The all clocks will be stopped when this pin set to
43
44
46 OUT
29,31,32,34,
35,37,38,40
7 I/O Free running PCI clock during normal operation.
10 I/O Low skew (< 250ps) PCI clock outputs.
11,12,13 OUT Low skew (< 250ps) PCI clock outputs.
W83194BR-KT
PRELIMINARY
feedback resistors.
OD CPU_C0 and CPU_T0 are the differential open drain
CPU clocks for AMD AthloneTM CPU. CPUT_CS is
the open drain pin for the chipset. It has the same
phase relationship as CPU_T0.
same phase relationship as CPU_T0.
OUT SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset) They are
disabled when PD# is set LOW.
Latched Input. Mode1=1(default), Pin 41 is RESET#
open drain. (4ms low active pulse when Watch Dog
time out), *Mode1=0, PD# input
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Latched input for at initial power up for H/W
selecting the output frequency of 24_48MHz.
SEL24_48*=1(default), pin25 is 24MHz,
SEL24_48=0, pin25 is 48MHz.
PCICLK_F and PCICLK [1:4] are double strength
pins
PCICLK 5 is not..
LOW. Mode1=1(default), Pin41 is RESET$ open
Publication Release Date: June 2000
- 3 - Revision 0.43
W83194BR-KT
wire control interface with internal
PRELIMINARY
out); *Mode1=0, PD# input
4.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
*SDATA 23 I/O Serial data of I2C 2-
*SDCLK 24 IN Serial clock of I2C 2-wire control interface with
4.4 Fixed Frequency Outputs
pull-up resistor.
internal pull-up resistor.
SYMBOL PIN I/O FUNCTION
^REF0/ *FS4 2 I/O 14.318MHz reference clock.
Latched input for FS4 at initial power up for H/W
selecting the output frequency of CPU and PCI
clocks
REF1/FS2* 48 I/O 14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU and PCI
clocks.
24_48MHz / *FS1 25 I/O 24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU and PCI
clocks.
48MHz / *FS0 26 I/O 48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU and PCI
clocks.
4.5 Power Pins
SYMBOL PIN FUNCTION
Vddq2 42 Power supply for CPU clocks, 2.5V or 3.3V.
Vddq3 1,6,14,19,27,30,36 Power supply for PCI, 24_48MHz, SDRAM [0:12], and
CPU PLL core, nominal 3.3V.
Publication Release Date: June 2000
- 4 - Revision 0.43
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