Winbond Electronics W83194BR-C Datasheet
W83194BR-C
200MHZ CLOCK FOR CAMINO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-C is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-C provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable
with smooth transitions.
The W83194BR-C provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI.
The W83194BR-C accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%
duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns
slew rate.
2.0 PRODUCT FEATURES
• 2 CPU clock outputs
• One CPU/2 output as reference input to DRCG
• 3 3V66 clock outputs
• 3 IOAPIC clock outputs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V)
• CPU to 3V66 offset .0 to 1.5 ns
• 3V66 to PCI offset 1.5 to 4.0 ns
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• I2C 2-Wire serial interface and I2C read back
• 0.5% and 0.75% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz pins for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Dec. 1999
- 1 - Revision 0.40
3.0 PIN CONFIGURATION
W83194BR-C
PRELIMINARY
IOAPIC
REF2X
VDDQ3
Xin
Xout
VSS
PCICLK0/ *FS2
PCICLK1/ *FS1
VDDQ3
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VSS
PCICLK6
PCICLK7/FS3#
VDDQ3
PCICLK8
PCICLK9
VSS
3V66-0
3V66-1
3V66-2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VddQ2
IOAPIC0
IOAPIC
VSS
VDDQ2
CPU/2
VSS
VDDQ2
CPUCLK2
VSS
VDDQ2
CPUCLK1
CPUCLK0
*SDATA
VDDQ3
VSS
PD#
*SDCLK
VDDQ3
*24_48MHz /SIO
48MHz/ *FS0
VSS
SEL133/100#
Publication Release Date: Dec. 1999
- 2 - Revision 0.40
W83194BR-C
PCICLK1/ *FS1
PCICLK7/ *FS3
PRELIMINARY
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
4.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN Crystal input with internal loading capacitors and
feedback resistors.
Xout 5 OUT Crystal output at 14.318MHz nominally.
4.2 CPU, 3V66, PCI, IOAPIC Clock Outputs
CPUCLK [0:2] 45,44 OUT Low skew (< 250ps) clock outputs for host
CPU/2 42 O As a reference signal for DRCG. The voltage is
PD# 31 IN Power Down mode when driven low.
SEL133/100# 25 IN Frequency selection input pin.
PCICLK0/ *FS2 7 I/O 3.3V PCI clock during normal operation.
PCICLK[2,8:9] 10,11,12,13,15
3V66 [0:2] 21, 22, 23 OUT 3.3V output clocks for the chipset.
IOAPIC[0:2] 46, 45, 1 O Synchronous with CPU clocks, 2.5V.
SYMBOL PIN I/O FUNCTION
frequencies such as CPU and Chipset.
determined by VDDQ2.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
8 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O Low skew (< 250ps) PCI clock outputs.
,18,19
16 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Publication Release Date: Dec. 1999
- 3 - Revision 0.40
wire control interface with internal
t frequency of 24MHz(HIGH) and 48MHz(LOW)
4.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
*SDATA 34 I/O Serial data of I2C 2-
*SDCLK 30 IN Serial clock of I2C 2-wire control interface with
4.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
IOAPIC[0:2] 46, 45, 1 O Synchronous with CPU clocks, 2.5V.
REFX2 2 I/O 14.318MHz reference clock.
24_48MHz/ *SIO 28 I/O 24MHz or 48MHz output clock.
48MHz/ FS0* 27 I/O 48MHz / Latched input for FS0 at initial power up
W83194BR-C
PRELIMINARY
pull-up resistor.
internal pull-up resistor.
Latched input for SIO at initial power up for the
outpu
clocks.
for H/W selecting the output frequency.
4.5 Power Pins
SYMBOL PIN FUNCTION
VddQ2 37,40,43,47 Power supply for CPU & IOAPIC, 2.5V
VddQ3 3,9,17,24,29,33 Power supply for PCI,3V66,REF2X,48MHz output,3.3V.
Vss 6,14,20,26,32,38,41,
44,48
Circuit Ground.
Publication Release Date: Dec. 1999
- 4 - Revision 0.40
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