Winbond Electronics W83194BR-97 Datasheet
W83194BR-97
200MHZ CLOCK FOR CAMINO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-97 is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-97 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 sets of different
frequencies of CPU, PCI, 3V66, IOAPIC clocks or stepless frequecies programming by M/N value via
I2C registers. All clocks are externally selectable with smooth transitions.
The W83194BR-97 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.5% and 0.25% center type spread spectrum to reduce EMI.
The W83194BR-97 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%
duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns
slew rate.
2.0 PRODUCT FEATURES
•
2 CPU clock outputs
•
One CPU/2 output as reference input to DRCG
•
3 3V66 clock outputs
•
3 IOAPIC clock outputs
• 8 PCI synchronous clocks.
•
Optional single or mixed supply:
(VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V)
•
CPU to 3V66 offset 0 to 1.5 ns
•
3V66 to PCI offset 1.5 to 4.0 ns
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
•
Smooth frequency switch with selections from 66.8 to 200MHz
•
Stepless programmable frequencies by I2C register9 ~ register12
•
I2C 2-Wire serial interface and I2C read back
•
0.5% and 0.75% center type spread spectrum
•
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
•
48 MHz pins for USB
• 24 MHz for super I/O
•
48-pin SSOP package
Publication Release Date: Dec. 1999
- 1 - Revision 0.35
W83194BR-97
PRELIMINARY
3.0 PIN CONFIGURATION
VSSR
REF0
REF1/*SEL24_48#
VDDR
Xin
Xout
VSSP
PCICLK_F/ *FS0
PCICLK1/ *FS1
VDDP
PCICLK2/ *FS2
PCICLK3/ *FS3
VSSPCI
PCICLK4
PCICLK5
VDDP
PCICLK6
PCICLK7
VSSPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VddA
IOAPIC0
IOAPIC1
VSSA
IOAPIC2
VDDC/2
CPU/2
VSSC/2
CPUCLK0
VDDCPU
CPUCLK1
CPUCLK2
VSSCPU
VDD66
3V66-0
3V66-1
3V66-2
VSS66
*SDATA
*SDCLK
VDD48
48MHz/ *FS4
24_48MHz/FREQ_APIC*
VSS48
Publication Release Date: Dec. 1999
- 2 - Revision 0.35
4.0 FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0
CPU
(MHz)
CPU/2 3V66/
CPU
3V66
(MHz)
W83194BR-97
PRELIMINARY
PCI
(MHz)
IOAPIC (MHz)
FREQ_APIC=1
IOAPIC (MHz)
FREQ_APIC=0
0 0 0 0 0 103.00 51.50 0.67 68.67 34.33
0 0 0 0 1 105.00 52.50 0.67 70.00 35.00
0 0 0 1 0 100.30 50.15 0.67 66.87 33.43
0 0 0 1 1 100.90 50.45 0.67 67.27 33.63
0 0 1 0 0 107.00 53.50 0.67 71.33 35.67
0 0 1 0 1 109.00 54.50 0.67 72.67 36.33
0 0 1 1 0 112.00 56.00 0.67 74.67 37.33
0 0 1 1 1 114.00 57.00 0.67 76.00 38.00
0 1 0 0 0 116.10 58.05 0.67 77.40 38.70
0 1 0 0 1 118.00 59.00 0.67 78.67 39.33
0 1 0 1 0 133.30 66.65 0.50 66.65 33.33
0 1 0 1 1 120.00 60.00 0.67 80.00 40.00
0 1 1 0 0 122.00 61.00 0.67 81.33 40.67
0 1 1 0 1 125.10 62.55 0.67 83.40 41.70
0 1 1 1 0 128.20 64.10 0.67 85.47 42.73
0 1 1 1 1 130.00 65.00 0.67 86.67 43.33
1 0 0 0 0 133.00 66.50 0.67 88.67 44.33
1 0 0 0 1 133.90 66.95 0.50 66.95 33.48
1 0 0 1 0 138.00 69.00 0.50 69.00 34.50
1 0 0 1 1 142.00 71.00 0.50 71.00 35.50
1 0 1 0 0 146.00 73.00 0.50 73.00 36.50
1 0 1 0 1 150.00 75.00 0.50 75.00 37.50
1 0 1 1 0 153.00 76.50 0.50 76.50 38.25
1 0 1 1 1 156.00 78.00 0.50 78.00 39.00
1 1 0 0 0 159.10 79.55 0.50 79.55 39.78
1 1 0 0 1 162.00 81.00 0.50 81.00 40.50
1 1 0 1 0 165.00 82.50 0.50 82.50 41.25
1 1 0 1 1 168.00 84.00 0.50 84.00 42.00
1 1 1 0 0 171.00 85.50 0.50 85.50 42.75
1 1 1 0 1 174.00 87.00 0.50 87.00 43.50
1 1 1 1 0 177.00 88.50 0.50 88.50 44.25
1 1 1 1 1 180.00 90.00 0.50 90.00 45.00
5.0
SERIAL CONTROL REGISTERS
17.17 34.33
17.50 35.00
16.72 33.43
16.82 33.63
17.83 35.67
18.17 36.33
18.67 37.33
19.00 38.00
19.35 38.70
19.67 39.33
16.66 33.33
20.00 40.00
20.33 40.67
20.85 41.70
21.37 42.73
21.67 43.33
22.17 44.33
16.74 33.48
17.25 34.50
17.75 35.50
18.25 36.50
18.75 37.50
19.13 38.25
19.50 39.00
19.89 39.78
20.25 40.50
20.63 41.25
21.00 42.00
21.38 42.75
21.75 43.50
22.13 44.25
22.50 45.00
Publication Release Date: Dec. 1999
- 3 - Revision 0.35
3V66/
3V66/
W83194BR-97
PRELIMINARY
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Frequency Selection BY I2C
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
0 0 0 0 0 0 103.00 51.50 0.67 68.67 34.33
0 0 0 0 0 1 105.00 52.50 0.67 70.00 35.00
0 0 0 0 1 0 100.30 50.15 0.67 66.87 33.43
0 0 0 0 1 1 100.90 50.45 0.67 67.27 33.63
0 0 0 1 0 0 107.00 53.50 0.67 71.33 35.67
0 0 0 1 0 1 109.00 54.50 0.67 72.67 36.33
0 0 0 1 1 0 112.00 56.00 0.67 74.67 37.33
0 0 0 1 1 1 114.00 57.00 0.67 76.00 38.00
0 0 1 0 0 0 116.10 58.05 0.67 77.40 38.70
0 0 1 0 0 1 118.00 59.00 0.67 78.67 39.33
0 0 1 0 1 0 133.30 66.65 0.50 66.65 33.33
0 0 1 0 1 1 120.00 60.00 0.67 80.00 40.00
0 0 1 1 0 0 122.00 61.00 0.67 81.33 40.67
0 0 1 1 0 1 125.10 62.55 0.67 83.40 41.70
0 0 1 1 1 0 128.20 64.10 0.67 85.47 42.73
0 0 1 1 1 1 130.00 65.00 0.67 86.67 43.33
0 1 0 0 0 0 133.00 66.50 0.67 88.67 44.33
0 1 0 0 0 1 133.90 66.95 0.50 66.95 33.48
0 1 0 0 1 0 138.00 69.00 0.50 69.00 34.50
0 1 0 0 1 1 142.00 71.00 0.50 71.00 35.50
0 1 0 1 0 0 146.00 73.00 0.50 73.00 36.50
0 1 0 1 0 1 150.00 75.00 0.50 75.00 37.50
0 1 0 1 1 0 153.00 76.50 0.50 76.50 38.25
0 1 0 1 1 1 156.00 78.00 0.50 78.00 39.00
0 1 1 0 0 0 159.10 79.55 0.50 79.55 39.78
0 1 1 0 0 1 162.00 81.00 0.50 81.00 40.50
0 1 1 0 1 0 165.00 82.50 0.50 82.50 41.25
0 1 1 0 1 1 168.00 84.00 0.50 84.00 42.00
0 1 1 1 0 0 171.00 85.50 0.50 85.50 42.75
0 1 1 1 0 1 174.00 87.00 0.50 87.00 43.50
0 1 1 1 1 0 177.00 88.50 0.50 88.50 44.25
0 1 1 1 1 1 180.00 90.00 0.50 90.00 45.00
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
CPU
(MHz)
CPU
(MHz)
CPU/2
CPU/2
CPU
CPU
3V66
(MHz)
3V66
(MHz)
PCI
(MHz)
PCI
(MHz)
IOAPIC (MHz)
FREQ_APIC=1
IOAPIC (MHz)
FREQ_APIC=0
17.17 34.33
17.50 35.00
16.72 33.43
16.82 33.63
17.83 35.67
18.17 36.33
18.67 37.33
19.00 38.00
19.35 38.70
19.67 39.33
16.66 33.33
20.00 40.00
20.33 40.67
20.85 41.70
21.37 42.73
21.67 43.33
22.17 44.33
16.74 33.48
17.25 34.50
17.75 35.50
18.25 36.50
18.75 37.50
19.13 38.25
19.50 39.00
19.89 39.78
20.25 40.50
20.63 41.25
21.00 42.00
21.38 42.75
21.75 43.50
22.13 44.25
22.50 45.00
IOAPIC (MHz)
FREQ_APIC=1
IOAPIC (MHz)
FREQ_APIC=0
Publication Release Date: Dec. 1999
- 4 - Revision 0.35
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