Winbond Electronics W83194AR-W Datasheet
W83194AR-W
150MHZ CLOCK FOR WHITNEY CHIPSET
1.0 GENERAL DESCRIPTION
The W83194AR-W is a Clock Synthesizer for Intel Whitney chipset. W83194AR-W provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83194AR-W provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI.
The W83194AR-W accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• 2 CPU clocks
• 9 SDRAM clocks for 2 DIMMs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddA=VddC=2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 150MHz
• I2C 2-Wire serial interface and I2C read back
• 0.5% and 0.75% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• Two 48 MHz pins for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: May. 1999
- 1 - Revision 0.50
3.0 PIN CONFIGURATION
W83194AR-W
PRELIMINARY
REFX2/*FS3
VddR
Xin
Xout
Vss
Vdd3
3V66-0
3V66-1
Vss3
PCICLK0/ *FS0
PCICLK1/ FS1#
PCICLK2/*FS2
VssP
PCICLK3/FS4#
PCICLK4
VddP
PCICLK5
PCICLK6
PCICLK7
Vss48
48MHz_0
48MHz_1
*SIO_SEL/24_48MHz
Vdd48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VddLAPIC
IOAPIC
VddLCPU
CPUCLK0
CPUCLK1
VssC
VddS
SDRAM 0
SDRAM 1
SDRAM 2
VssS
SDRAM 3
SDRAM 4
SDRAM 5
VddS
SDRAM 6
SDRAM 7
SDRAM 8
VssS
PD#
*SDCLK
VddA
VssA
*SDATA
Publication Release Date: May. 1999
- 2 - Revision 0.50
W83194AR-W
PRELIMINARY
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
4.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 3 IN Crystal input with internal loading capacitors and
feedback resistors.
Xout 4 OUT Crystal output at 14.318MHz nominally.
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL PIN I/O FUNCTION
CPUCLK [0:1] 45,44 OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
PD# 29 IN Power Down mode when driven low.
IOAPIC 47 OUT Clock outputs synchronous with PCI clock and
powered by VddA.
SDRAM [ 0:8] 41,40,
39,37,36,35,33
,32,31
PCICLK0/ *FS0 10 I/O 3.3V 33MHz PCI clock during normal operation.
PCICLK1/ FS1# 11 I/O Low skew (< 250ps) PCI clock outputs.
PCICLK2/ *FS2 12 I/O Low skew (< 250ps) PCI clock outputs.
PCICLK3/ FS4# 14 I/O Low skew (< 250ps) PCI clock outputs.
PCICLK [ 4:7 ] 15,17,18,19 OUT Low skew (< 250ps) PCI clock outputs.
3V66 [0:1] 7,8 OUT 3.3V output clocks for the chipset.
OUT SDRAM clock outputs.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Latched input for FS4 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Publication Release Date: May. 1999
- 3 - Revision 0.50
W83194AR-W
PRELIMINARY
4.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
*SDATA 25 I/O Serial data of I2C 2-wire control interface with internal
pull-up resistor.
*SDCLK 28 IN Serial clock of I2C 2-wire control interface with
internal pull-up resistor.
4.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
REFX2 / *FS3 3 I/O 14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
*SIO_SEL/24_48MHz 23 I/O 24MHz or 48MHz output clock.
Latched input for SIO_SEL at initial power up for the
output frequency of 24MHz(HIGH) and 48MHz(LOW)
clocks.
48MHz [0:1] 21,22 I/O 48MHz output for USB during normal operation.
4.5 Power Pins
SYMBOL PIN FUNCTION
VddL 48 Power supply for CPU & IOAPIC, 2.5V or 3.3V.
Vdd48 24 Power supply for 48MHz output,3.3V.
Vdd3 6 Power supply for 3V_66 output, 3.3V.
VddP 16 Power supply for PCICLK, 3.3V.
VddR 2 Power supply for REFX2, 3.3V.
VddS 42,34 Power supply for SDRAM[0:8], nominal 3.3V.
VddA 27 Power for I2C CLK and DATA.
Vss 5,9,13,20,26,30,38,43Circuit Ground.
Publication Release Date: May. 1999
- 4 - Revision 0.50
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