Winbond Electronics W83194AR-73 Datasheet

W83194AR-73

150MHZ CLOCK FOR WHITNEY CHIPSET

1.0 GENERAL DESCRIPTION

The W83194AR-73 is a Clock Synthesizer for Intel Whitney chipset. W83194AR-73 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 32 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.

The W83194AR-73 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% center and 0-0.5% down type spread spectrum to reduce EMI.

The W83194AR-73 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.

1.0 PRODUCT FEATURES

• 2 CPU clocks

• 9 SDRAM clocks for 2 DIMMs

• 8 PCI synchronous clocks.

• Optional single or mixed supply:

(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns

• Smooth frequency switch with selections from 66.8 to 150MHz

• I2C 2-Wire serial interface and I2C read back

• 0.25% center and 0-0.5% down type spread spectrum

• Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• 48 MHz for USB

• 24 MHz for super I/O

• Packaged in 48-pin SSOP

Publication Release Date: May 1999

- 1 - Revision 0.40

3.0 PIN CONFIGURATION

W83194AR-73

PRELIMINARY

REF1/*SEL_3V66

VDDR

Xin

Xout
VSS
VSS

3V66-0
3V66-1

VDD3

VDDP
PCICLK0/ *FS0
PCICLK1/ *FS1

PCICLK2/*SEL24_48#

VSS
PCICLK3
PCICLK4

PCICLK5

VDDP
PCICLK6
PCICLK7

VSS

PD#

*SDCLK
*SDATA

1
2
3
4

5
6
7

8
9
10
11

12
13

14
15

16

17
18
19
20
21
22
23
24

48
47
46
45

44
43
42
41
40
39
38
37
36
35

34
33
32
31
30

29
28
27
26
25

VddA
IOAPIC
VDDC

CPUCLK0
CPUCLK1

VSS

VSS
SDRAM 0
SDRAM 1
SDRAM 2
VDDS
SDRAM 3

SDRAM 4

SDRAM 5

VSS

SDRAM 6
SDRAM 7

SDRAM_F

VDDS
VSS

24_48MHz/ *FS2
48MHz-0

48MHz-1/ *FS3
VDD48

Publication Release Date: May 1999

- 2 - Revision 0.30

4.0 FREQUENCY SELECTION BY HARDWARE

W83194AR-73

PRELIMINARY

FS3 FS2 FS1 FS0 CPU(MHz) SDRAM

(MHz)

0 0 0 0 100.23 100.23 66.82
0 0 0 1 100.9 100.9 67.26 67.26 33.63 16.815
0 0 1 0 105 105 70 70 35 17.5
0 0 1 1 66.89 100.33 66.89 66.89 33.44 16.72
0 1 0 0 120 120 64 80 40 20.00
0 1 0 1 124 124 64 82.66 41.33 20.67
0 1 1 0 133.3 133.3
0 1 1 1
1 0 0 0 140 140 70 70 35 17.5
1 0 0 1 150 150 64 75 37.50 18.75
1 0 1 0 114.99 114.99 64 76.66 38.33 19.17
1 0 1 1 70 105 70 70 35 17.5
1 1 0 0 75 112.5 64 75 37.5 18.75
1 1 0 1 83.31 124.96 64 83.31 41.65 20.825

133.6 100.2 66.65 66.65

3V66 (MHz) PCI(MHz) IOAPIC

SEL_3V66=0 SEL_3V66=1

33.41 16.71

33.32 16.66

66.65

66.82

88.86 44.43 22.22

(MHz)

1 1 1 0 90 90 60 60 30 15
1 1 1 1 95 95 63.33 63.33 31.67 15.84

5.0 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.

After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and

acknowledged.

Publication Release Date: May 1999

- 3 - Revision 0.30