Winbond Electronics W83193R-04A, W83193R-04, W83193R-02 Datasheet
Preliminary W83193R-02/-04/-04A
83.3 MHZ 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83193R-02/-04/-04A is a Main board Clock Synthesizer which provides all clocks required for
high-speed RISC or CISC microprocessor such as Intel PentiumPro, PentiumII, AMD or Cyrix. Eight
different frequency of CPU and PCI clocks are externally selectable with smooth transitions.
The W83193R-02/-04/-04A also provides I2C serial bus interface to program the registers to enable
or disable each clock outputs and choose the 0.5% or 1.5% center type spread spectrum.
The W83193R-02/-04/-04A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads
as maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
• Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I
• 4 CPU clocks
• 12 SDRAM clocks for 3 DIMs.
• 7 PCI synchronous clocks.
• One IOAPIC clock for multiprocessor support.
• Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = 3.3V, VDDq2 = VDD2b = 2.5V)
• < 250 pS skew among CPU and SDRAM clocks.
• < 250 pS skew among PCI clocks.
• Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU. (W83193R-04)
• Smooth frequency switch with selections from 50 MHz to 112 MHz CPU. (W83193R-04A)
2
• I
C 2-Wire serial interface and I2C read back.
• Spread spectrum function to reduce EMI.
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal)
• MODE pin for power Management
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
2
C.
Publication Release Date: April 1999
- 1 - Revision A1
4.0 PIN CONFIGURATION
SCLK
Preliminary W83193R-02/-04/-04A
REF0/CPU3.3#_2.5
PCICLK_F/*FS1
PCICLK0/*FS2
PCICLK5/PCI_STOP#
3.0 BLOCK DIAGRAM
VDD
Vss
Xin
Xout
VDDq3
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDq3
Vss
SDRAM11
SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDq2
IOAPIC
REF1/CPU_STOP#
Vss
CPUCLK0
CPUCLK1
VDDq2b
CPUCLK2
CPUCLK3
Vss
SDRAM 0
SDRAM 1
VDDq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
VDDq3
SDRAM 6
SDRAM 7
Vss
48MHz/*FS0
24MHz/*MODE
Xin
Xout
FS(0:2)*
MODE*
CPU3.3#_2.5*
CPU_STOP#
PCI_STOP#
SDATA
PLL2
~
XTAL
OSC
6
PLL1
Spread
Spectrum
3
LATCH
~
POR
Control
Logic
Config. Reg.
1/2
STOP
PCI
5
Clock
STOP
Divider
48 MHz
24 MHz
IOAPIC
REF(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
PCICLK(0:5)
6
PCICLK_F
- 2 -
Preliminary W83193R-02/-04/-04A
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL PIN I/O FUNCTION
Xin 4 IN Crystal input with internal loading capacitors and
feedback resistors.
Xout 5 OUT Crystal output at 14.318 MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL PIN I/O FUNCTION
CPUCLK [ 0:3 ] 40, 41, 43, 44 OUT Low skew (< 250 pS) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VDDq2 is the supply voltage for these outputs.
IOAPIC 47 OUT High drive buffered output of the crystal, and is
powered by VDDq2.
SDRAM [ 0:11] 17, 18, 20, 21,
28, 29, 31, 32,
34, 35, 37, 38
PCICLK_F/ *FS1 7 I/O Latched input for FS1 at initial power up for H/W
PCICLK 0 / *FS2 8 I/O Latched input for FS2 at initial power up for H/W
PCICLK [ 1:4 ] 10, 11, 12, 13 OUT Low skew (< 250 pS) PCI clock outputs.
PCICLK5/ PCI_STOP# 15 I/O
O SDRAM clock outputs which have the same
frequency as CPU clocks.
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Free running PCI clock during normal operation.
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
Internal 250 KΩ pull-up.
If MODE = 1 (default), then this pin is a PCI5 clock
output. If MODE = 0 , then this pin is PCI_STOP #
and used in power management mode for
synchronously stopping the all PCI clocks.
Publication Release Date: April 1999
- 3 - Revision A1
5.3 I2C Control Interface
SYMBOL PIN I/O FUNCTION
SDATA
SDCLK
23 I/O Serial data of I2C 2-wire control interface
24 IN Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL PIN I/O FUNCTION
Preliminary W83193R-02/-04/-04A
REF0/CPU3.3#_2.5 2 I/O
REF1/CPU_STOP# 46 I/O
24MHz / *MODE 25 I/O
48MHz / *FS0 26 I/O
5.5 Power Pins
Internal 250kΩ pull-up.
Latched input for CPU3.3#_2.5 at initial power up. Reference
clock during normal operation.
Latched high - VDDq2 = VDDq2b = 2.5V
Latched low - VDDq2 = VDDq2b = 3.3V
Internal 250 KΩ pull-up.
If MODE = 1 (default), then this pin is a REF1 buffered output
of the crystal. If MODE = 0 , then this pin is CPU_STOP#
input used in power management mode for synchronously
stopping the all CPU clocks.
Internal 250 KΩ pull-up.
Latched input for MODE at initial power up. 24 MHz output for
super I/O during normal operation.
Internal 250 KΩ pull-up.
Latched input for FS0 at initial power up for H/W selecting the
output frequency of CPU, SDRAM and PCI clocks. 48 MHz
output for USB during normal operation.
SYMBOL PIN FUNCTION
VDD 1 Power supply for Ref [0:1] crystal and core logic.
VDDq2 42 Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
VDDq2b 48 Power supply for IOAPIC output, either 2.5V or 3.3V.
VDDq3 6, 14, 19, 30, 36 Power supply for SDRAM, PCICLK and 48/24 MHz outputs.
VSS 3, 9, 16, 22, 27, 33,
39, 45
Circuit Ground.
- 4 -
Preliminary W83193R-02/-04/-04A
6.0 FREQUENCY SELECTION
W83193R-02/-04 Frequency Table
FS2 FS1 FS0 CPU, SDRAM (MHz) PCI (MHz) REF, IOAPIC (MHz)
0 0 0 50 25 14.318
0 0 1 75 32 14.318
0 1 0 83.3 41.65 14.318
0 1 1 68.5 34.25 14.318
1 0 0 83.3 33.3 14.318
1 0 1 75 37.5 14.318
1 1 0 60 30 14.318
1 1 1 66.8 33.4 14.318
W83193R-04A Frequency Table
FS2 FS1 FS0 CPU, SDRAM (MHz) PCI (MHz) REF, IOAPIC (MHz)
0 0 0 50 25 14.318
0 0 1 100 50 14.318
0 1 0 83.3 41.65 14.318
0 1 1 68.5 34.25 14.318
1 0 0 90 45 14.318
1 0 1 75 37.5 14.318
1 1 0 112 56 14.318
1 1 1 66.8 33.4 14.318
7.0 CPU 3.3#_2.5 BUFFER SELECTION
CPU 3.3#_2.5 (PIN 2) INPUT LEVEL CPU & IOAPIC OPERATE AT
1 VDD = 2.5V
0 VDD = 3.3V
8.0 FUNCTIONAL DESCRIPTION
8.1 Power Management Functions
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE = 0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#),
when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2wire serial control interface and one of these pins indicate that it should be enable.
Publication Release Date: April 1999
- 5 - Revision A1
Preliminary W83193R-02/-04/-04A
The W83193R-02/-04/-04A may be disabled in the low state according to the following table in order
to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP# PCI_STOP# CPU PCI OTHER CLKs XTAL & VCOs
0 0 Low Low Running Running
0 1 Low Running Running Running
1 0 Running Low Running Running
1 1 Running Running Running Running
8.2 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83193R-02/-04/-04A initializes with default register settings, and then it's optional to use the 2-wire
control interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I2C registers after the string of data. The sequence order is as
follows:
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back, the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0 Ack
Byte 1
Ack
Byte2, 3, 4...
until Stop
8.3 Serial Control Registers
The pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in
these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,
the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
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