Winbond Electronics W83193R-01 Datasheet

W83193R-01

83.MHZ 3-DIMM CLOCK

1.0 GENERAL DESCRIPTION

The W83193R-01 is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel PentiumPro , AMD or Cyrix. Eight different frequency of CPU and
PCI clocks are externally selectable with smooth transitions.

The W83193R-02/-04 also provides I2C serial bus interface to program the registers to enable or
disable each clock outputs and choose the 0.6% or 1.5% center type spread spectrum.

The W83193R-01 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

• Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I2C.

• 4 CPU clocks.

• 12 SDRAM clocks for 3 DIMs.

• 7 PCI synchronous clocks.

• One IOAPIC clock for multiprocessor support.

• Optional single or mixed supply:

(Vdd = Vddq3 = Vddq2 = 3.3V) or (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)

• < 250ps skew among CPU and SDRAM clocks.

• < 250ps skew among PCI clocks.

• Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU.

• I2C 2-Wire serial interface.

• 0.6% or 1.5% center type spread spectrum function to reduce EMI.

• Programmable registers to enable/stop each output and select modes.

(mode as Tri-state, or Normal )

• MODE pin for power Management.

• 48 MHz for USB.

• 24 MHz for super I/O.

• 48-pin SSOP package.

Publication Release Date: May 1998

- 1 - Revision 0.20

3.0 BLOCK DIAGRAM

Vdd

Vddq2

Buffers

Buffers

Buffers

CPU_stop#

Vddq3

Vddq3

Vddq3

Vddq3

Vddq3

Xin

W83193R-01

PRELIMINARY

Xout

*SDATA
*SDCLK

*MODE

*CPU3.3#_2.5

*FS[0:2]

*CPU_STOP#

*PCI_STOP

4.0 PIN CONFIGURATION

Vdd

REF0

Vss

Xout

Vddq3

PCICLK_F/*FS1

PCICLK0/*FS2

PCICLK1/*FTS

PCICLK5/PCI_STOP#

Vss

PCICLK2
PCICLK3
PCICLK4

Vddq3

Vss
SDRAM11
SDRAM10

Vddq3

SDRAM 9
SDRAM 8

Vss

*SDATA
*SDCLK

Xin

REF
OSC

Register

PLL

LATC

Contr
ol

PLL2

1
2
3
4

5
6
7
8
9
10
11
12
13
14
15

16

17
18
19
20
21
22
23
24

Stop
clock

PCI_stop#

Stop

Dela

1/2

Vddq2

Buffers

Buffers

Buffers

Buffers

Buffers

48
47
46
45

44
43
42
41
40
39
38
37
36
35

34
33
32
31
30
29
28
27
26
25

REF[0:1]

IOAPIC

CPUCLK[0:3]

SDRAM[0:11]

PCICLK[0:5]

PCICLK_F

48MHz

24MHz

Vddq2

IOAPIC

REF1/CPU_STOP#

Vss

CPUCLK0

CPUCLK1

Vddq2
CPUCLK2
CPUCLK3

Vss
SDRAM 0

SDRAM 1

Vddq3
SDRAM 2
SDRAM 3
Vss
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vss

48MHz/*FS0
24MHz/*MODE

Publication Release Date: May 1998

- 2 - Revision 0.20

W83193R-01

PRELIMINARY

5.0 PIN DESCRIPTION

IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up

5.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 4 IN Crystal input with internal loading capacitors and

feedback resistors.

Xout 5 OUT Crystal output at 14.318MHz nominally.

5.2 CPU, SDRAM, PCI Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK [ 0:3 ] 40,41,43,44 OUT Low skew (< 250ps) clock outputs for host

frequencies such as CPU, Chipset and Cache.
Vddq2 is the supply voltage for these outputs.

IOAPIC 47 OUT High drive buffered output of the crystal, and is

powered by VDDq2.

SDRAM [ 0:11] 17,18,20,21,28

,29,31,32,34,

35,37,38

PCICLK_F/ *FS1 7 I/O Latched input for FS1 at initial power up for H/W

PCICLK 0 / *FS2 8 I/O Latched input for FS2 at initial power up for H/W

PCICLK 1/ *FTS 10 I/O Latched input for FTS at initial power up for H/W

O SDRAM clock outputs which have the same

frequency as CPU clocks.

selecting the output frequency of CPU, SDRAM and
PCI clocks.

Free running PCI clock during normal operation.

selecting the output frequency of CPU, SDRAM and
PCI clocks.

PCI clock during normal operation.

selecting the output frequency of CPU, SDRAM and
PCI clocks.

PCI clock during normal operation.

Publication Release Date: May 1998

- 3 - Revision 0.20

5.2 CPU, SDRAM, PCI Clock Outputs, continued

SYMBOL PIN I/O FUNCTION

W83193R-01

PRELIMINARY

SDRAM [ 0: 11 ] 17,18,20,21,

28,29,31,32,

34,35,37,38
PCICLK [ 2:4 ] 11,12,13 OUT Low skew (< 250ps) PCI clock outputs.
PCICLK5/ PCI_STOP# 15 I/O

O Synchronous DRAM DIMs clocks which have the

same frequency as CPU clocks

Internal 250kΩ pull-up.
If MODE = 1 (default), then this pin is a PCI5 clock

output. If MODE = 0 , then this pin is PCI_STOP #
and used in power management mode for
synchronously stopping the all PCI clocks.

5.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

*SDATA 23 I/O Serial data of I2C 2-wire control interface with internal

pull-up resistor.

*SDCLK 24 IN Serial clock of I2C 2-wire control interface with

internal pull-up resistor.

5.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

REF0 2 I/O
REF1 / CPU_STOP# 46 I/O

24MHz / *MODE 25 I/O

48MHz / *FS0 26 I/O

Internal 250kΩ pull-up buffered output of the crystal.
Internal 250kΩ pull-up.

If MODE =1 (default), then this pin is a REF1
buffered output of the crystal. If MODE = 0 , then this
pin is CPU_STOP# input used in power
management mode for synchronously stopping the
all CPU clocks.

Internal 250kΩ pull-up.
Latched input for MODE at initial power up. 24MHz

output for super I/O during normal operation.
Internal 250kΩ pull-up.

Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.

Publication Release Date: May 1998

- 4 - Revision 0.20

W83193R-01

PRELIMINARY

5.5 Power Pins

SYMBOL PIN FUNCTION

Vdd 1 Power supply for Ref [0:1] crystal and core logic.
Vddq2 42, 48 Power supply for IOAPIC output and CPUCLK[0:3],

either 2.5V or 3.3V.

Vddq3 6,14,19, 30, 36 Power supply for SDRAM, PCICLK and 48/24MHz

outputs.

Vss 3,9,16,22,27,

33,39,45

Circuit Ground.

6.0 FREQUENCY SELECTION

FTS = 1 (MHz) FTS = 0 (MHz) REF,IOAPIC (MHz)

FS2 FS1 FS0 CPU PCI CPU PCI

0 0 0 61.8 30.9 62.4 31.2 14.318
0 0 1 75 30 78 39 14.318
0 1 0 83.3 33.3 85.8 42.8 14.318
0 1 1 68.5 34.25 69.5 34.74 14.318
1 0 0 55 27.5 83.3 41.7 14.318
1 0 1 75 37.5 75 32 14.318
1 1 0 60 30 80 40 14.318
1 1 1 66.8 33.4 50 25 14.318

Publication Release Date: May 1998

- 5 - Revision 0.20

W83193R-01

PRELIMINARY

7.0 FUNTION DESCRIPTION

7.1 POWER MANAGEMENT FUNCTIONS

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO’s to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#),
(CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be
enabled as both the 2-wire serial control interface and one of these pins indicate that it should be
enable.

The W83193R-01 may be disabled in the low state according to the following table in order to reduce
power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.

CPU_STOP# PCI_STOP# CPU PCI OTHER CLKs XTAL & VCOs

0 0 LOW LOW RUNNING RUNNING
0 1 LOW RUNNING RUNNING RUNNING
1 0 RUNNING LOW RUNNING RUNNING
1 1 RUNNING RUNNING RUNNING RUNNING

7.2 2-WIRE I2C CONTROL INTERFACE

The 2-wire control interface implements a write only slave interface and cannot be read back. All
proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows
each clock output individually enabled or disabled. On power up, the W83193R-01 initializes with
default register settings, and then it’s optional to use the 2-wire control interface.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a “start” condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock
chip. Controller can start to write to internal I2C registers after the string of data. The sequence
order is as follows:

Publication Release Date: May 1998

- 6 - Revision 0.20