Winbond Electronics W78LE58P-24, W78LE58F-24, W78LE58-24 Datasheet

Preliminary W78LE58

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78LE58 is an 8-bit microcontroller which has an in-system programmable MTP-ROM for firmware updating. The instruction set of the W78LE58 is fully compatible with the standard 8052. The W78LE58 contains a 32K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which allows the contents of the 32KB main MTP-ROM to be updated by the loader program located at the 4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78LE58 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.

The W78LE58 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.

FEATURES

•

Fully static design 8-bit CMOS microcontroller

•

32K bytes of in-system programmable MTP-ROM for Application Program (APROM)

•

4K bytes of auxiliary MTP-ROM for Loader Program (LDROM)

•

512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)

•

64K bytes program memory address space and 64K bytes data memory address space

•

Four 8-bit bi-directional ports

•

One 4-bit multipurpose programmable port

•

Three 16-bit timer/counters

•

One full duplex serial port

•

Eight-sources, two-level interrupt capability

•

Built-in power management

•

Code protection

•

Packaged in

− DIP 40: W78LE58-24

− PLCC 44: W78LE58P-24

− QFP 44: W78LE58F-24

Publication Release Date: June 2000

- 1 - Revision A1

PIN CONFIGURATIONS

40-Pin DIP (W78LE58)

T2, P1.0

T2EX, P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST RXD, P3.0 TXD, P3.1

INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

WR, P3.6

RD, P3.7

XTAL2 XTAL1

VSS

Preliminary W78LE58

VDD1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39

P0.0, AD0

P0.1, AD1

38 37

P0.2, AD2

P0.3, AD3

36 35

P0.4, AD4

P0.5, AD5

34 33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

23

P2.2, A10

22

P2.1, A9

21

P2.0, A8

44-Pin PLCC (W78LE58P) 44-Pin QFP (W78LE58F)

/

T

P1.5 P1.6 P1.7

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

P

1

.

3

4

6 5 4 3

7 8 9 10 11 12 13 14 15 16

17

P

3

.

7

6

,

/

R

W

D

R

2 E X ,

P

P 1

1

.

. 2

1

X

T

A

L

1

2

I N

T

2

3

,

P

1

V

4

.

D

.

0

D

2

2 1 44 43 42

V

P

S

2

4

S

.

0

, A 8

A

D

3

2

1

0

,

P

0

.

3

2

1

0

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

2

.

4

3

2

1

,

A

1

9

2

1

0

P1.5 P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

/

T

I

2

N

T

E

T

2

X

3

,

P

1

.

3

4

43 42 41

44

1 2

3

4 5 6 7 8 9 10

11

P

3

.

7

6

,

/

R

W

D

R

1

.

0

2

1

40 39 38 37 36 35

X

V

X

T

S

T

A

S

A

L

1

2

P

V

4

D

.

D

2

P

2

4

.

0

, A 8

A

D

3

1

2

0

,

P

0

.

3

2

1

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

2221201918171615141312

P

2

.

4

3

2

1

,

A

1

9

2

1

0

- 2 -

PIN DESCRIPTION

EA

Preliminary W78LE58

SYMBOL TYPE

P0.0−P0.7 P1.0−P1.7 P2.0−P2.7

P3.0−P3.7 P4.0−P4.3

PSEN

ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

RST I L RESET: A high on this pin for two machine cycles while the oscillator is

XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an

XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

SS

V

DD

V

I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the

external ROM. The ROM address and data will not be presented on the bus if the EA pin is high.

O H

I/O D PORT 0: Function is the same as that of standard 8052. I/O H PORT 1: Function is the same as that of standard 8052. I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

I/O H PORT 3: Function is the same as that of the standard 8052. I/O H PORT 4: A bi-directional I/O. See details below.

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no

strobe signal outputs originate from this pin.

separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency.

running resets the device.

external clock.

I GROUND: ground potential. I POWER SUPPLY: Supply voltage for operation.

provides the upper address bits for accesses to external memory.

DESCRIPTIONS

PSEN

* Note:

I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

TYPE

Publication Release Date: June 2000

- 3 - Revision A1

BLOCK DIAGRAM

Preliminary W78LE58

P1.0

P1.7

P3.0

P3.7

P4.0 P4.3

Port

Interrupt

UART

Port 1 Latch

Timer

Port 3 Latch

Port 4 Latch

2

0

1

XTAL1

Oscillator

ACC

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALE

PSEN

ALU

SFR RAM

Address

512 bytes

RAM & SFR

Reset Block

B

T2T1

Stack

Pointer

Power control

VssVCCRSTXTAL2

Port 0

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

32KB

MTP-ROM

4KB

Port 2

Latch

Port 0

Port 2

P0.0

P0.7

P2.0

P2.7

1

Port

3

Port

4

FUNCTIONAL DESCRIPTION

The W78LE58 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.

RAM

The internal data RAM in the W78LE58 is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.

•

RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers

are R0 and R1 of the selected register bank.

•

RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank.

- 4 -

Preliminary W78LE58

•

AUX-RAM 0H−FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal

program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD. Example, CHPENR REG F6H

CHPCON REG BFH MOV CHPENR ,#87H MOV CHPENR,#59H ORL CHPCON,#00010000B ; enable AUX-RAM MOV CHPENR,#00H MOV R0,#12H MOV A,#34H MOVX @R0,A ; Write 34h data to 12h address.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78LE58 is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78LE58 relatively insensitive to duty cycle variations in the clock.

Crystal Oscillator

The W78LE58 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator.

Publication Release Date: June 2000

- 5 - Revision A1

Preliminary W78LE58

INT1

Power Management

Idle Mode

Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a

hardware reset or external interrupts INT0 to

Reduce EMI Emission

The W78LE58 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78LE58 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

when enabled and set to level triggered.

W78LE58 Special Function Registers (SFRs) and Reset Values

F8

F0 +B

E8

E0 +ACC

D8

D0 +PSW

C8 +T2CON

C0 XICON

B8 +IP

B0 +P3

00000000

+P4

xxxx1111

00000000

RCAP2L

00000000

P4CONA

00000000

RCAP2H

00000000

P4CONB

00000000

TL2

00000000

SFRAL

00000000

P43AL

00000000

SFRAH

00000000

P43AH

00000000

- 6 -

TH2

CHPENR

00000000

SFRFD

00000000

SFRCN 00000000 CHPCON 0xx00000

FF

F7

EF

E7

DF

D7

CF

C7

BF

B7

Preliminary W78LE58

INT3

INT2

CLR

Continued

A8 +IE

00000000

A0 +P2

11111111

98 +SCON

00000000

90 +P1

11111111

88 +TCON

00000000

80 +P0

11111111

Notes:

1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.

2. The text of SFR with bold type characters are extension function registers.

SBUF

xxxxxxxx

TMOD

00000000

SP

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

P42AL

00000000

P41AL

00000000

TH0

00000000

P40AL

00000000

P42AH

00000000

P41AH

00000000

TH1

00000000

P40AH

00000000

P2ECON

0000xx00

Port 4

Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes.

Mode 0: P4.0−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as

external interrupt

and

if enabled.

PCON

00110000

AF

A7

9F

97

8F

87

Mode 1: P4.0−P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals.

Mode 2: P4.0−P4.3 are write strobe signals that are synchronized with WRsignal at specified addresses. These signals can be used as chip-select signals for external peripherals.

Mode 3: P4.0−P4.3 are read/write strobe signals that are synchronized with RD or WRsignal at specified addresses. These signals can be used as chip-select signals for external peripherals.

When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode.

INT3

/

Two additional external interrupts,

and

INT3

, whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (

) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

Publication Release Date: June 2000

- 7 - Revision A1

Preliminary W78LE58

XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt information:

INTERRUPT SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 Serial Port 23H 4 IE.4 Timer/Counter 2 2BH 5 IE.5 External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

VECTOR ADDRESS

POLLING SEQUENCE WITHIN PRIORITY LEVEL

ENABLE REQUIRED SETTINGS

INTERRUPT TYPE EDGE/LEVEL

P4CONB (C3H)

BIT NAME FUNCTION

7, 6 P43FUN1

P43FUN0

00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address

range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address

range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0.

- 8 -

P4CONB (C3H), continued

A8) of address bus with the base address

BIT NAME FUNCTION

5, 4 P43CMP1

P43CMP0

3, 2 P42FUN1

P42FUN0

1, 0 P42CMP1

P42CMP0

Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register

P43AH, P43AL. 01: Compare the 15 high bits (A15−A1) of address bus with the base address

register P43AH, P43AL. 10: Compare the 14 high bits (A15−A2) of address bus with the base address

register P43AH, P43AL. 11: Compare the 8 high bits (A15−

register P43AH, P43AL. The P4.2 function control bits which are the similar definition as P43FUN1,

P43FUN0. The P4.2 address comparator length control bits which are the similar

definition as P43CMP1, P43CMP0.

P4CONA (C2H)

BIT NAME FUNCTION

7, 6 P41FUN1

P41FUN0

5, 4 P41CMP1

P41CMP0

3, 2 P40FUN1

P40FUN0

1, 0 P40CMP1

P40CMP0

The P4.1 function control bits which are the similar definition as P43FUN1, P43FUN0.

The P4.1 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.

The P4.0 function control bits which are the similar definition as P43FUN1, P43FUN0.

The P4.0 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.

Preliminary W78LE58

P2ECON (AEH)

BIT NAME FUNCTION

7 P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe

signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal.

= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. 6 P42CSINV The similarity definition as P43SINV. 5 P41CSINV The similarity definition as P43SINV. 4 P40CSINV The similarity definition as P43SINV. 3 - Reserve 2 - Reserve 1 - 0 0 - 0

Publication Release Date: June 2000

- 9 - Revision A1

Preliminary W78LE58

Port 4 Base Address Registers P40AH, P40AL:

The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address.

P41AH, P41AL:

The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address.

P42AH, P42AL:

The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address.

P43AH, P43AL:

The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address.

P4 (D8H)

BIT NAME FUNCTION

7 - Reserve 6 - Reserve 5 - Reserve 4 - Reserve 3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0. 2 P42 Port 4 Data bit. which outputs to pin P4.2 at mode 0. 1 P41 Port 4 Data bit. which outputs to pin P4.1at mode 0. 0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0.

Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H−1237H and positive polarity, and P4.1−P4.3 are used as general I/O ports.

MOV P40AH,#12H MOV P40AL,#34H ; Base I/O address 1234H for P4.0 MOV P4CONA,#00001010B ; P4.0 a write strobe signal and address line A0 and A1 are masked. MOV P4CONB,#00H ; P4.1−P4.3 as general I/O port which are the same as PORT1 MOV P2ECON,#10H ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity

MOV CHPENR,#00H ; Disable CHPCON write attribute.

Then any instruction MOVX @DPTR,A (with DPTR = 1234H−1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4,#XX will output the bit3 to bit1 of data #XX to pin P4.3−P4.1.

; default is negative.

- 10 -