Winbond Electronics W78L52P-24, W78L52F-24, W78L52-24 Datasheet

W78L52

INT2

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78L52 microcontroller supplies a wider frequency and supply voltage range than most 8-bit microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller series. The W78L52 contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O

port (Port 4) and two additional external interrupts ( watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.

The W78L52 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.

FEATURES

• Fully static design

• Supply voltage of 1.8V to 5.5V

• DC-24 MHz operation

• 256 bytes of on-chip scratchpad RAM

• 8K bytes of on-chip mask ROM

• 64K bytes program memory address space

• 64K bytes data memory address space

• Four 8-bit bidirectional ports

• Three 16-bit timer/counters

• One full duplex serial port

• Eight-source, two-level interrupt capability

• One extra 4-bit bit-addressable I/O port

, INT3), three 16-bit timer/counters, one

• Two additional external interrupts

• Watchdog timer

• EMI reduction mode

• Built-in power management

• Code protection

• Packages:

− DIP 40: W78L52-24

− PLCC 44: W78L52P-24

− QFP 44: W78L52F-24

/ INT3

Publication Release Date: January 1999

- 1 - Revision A2

PIN CONFIGURATIONS

40-Pin DIP (W78L52)

T2, P1.0

T2EX, P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST RXD, P3.0 TXD, P3.1

INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

WR, P3.6

RD, P3.7

XTAL2 XTAL1

VSS

W78L52

VDD1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39

P0.0, AD0

38

P0.1, AD1

P0.2, AD2

37 36

P0.3, AD3

35

P0.4, AD4

P0.5, AD5

34 33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

P2.5, A13

26 25

P2.4, A12

P2.3, A11

24 23

P2.2, A10

22

P2.1, A9

P2.0, A8

21

P1.5 P1.6 P1.7

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

44-Pin PLCC (W78L52P)

/

T

I

P

1

.

3

4

6 5 4 3

7 8 9 10 11 12 13 14 15 16

17

P

3

.

7

6

,

/

R

W

D

R

2 E X ,

P

P 1

1 .

. 1

2

X

T

A

L

1

2

A

N

T

D

T

2

0

3

,

P

1

V

0

4

.

D

.

0

D

0

2

2 1 44 43 42

V

P

S

2

4

S

.

1

0

,

A

9

8

44-Pin QFP (W78L52F)

/

T

I

2

N

T

E

A

D

3

1

2

,

P

0

.

3

2

1

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

2

.

3

4

2

,

A

1

2

0

P1.5 P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4

T1, P3.5

1 2

5 6 7 8 9 10

3 4

11

P 1 . 4

44

12

P 3 . 6 , / W R

P 1 . 3

43 42 41

P 3 . 7 , / R D

2

X

,

P

1

.

0

2

1

40 39 38 37 36 35

X

V

X

T

S

T

A

S

A

L

1

2

T 3 , P

V

4

D

.

D

2

P

2

4

.

0

, A 8

A

D

3

2

1

0

,

P

0

.

3

1

2

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P

2

.

4

3

2

1

,

A

1

9

1

2

0

- 2 -

W78L52

INT0

INT1

WR

RD

INT2

EA

PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data P3.1 TXD Serial Transmit Data P3.2

P3.3 P3.4 T0 Timer 0 Input

P3.5 T1 Timer 1 Input P3.6

P3.7

External Interrupt 0

External Interrupt 1

Data Write Strobe

Data Read Strobe

P4.0−P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources (

External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78C32 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor.

- 3 - Revision A2

/ INT3 ).

Publication Release Date: January 1999

W78L52

PSEN

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high impedance state during reset with a weak pull-up.

Program Store Enable Output, active low. address/data bus during fetch and MOVC operations.

enables the external ROM onto the Port 0

goes to a high impedance state during

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VDD

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

P1.0

~

P1.7

P3.0 ~ P3.7

P4.0 ~ P4.3

INT2

INT3

Port

1

Port

3

4

Interrupt

UART

Port 1

Latch

Timer

Port 3

Latch

Port 4

Latch

ACC

2

Oscillator

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

0

1

ALU

SFR RAM

Address

256 bytes

RAM & SFR

8K bytes

ROM

Watchdog

Timer

Reset Block

T2T1

B

Stack

Pointer

Power control

Port 0 Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port 0

Port 2

P0.0 ~ P0.7

P2.0 ~ P2.7

XTAL1 PSENALE GNDVDDRSTXTAL2

- 4 -

W78L52

FUNCTIONAL DESCRIPTION

The W78L52 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64 K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78L51. Timer 2 is a special feature of the W78L52: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78L52 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L52 relatively insensitive to duty cycle variations in the clock.

Crystal Oscillator

The W78L52 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts when VDD = 5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L52 is used with an external RC network. The reset logic also has

Publication Release Date: January 1999

- 5 - Revision A2

W78L52

INT2

a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts

, INT3 have been added to either the PLCC or QFP package. And description follows:

1.

Two additional external interrupts, interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

/ INT3

and INT3 , whose functions are similar to those of external

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

INTERRUPT

SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 Serial Port 23H 4 IE.4 Timer/Counter 2 2BH 5 IE.5 External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

- 6 -

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL