Winbond Electronics W78E54P-40, W78E54P-24, W78E54P-16, W78E54M-40, W78E54M-24 Datasheet

W78E54

INT2

INT2

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78E54 is an 8-bit microcontroller that is functionally compatible with the W78C54, except that
the mask ROM is replaced by a flash EEPROM with a size of 16 KB. To facilitate programming and
verification, the flash EEPROM inside the W78E54 allows the program memory to be programmed
and read electronically. Once the code is confirmed, the user can protect the code for security.

The W78E54 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the
market. It is functionally compatible with the industry-standard 80C52 microcontroller series, except

that one extra 4-bit bit-addressable I/O port (Port 4) and two additional external interrupts (

INT3 ).

The W78E54 contains four 8-bit bidirectional and bit-addressable I/O ports, three 16-bit
timer/counters, and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 16 KB flash EEPROM for application
programs.

The W78E54 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

,

FEATURES

• 8-bit CMOS microcontroller

• Fully static design

• Low standby current at full supply voltage

• DC-40 MHz operation

• 256 bytes of on-chip scratchpad RAM

• 16 KB electrically erasable/programmable EPROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bidirectional ports

• One extra 4-bit bit-addressable I/O port, additional

(available on 44-pin PLCC/QFP package)

• Three 16-bit timer/counters

• One full duplex serial port

• Boolean processor

• Eight-source, two-level interrupt capability

• Built-in power management

• Code protection mechanism

• Packages:

− DIP 40: W78E54-16/24/40

− PLCC 44: W78E54P-16/24/40

− QFP 44: W78E54F-16/24/40

− TQFP 44: W78E54M-16/24/40

/ INT3

Publication Release Date: November 1997

- 1 - Revision A2

PIN CONFIGURATIONS

40-Pin DIP (W78E54)

T2, P1.0

T2EX, P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
RXD, P3.0
TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

W78E54

VCC1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39

P0.0, AD0

38

P0.1, AD1

37

P0.2, AD2

36

P0.3, AD3

P0.4, AD4

35
34

P0.5, AD5

33

P0.6, AD6

P0.7, AD7

32
31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

23

P2.2, A10

P2.1, A9

22
21

P2.0, A8

44-Pin PLCC (W78E54P)

T
2

T

E

2

X

,

,

P

P

P

P

P1.5
P1.6
P1.7

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

P
1
.
4

6 5 4 3

7
8
9
10
11
12
13
14
15
16

17

P
3
.
6
,
/
W
R

1
.
3

P
3
.
7
,
/
R
D

1

1
.

.

1

2

X

X

T

T

A

A

L

L

1

2

1
.
0

2 1 44 43 42

V
S
S

44-Pin QFP/TQFP (W78E54F/W78E54M))

/

P
1
.
4

P
3
.
6
,
/
W
R

P

P

1

1

.

.

2

3

43 42 41

X

P

T

3

A

.

L

7

2

,
/
R
D

T

I

2

N

T

E

T

2

X

3

,

,

,

P

P

P

1

1

4

.

.

.

0

1

2

403938 37 36

X

V

P

T

S

4

A

S

.

L

0

1

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

V

0

0

.

.

C

.

.

3

1

C

2

0

34

3544

P

P

P

P

2

2

2

2

.

.

.

.

3

1

0

2

,

,

,

,

A

A

A

A

1

1

9

8

1

0

P0.4, AD4

33
32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P
2
.
4
,
A
1
2

/
I
N
T
3
,
P

V

4

C

.

C

2

P

P

2

4

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

2

1

0

40

41

P

P

P

2

2

2

.

.

.

3

2

1

,

,

,

A

A

A

1

9

1

1

0

P0.4, AD4

39
38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P
2
.
4
,
A
1
2

RXD, P3.0
INT2, P4.3

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

P1.5
P1.6
P1.7

RST

1
2

3

4
5
6
7
8
9
10

11

12

- 2 -

W78E54

INT2

PIN DESCRIPTION

The W78E54 has two operating modes, normal and flash. In normal mode, the W78E54 corresponds
to the W78C54. In flash mode, the user (the maker of the flash EEPROM writer) can access the flash
EEPROM.

P0.7−P0.0 Port 0, Bits 7−0

MODE DESCRIPTION

Normal Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a

multiplexed low order address/data bus during accesses to external memory.

Flash This port provides the data bus during access to the flash EEPROM.

P1.7−P1.0 Port 1, Bits 7−0

MODE DESCRIPTION

Normal Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins

P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2
capture/reload trigger), respectively.

Flash This port provides the low-order address bus during access to the flash EEPROM.

P2.7−P2.0 Port 2, Bits 7−0

MODE DESCRIPTION

Normal Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port

also provides the upper address bits for accesses to external memory..

Flash This port provides the high-order address bus during access to the flash EEPROM.

P3.7−P3.0 Port 3, Bits 7−0

MODE DESCRIPTION

Normal Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits

have alternate functions.

Flash

P3.3−P3.0 and P3.7−P3.6 are the flash mode configuration pins, Input.
P3.3−P3.0 and P3.7−P3.6 are configured to select or execute the flash operations. For

details, see Flash Operations.

P4.3−P4.0 Port 4, Bits 3−0 (available on 44-pin PLCC/QFP package)

MODE DESCRIPTION

Normal Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative

function pins. It can be used as general I/O pins or external interrupt input sources
(

/INT3 ).

Publication Release Date: November 1997

- 3 - Revision A2

Flash No function in this mode.

EA

PSEN

This pin

PSEN

PSEN

EA/VPP

MODE DESCRIPTION

W78E54

Normal

Flash VPP, Program Power supply pin, Input.

External Access, Input, active low.

,

This pin forces the processor to execute a program from the external ROM. When the
internal flash EEPROM is accessed as in the W78C54, this pin should be kept high.

This pin accepts the high voltage (12V) needed for programming the flash EEPROM.

RST

MODE DESCRIPTION

Normal RST, Reset, Input, active high.

This pin resets the processor. It must be kept high for at least two machine cycles in
order to be recognized by the processor.

Flash Flash mode configuration pin, Input, active high.

RST is used to configure the flash operations. For details, see Flash Operations.

ALE

MODE DESCRIPTION

Normal

Flash Flash mode configuration pin, Input, active low.

Address Latch Enable, Output, active high.

ALE,
ALE is used to enable the address latch that separates the address from the data on

Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped
during external data memory accesses. ALE goes to a high impedance state with a
weak pull-up during reset state.

ALE is used to configure the flash operations. For details, see Flash Operations.

PSEN

MODE DESCRIPTION

Normal

MOVC operations.
reset state

Flash Flash mode configuration pin, Input, active high.

Program Store Enable, Output, active low.

,

enables the external ROM onto the Port 0 address/data bus during fetch and

goes to a high impedance state with a weak pull-up during

is used to configure the flash operations. For details, see Flash Operations.

XTAL1

MODE DESCRIPTION

- 4 -

W78E54

Normal Crystal 1. This is the crystal oscillator input. This pin may be driven by an external

clock.

Flash Connect to VSS.

XTAL2

MODE DESCRIPTION

Normal Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

Flash No function in this mode.

VSS, VCC

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

Publication Release Date: November 1997

- 5 - Revision A2

W78E54

P1.0

~

P1.7

P3.0
~
P3.7

P4.0
~
P4.3

INT2

INT3

Port

1

Port

Port

Port 1
Latch

ACC

Interrupt

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

T1

ALU

Reset Block

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4

Latch

Oscillator

T2

SFR RAM

Address

256 bytes

RAM & SFR

B

Stack

Pointer

Power control

Port 0
Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port

Port

2

P0.0

0

~
P0.7

P2.0
~
P2.7

XTAL1

PSENALE

RSTXTAL2

Vcc

Vss

- 6 -

W78E54

FUNCTIONAL DESCRIPTION

The W78E54 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78E54: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto­reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

Clock

The W78E54 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E54 relatively insensitive to duty cycle
variations in the clock.

Crystal Oscillator

The W78E54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

Publication Release Date: November 1997

- 7 - Revision A2