Datasheet W49F002UT90B, W49F002UT70B, W49F002UT12B, W49F002UP90B, W49F002UP70B Datasheet (Winbond Electronics)

W49F002U

256K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

•

Single 5-volt operations:

− 5-volt Read

− 5-volt Erase

− 5-volt Program

•

Fast Program operation:

− Byte-by-Byte programming: 35 µS (typ.)

•

Fast Erase operation: 100 mS (typ.)

•

Fast Read access time: 70/90/120 nS

•

Endurance: 10K cycles (typ.)

•

Ten-year data retention

•

Hardware data protection

•

One 16K byte Boot Block with Lockout

protection

•

Two 8K byte Parameter Blocks

Two Main Memory Blocks (96K, 128K) Bytes

•

Low power consumption

−

Active current: 25 mA (typ.)

−

Standby current: 20 µA (typ.)

•

Automatic program and erase timing with

internal VPP generation

•

End of program or erase detection

− Toggle bit

− Data polling

•

Latched address and data

•

TTL compatible I/O

•

JEDEC standard byte-wide pinouts

•

Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

Publication Release Date: April 2000

- 1 - Revision A2

W49F002U

1

234

7

9

11

12

13

14

15

16

323130

GND

V

DD

10

E

2

3

6

8

12

131415

V

A13

DD

DQ2

3C000

CE

OE

WE

PIN CONFIGURATIONS

RESET

A16
A15
A12

5

A7

6

A6

DQ0

A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

A7
A6
A5
A4
A3
A2
A1
A0

32-pin

8

DIP

10

/
R
E

A

S

1

E
T

6

32-pin
PLCC

G

D

N

Q

D

3

/

V
D

W

D

D

D

Q

Q

4

5

A

A

1

1

2

5

5
6
7

8

9

11
12
13

D

D

Q

Q

1

2

BLOCK DIAGRAM

V

DD

WE
A17

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

A
1
7

3031321234

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

20191817161514

D
Q
6

V

SS

CE

OE

WE

CONTROL

RESET

A0

.

DECODER

.

A17

PIN DESCRIPTION

OUTPUT
BUFFER

BOOT BLOCK

16K BYTES

PARAMETER
BLOCK1

8K BYTES

PARAMETER

BLOCK2

8K BYTES

MAIN MEMORY

BLOCK1

96K BYTES

MAIN MEMORY

BLOCK2

128K BYTES

DQ0

.
.

DQ7

3FFFF

3BFFF

3A000
39FFF

38000
37FFF

20000
1FFFF

00000

32

A11

A14

A17

RESET

A16
A15
A12

A9
A8

5

WE

9
10
11

A7
A6
A5

16

A4

32-pin
TSOP

OE
A10

31
30

CE
DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24
23

DQ1

22

DQ0

21

A0

20

A1

19

A2

18

A3

17

- 2 -

SYMBOL PIN NAME

RESET
A0−A17

DQ0−DQ7

Reset
Address Inputs

Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable

VDD Power Supply

GND Ground

W49F002U

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F002U is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Reset Operation

The reset input pin can be used in some application. When RESET pin is at high state, the device is
in normal operation mode. When
at high impedance state. As the high state re-asserted to the RESET pin, the device will return to
read or standby mode, it depends on the control signals. When the system drives the RESET pin low

for at least a period of 500 nS, the device immediately terminates any operation in progress duration
of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By

applying the 12V to
lockout function is enabled.

RESET

RESET

pin, the boot block can be reprogrammed even though the boot block

pin is at low state, it will halts the device and all outputs are

Boot Block Operation

There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in
the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See
Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is
set the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed with the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function can no longer erase the boot block.

There is one condition that the lockout feature can be overridden. Just apply 12V to
lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the

RESET
In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform
software command code sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
(hex)". If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the

DQ0

erased/programmed.
To return to normal operation, perform a three-byte command code sequence (or an alternate single­byte command) to exit the identification mode. For the specific code, see Command Code for
Identification/Boot Block Lockout Detection.

pin return to TTL level, the lockout feature will be activated again.

of output data is "0 ," the lockout feature is inactivated and the block can be

RESET

pin, the

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command code sequence. After the command
loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed as fast as 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The entire memory array will be erased to FF hex. by the chip erase

Publication Release Date: April 2000

- 3 - Revision A2

W49F002U

operation if the boot block programming lockout feature is not activated. Once the boot block lockout
feature is activated, the whole chip erase function will erase the two main memory blocks and the two
parameter blocks but not the boot block. The device will automatically return to normal read mode
after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

There are four sectors: two main memory blocks and two parameters blocks which can be erased
individually by initiating a six-byte command code sequence. Sector address is latched on the falling

edge of WE signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of WE
in this cycle. After the command loading cycle, the device enters the internal sector erase mode,
which is automatically timed and will be completed as fast as 100 mS (typical). The host system does
not require to provide any control or timing during this operation. The device will automatically return
to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect
the end of erase cycle.

When different sector address is loaded in the sixth cycle for sector erase command, the
correspondent sectors will be erased automatically; that these sections will be erased independedntly.
For detail sector to be erased information, please refer to the

Program Operation

The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and
two parameter blocks and/or boot block from "0" to "1") is needed before programming.

The program operation is initiated by a 4-byte command code sequence (see Command Codes for
Byte Programming). The device will internally enter the program operation immediately after the byte­program command is entered. The internal program timer will automatically time-out (50 µS max. ­TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can
be used to detect end of program cycle.

Table of Command Definition

.

Hardware Data Protection

The integrity of the data stored in the W49F002U is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

DD

(2) V

2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Power Up/Down Detection: The programming operation is inhibited when VDD is less than

Data Polling (DQ7)- Write Status Detection

The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.
When the W49F002U is in the internal program or erase cycle, any attempt to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle,
and become logical "1" or true data when the erase cycle has been completed.

- 4 -

W49F002U

CE OE WE

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49F002U provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from
address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a
three-byte command code sequence or an alternate one-byte command code sequence (see
Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

(VHH = 12V ± 5%)

MODE PINS

Read VIH VIL VIL VIH AIN Dout
Write VIH VIL VIH VIL AIN Din
Standby VIH VIH X X X High Z
Write Inhibit VIH X VIL X X High Z/DOUT
VIH X X VIH X High Z/DOUT
Output Disable VIH X VIH X X High Z
Reset Mode VIL X X X X High Z
Product ID VIH VIL VIL VIH

VIH VIL VIL VIH

RESET

ADDRESS DQ.

A0 = VIL; A1−A17 = VIL;
A9 = VHH

A0 = VIH; A1−A17 = VIL;
A9 = VHH

Manufacturer Code DA (Hex)

Device Code 0B (Hex)

Publication Release Date: April 2000

- 5 - Revision A2

TABLE OF COMMAND DEFINITION

(1)

W49F002U

COMMAND NO.

OF

DESCRIPTION

Read 1 AIN D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN D
Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

Notes:

1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA means: Sector Address

If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,
nothing will happen and the device will go back to read mode after 100nS.

If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.
If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.
If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.
If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.

If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.

(2)

3 5555 AA 2AAA 55 5555 F0

(2)

1 XXXX F0

1ST

CYCLE

OUT

2ND

CYCLE

3RD

CYCLE

4TH

CYCLE

5TH

CYCLE

IN

6TH

CYCLE

(3)

30

- 6 -

Command Codes for Byte Program

Command Flow

COMMAND SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-address Programmed-data

Byte Program Flow Chart

Byte Program

W49F002U

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data AA

address 2AAA

to

address 5555

Load data 55

to

Load data A0

to

address 5555

Load data Din

to

programmed-

address

Pause T

BP

Exit

Publication Release Date: April 2000

- 7 - Revision A2

Command Codes for Chip Erase

BYTE SEQUENCE ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 10H

Chip Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

W49F002U

Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause T

EC

Exit

- 8 -

Command Codes for Sector Erase

BYTE SEQUENCE ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write SA* 30H

Sector Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

W49F002U

Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

SA : For details, see the page 6 .

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 30

to

address SA*

Pause T

EC

Exit

Publication Release Date: April 2000

- 9 - Revision A2

W49F002U

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT(6)

ADDRESS DATA ADDRESS DATA

1 Write 5555 AA 5555H AAH
2 Write 2AAA 55 2AAAH 55H
3 Write 5555 90 5555H F0H

Pause 10 µS Pause 10 µS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product
Identification
Entry (1)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Product

Identification
and Boot Block
Lockout Detection
Mode (3)

Read address = 0000

data = DA

(2)

Product
Identification Exit(6)

Load data 55

to

address 2AAA

Load data 90

to

address 5555

Pause 10 S

µ

Read address = 0001

Read address = 0002

data =in DQ0= "1" / "0"

(2)

(4)

Load data F0

to

address 5555

Normal Mode

µ

(5)

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 = " 0 ,"

the lockout feature is inactivated and the boot block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout

detection.

- 10 -

Command Codes for Boot Block Lockout Enable

Boot Block Lockout

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 40H

Pause TBP

Boot Block Lockout Enable Acquisition Flow

Feature Set Flow

Load data AA

to

address 5555

W49F002U

Notes for boot block lockout enable:
Data Format: DQ7−DQ0 (Hex)

Address Format: A14−A0 (Hex)

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Pause T

BP

Exit

Publication Release Date: April 2000

- 11 - Revision A2

W49F002U

CE=OE

CE

CE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to V
Operating Temperature 0 to +70
Storage Temperature -65 to +150

D.C. Voltage on Any Pin to Ground Potential except OE
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V

Voltage on OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

DC Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

ss

Potential -0.5 to +7.0 V

-0.5 to VDD +1.0 V

-0.5 to 12.5 V

°C
°C

PARAMETER SYM.

Power Supply
Current

Standby VDD
Current (TTL input)

Standby VDD
Current

(CMOS input)
Input Leakage

Current
Output Leakage

Current
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VDD +0.5 V
Output Low Voltage VOL I
Output High Voltage VOH I

MIN. TYP. MAX.

ICC

Address inputs = VIL/VIH, at f = 5 MHz

ISB1

Other inputs = VIL/VIH

ISB2

Other inputs = VDD -0.3V/GND

IN

ILI V

ILO V

OUT

OL
OH

TEST CONDITIONS LIMITS UNIT

= VIL, WE= VIH, all DQs open

= VIH, all DQs open

= VDD -0.3V, all DQs open

= GND to VDD - - 10

= GND to VDD - - 10

= 2.1 mA - - 0.45 V

= -0.4 mA 2.4 - - V

- 25 50 mA

- 2 3 mA

- 20 100

µ

µ

µ

A

A

A

- 12 -

W49F002U

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 5 mS

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O Pin Capacitance C

I/O

V

Input Capacitance CIN V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 100 pF for 120 nS;

I/O

= 0V 12 pf

IN

= 0V 6 pf

CL = 30 pF for 70 nS /90 nS

µ

S

AC Test Load and Waveform

+5V

1.8K

Ω

D

OUT

30 pF for 70nS / 90nS
100 pF for 120nS

(Including Jig and Scope)

Input

3V

0V

1.5V

Test Point

Publication Release Date: April 2000

- 13 - Revision A2

Output

1.5V

Test Point

1.3K

Ω

AC Characteristics, continued

CE

OE

Read Cycle Timing Parameters

(VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C)

PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

W49F002U

Read Cycle Time T
Chip Enable Access Time T
Address Access Time T
Output Enable Access Time T

CE Low to Active Output
OE Low to Active Output

High to High-Z Output

High to High-Z Output

Output Hold from Address Change T

MIN. MAX. MIN. MAX. MIN. MAX.

T
T
T

T

RC
CE
AA
OE
CLZ

OLZ

CHZ

OHZ

OH

70 - 90 - 120 - nS

- 70 - 90 - 120 nS

- 70 - 90 - 120 nS

- 35 - 40 - 50 nS

0 - 0 - 0 - nS
0 - 0 - 0 - nS

- 25 - 25 - 30 nS

- 25 - 25 - 30 nS

0 - 0 - 0 - nS

Write Cycle Timing Parameters

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Address Setup Time T
Address Hold Time T

WE

and CE Setup Time

WE

and CE Hold Time

OE

High Setup Time

OE High Hold Time
CE Pulse Width

WE

Pulse Width

WE

High Width
Data Setup Time T
Data Hold Time T
Byte Programming Time T
Erase Cycle Time T

AS
AH
CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

DS
DH
BP
EC

0 - - nS

50 - - nS

0 - - nS
0 - - nS
0 - - nS

0 - - nS
100 - - nS
100 - - nS
100 - - nS

50 - - nS
10 - - nS

- 35 50

µS

- 0.1 0.2 S

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

- 14 -

W49F002U

OE

CE

OE

CE

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

to Data Polling Output Delay

to Data Polling Output Delay

to Toggle Bit Output Delay

to Toggle Bit Output Delay

TIMING WAVEFORMS

Read Cycle Timing Diagram

MIN. MAX. MIN. MAX. MIN. MAX.

T
T
T
T

OEP

CEP

OET

CET

- 35 - 40 - 50 nS

- 70 - 90 - 120 nS

- 35 - 40 - 50 nS

- 70 - 90 - 120 nS

Address A17-0

CE

OE

WE

DQ7-0

High-Z

T

RC

T

CE

T OE

T

OLZ

V

IH

T

T

CLZ

Data Valid

T

OH

AA

T

T

Data Valid

CHZ

OHZ

High-Z

Publication Release Date: April 2000

- 15 - Revision A2

Timing Waveforms, continued

WE

CE

Controlled Command Write Cycle Timing Diagram

W49F002U

Address A17-0

CE

OE

WE

DQ7-0

T

AS

T

CS

T

OES

T

AH

T

WP

Controlled Command Write Cycle Timing Diagram

AS

T

AH

T

T

DS

Data Valid

T

CH

T

OEH

T

WPH

T

DH

Address A17-0

CE

TOES

OE

WE

DQ7-0

High Z

- 16 -

TCP

Data Valid

TDS

TCPH

TOEH

TDH

Timing Waveforms, continued

DATA

Program Cycle Timing Diagram

W49F002U

Byte Program Cycle

Address A17-0

DQ7-0

CE

OE

WE

5555

WP

T

Byte 0

Polling Timing Diagram

Address A17-0

An An

AA

TWPH

Byte 1

55552AAA

Byte 2

Address

A055

Byte 3

Data-In

BP

T

Internal Write Start

An

An

WE

T CEP

CE

OE

DQ7

TOEH

T

OEP

X

X

TECTBP or

X

OES

T

X

Publication Release Date: April 2000

- 17 - Revision A2

Timing Waveforms, continued

Toggle Bit Timing Diagram

Address A17-0

WE

CE

W49F002U

OEH T

T

OE

DQ6

TBP orTEC

Boot Block Lockout Enable Timing Diagram

Six byte code for Boot Block
Lockout Feature Enable

Address A17-0

DQ7-0

CE

5555

AA

2AAA

5555

55 80

5555 2AAA

AA

55

OES

5555

40

OE

WE

WP

T

SB0

T

WPH

SB1

SB2

- 18 -

SB3

SB4

SB5

EC

T

Timing Waveforms, continued

Chip Erase Timing Diagram

W49F002U

Six-byte code for 5V-only software
chip erase

Address A17-0

DQ7-0

CE

OE

WE

5555 2AAA

AA

T

WP

SB0

Sector Erase Timing Diagram

Address A17-0

5555

5555 5555 2AAA

55 80

T

WPH

SB1

2AAA

SB2

Six-byte code for 5V-only software
Main Memory Erase

5555

5555

AA

SB3

5555 2AAA SA

SB4

55

SB5

10

T

Internal Erase starts

EC

T

WPH

55 80

SB1

SB2

SB3

AA

SB4

55

30

SB5

T

EC

Internal Erase starts

DQ7-0

CE

OE

WE

SA = Sector Address

T

SB0

AA

WP

Publication Release Date: April 2000

- 19 - Revision A2

ORDERING INFORMATION

ACCESS

S)

W49F002U

PART NO.

TIME

(n

W49F002U-70B 70 50 100 (CMOS) 32-pin DIP 10K
W49F002U-90B 90 50 100 (CMOS) 32-pin DIP 10K
W49F002U-12B 120 50 100 (CMOS) 32-pin DIP 10K
W49F002UT70B 70 50 100 (CMOS)
W49F002UT90B 90 50 100 (CMOS)
W49F002UT12B 120 50 100 (CMOS)
W49F002UP70B 70 50 100 (CMOS) 32-pin PLCC 10K
W49F002UP90B 90 50 100 (CMOS) 32-pin PLCC 10K
W49F002UP12B 120 50 100 (CMOS) 32-pin PLCC 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

3. Winbond withholds a Boot Block options for Bottom Boot use. Please contact Winbond FAEs for detail information.

POWER

SUPPLY

CURRENT

MAX.

(mA)

STANDBY

VDD

CURRENT

MAX.

(µA)

PACKAGE CYCLE

32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)

10K
10K
10K

- 20 -

PACKAGE DIMENSIONS

32-pin P-DIP

W49F002U

32

1E

1

2

A

A

L

32-pin PLCC

5

13

14 20

L

θ

Seating Plane

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.155

0.150

2

A

0.016

0.018

B

0.050 1.27

B1
c

0.010

D

S

B

1

e

1

B

17

16

1A

Base Plane

Seating Plane

E

e

A

a

c

Symbol

H

E

E

1

324

30

29

D

H D

21

G D

0.008

1.650 1.660 41.91 42.16

D

0.6000.590

E

0.545

E

0.550

1

e

1

0.120

0.130

L

0 15

a

0.6500.630 16.00 16.51

e

A

S

Notes:

1.Dimensions D Max. & S include mold flash or
tie bar burrs.

2.Dimension E1 does not include interlead flash.

3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.

4.Dimension B1 does not include dambar

protrusion/intrusion.

5.Controlling dimension: Inches

6.General appearance spec. should be based on
final visual inspection spec.

Dimension in Inches Dimension in mm

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b
b

c

D

E
e

G
G
H
H
L

y

θ

0.028

1

0.016

0.018

0.008

0.010

0.547

0.550

0.447

0.450

0.050

0.490

D

0.390

0.410

E

0.585

0.590

D

0.485

0.49

E

0.075

0.090

°

0

Dimension in mm

0.210 5.33

0.25

0.160

3.81

0.41

0.022

0.0540.048

0.014

0.20

0.610

14.99

0.555

0.110

2.29 2.54 2.790.090 0.100

0.140

3.05

0.670

0.085

.

0.140

0.50

0.66 0.81

0.41

0.20

13.89

11.35

1.12 1.420.044 0.056

12.45

9.91

14.86

12.32

1.91

°

10

0

°

2.802.67 2.93

0.71

0.46

0.25

13.97

11.43

1.27

12.9

10.41

14.99

12.45

2.29

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.5300.51

0.430

0.595

0.495

0.095

0.004

15.24

13.9713.84

3.94

4.06

0.46

0.56

1.371.22

0.25

0.36

15.49

14.10

3.30

3.56
150

17.02

2.16

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

Notes:

c

2A

A

e

b

1b

E

G

A1

y

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final
visual inspection sepc.

Publication Release Date: April 2000

- 21 - Revision A2

Package Dimensions, continued

32-pin TSOP

M

e

0.10(0.004)

b

θ

L

L

1

W49F002U

H

D

D

c

E

A

A

2

1

A

Y

Dimension in Inches

Symbol

Min. Nom.

__

A

0.002

A

1

0.037

2

A

0.007 0.008

b

c

0.005 0.006

0.720 0.724

D

0.311 0.315

E

0.780 0.787

HD

__

e

0.016 0.020

L

__

L

1

0.000 0.004

Y

θ

Note:
Controlling dimension: Millimeters

Max.

__

0.047

__ __

0.006

0.041

0.039

0.009

0.007

0.728

0.319

0.795

__

0.020

0.024

0.031

__

1

3 5

__

Dimension in mm

Min. Nom.

__

__

0.05

0.95

0.17

0.20 0.23

0.12

0.15 0.17

18.30

18.40 18.50

7.90

8.00 8.10

19.80

20.00

__

0.50

0.40

0.50 0.60

__

0.80

__

0.00
1

3

Max.

1.20

0.15

1.051.00

20.20

__

__

0.10
5

- 22 -

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Nov. 1999 - Renamed from W49F002/B/U/N
A2 Apr. 2000

14

1, 13−15, 20

Add the 120 nS bin
Change Tbp(typ.) from 10 µS to 35 µS

Change Tec(max.) from 1 Sec to 0.2 Sec

W49F002U

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: April 2000

- 23 - Revision A2