Datasheet W29EE011T90B, W29EE011T15B, W29EE011T-90, W29EE011T-15, W29EE011P90B Datasheet (Winbond Electronics)

W29EE011

128K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29EE011 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt program and erase operations

•

Fast page-write operations

− 128 bytes per page

− Page program cycle: 10 mS (max.)

− Effective byte-program cycle time: 39 µS

− Optional software-protected data write

•

Fast chip-erase operation: 50 mS

•

Read access time: 90/150 nS

•

Page program/erase cycles: 1K/10K

•

Ten-year data retention

•

Software and hardware data protection

•

Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

•

Automatic program timing with internal V

generation

•

End of program detection

− Toggle bit

− Data polling

•

Latched address and data

•

TTL compatible I/O

•

JEDEC standard byte-wide pinouts

•

Available packages: 32-pin 600 mil DIP,

TSOP, and PLCC

PP

Publication Release Date: July 1999

- 1 - Revision A12

W29EE011

1

234

7

910111213

14

1516323130

V

DD

E

2

3

6

8

DQ1

DQ2

V

A13

DD

CE

OE

WE

PIN CONFIGURATIONS

NC
A16
A15
A12

5

A7

6

A6
A5

8

A4

A3

A2

A1

A0

DQ0
DQ1
DQ2
GND

A

A

1

1

2

5

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

DQ0

D

D

Q

Q

1

2

A11

A9
A8

5

A14

NC

WE

9

NC

10

A16

11

A15

12

A12

13

A7

14

A6

15

A5

16 A3

A4

32-pin

DIP

A
1
6NC

32-pin
PLCC

G
N
D

32-pin
TSOP

29
28
27
26
25
24
23
22
21
20
19
18
17

/

V
D

W

N

D

C

1234

303132

29
28
27
26
25
24
23
22
21

20191817161514

D

D

D

D

Q

Q

Q

Q

4

5

3

6

BLOCK DIAGRAM

V

WE
NC

A14
A13
A8
A9
A11

OE
A10

CE
DQ7
DQ6
DQ5
DQ4
DQ3

A14
A13
A8
A9
A11
OE

A10
CE

DQ7

32

OE
A10

31
30

CE
DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24
23
22

DQ0

21
20

A0

19

A1
A2

18
17

PIN DESCRIPTION

DD

V

SS

CE
OE

WE

CONTROL

OUTPUT
BUFFER

DQ0
DQ7

A0

.
.

DECODER

CORE

ARRAY

A16

SYMBOL PIN NAME

A0−A16

DQ0−DQ7

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable

VDD Power Supply

GND Ground

NC No Connection

.
.

- 2 -

W29EE011

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE011 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

µ

S, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional byte is loaded into the page buffer within 300 µS (T

from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last
rising edge of WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer

must have the same page address. A0 to A6 specify the byte address within the page. The bytes may
be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

BLC

) of 200

BLCO

)

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to
a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.

The W29EE011 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
software data protection feature. To reset the device to unprotected mode, a six-byte command
sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.

Publication Release Date: July 1999

- 3 - Revision A12

W29EE011

Hardware Data Protection

The integrity of the data stored in the W29EE011 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

DD

(2) V

3.8V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ7)-Write Status Detection

The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE011 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded
during the page/byte-load cycle will receive the complement of the true data. Once the programming
cycle is completed. DQ7 will show the true data.

Toggle Bit (DQ6)-Write Status Detection

In addition to data polling, the W29EE011 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.

Power Up/Down Detection: The programming operation is inhibited when VDD is less than

5-Volt-only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.

- 4 -

TABLE OF OPERATING MODES

CE OE WE

Operating Mode Selection

Operating Range = 0 to 70°C (Ambient Temperature), V

MODE PINS

DD =

5V ±10%, VSS = 0V, VHH = 12V

W29EE011

Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby VIH X X X High Z
Write Inhibit X VIL X X High Z/D
X X VIH X High Z/D
Output Disable X VIH X X High Z
5-Volt Software Chip Erase VIL VIH VIL AIN DIN
Product ID VIL VIL VIH A0 = VIL; A1-A16 = VIL;

A9 = VHH

VIL VIL VIH A0 = VIH; A1-A16 = VIL;

A9 = VHH

ADDRESS DQ.

OUT
OUT

Manufacturer Code DA
(Hex)

Device Code
C1 (Hex)

Publication Release Date: July 1999

- 5 - Revision A12

W29EE011

Command Codes for Software Data Protection

BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H A0H 5555H 80H
3 Write - - 5555H AAH
4 Write - - 2AAAH 55H
5 Write - - 5555H 20H

Sofware Data Protection Acquisition Flow

Software Data Protection
Enable Flow

Software Data Protection
Disable Flow

(Optional page

load operation)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Sequentially load

up to 128 bytes

of page data

Pause 10 mS

Exit

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 20

to

address 5555

Pause 10 mS

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

- 6 -

Exit

Command Codes for Software Chip Erase

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 10H

Sofware Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

W29EE011

to

to

Notes for software chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Publication Release Date: July 1999

- 7 - Revision A12

Command Codes for Product Identification

BYTE SEQUENCE SOFTWARE PRODUCT

IDENTIFICATION ENTRY

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H 80H 5555H F0H
3 Write 5555H AAH - ­4 Write 2AAAH 55H - ­5 Write 5555H 60H - -

Pause 10 µS Pause 10 µS

Software Product Identification Acquisition Flow

Product Identification Entry(1)

Load data AA

to

address 5555

Product Identification Mode(2, 3)

W29EE011

SOFTWARE PRODUCT

IDENTIFICATION EXIT

Product Identification Exit(1)

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 60

to

address 5555

Pause 10

µ

Notes for software product identification:
(1) Data format: DQ7−DQ0 (Hex); address format: A14−A0 (Hex).
(2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.

Read address = 0

data = DA

Read address = 1

data = C1

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data FO

to

address 5555

Pause 10

Normal Mode

mµS

(4)

- 8 -

W29EE011

CE

CE

CE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to V
Operating Temperature 0 to +70
Storage Temperature -65 to +150

D.C. Voltage on Any Pin to Ground Potential except OE
Transient Voltage (< 20 nS ) on Any Pin to Ground Potential -1.0 to V

Voltage on OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

ss

Potential -0.5 to +7.0 V

-0.5 to V

DD

+1.0 V

DD

+1.0 V

-0.5 to 12.5 V

°

C

°C

PARAMETER SYM.

MIN. TYP. MAX.

Power Supply Current ICC

TEST CONDITIONS LIMITS UNIT

= OE = VIL, WE = VIH,

- - 50 mA
all I/Os open
Address inputs = VIL/VIH,

at f = 5 MHz

Standby VDD
Current (TTL input)

Standby V

DD

Current

(CMOS input)
Input Leakage Current ILI V

Output Leakage

ISB1

ISB2

= VIH, all I/Os open

Other inputs = VIL/VIH

DD

= V

Other inputs = V

IN

= GND to VDD - - 1

ILO V

IN

= GND to VDD - - 10

-0.3V, all I/Os open

DD

-0.3V/GND

- 2 3 mA

- 20 100

µ

A

µ

A

µA

Current
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - V

DD

V

+0.5
Output Low Voltage VOL I
Output High Voltage VOH I

OL

= 2.1 mA - - 0.45 V

OH

= -0.4 mA 2.4 - - V

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU.READ 100

µ

S

Power-up to Write Operation TPU.WRITE 5 mS

Publication Release Date: July 1999

- 9 - Revision A12

W29EE011

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O Pin Capacitance C

I/O

V

Input Capacitance CIN V

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5V ±10%)

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V
Input Rise/Fall Time
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 30 pF for 70 nS and 100 pF for others.

AC Test Load and Waveforms

<

5 nS

I/O

= 0V 12 pF

IN

= 0V 6 pF

OUT

D

100 pF for 90/120/150 nS
30 pF for 70 nS
(Including Jig and Scope)

Input

3V

0V

Test Point

1.5V

+5V

1.8K ohm

1.3K ohm

Output

1.5V

Test Point

- 10 -

Read Cycle Timing Parameters

(VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM.

MIN. MAX. MIN. MAX.

T

T
T
T

RC
CE

AA

OE

CLZ

OLZ

CHZ

OHZ

OH

Read Cycle Time T
Chip Enable Access Time T
Address Access Time T
Output Enable Access Time T

CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output

Output Hold from Address Change T

Byte/Page-write Cycle Timing Parameters

W29EE011

W29EE011-90 W29EE011-15

90 - 150 - nS

- 90 - 150 nS

- 90 - 150 nS

- 45 - 70 nS

0 - 0 - nS
0 - 0 - nS

- 45 - 45 nS

- 45 - 45 nS

0 - 0 - nS

UNIT

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Write Cycle (Erase and Program) T
Address Setup Time T
Address Hold Time T

WE

and CE Setup Time

WE

and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
WE

Pulse Width
WE

High Width

Data Setup Time T
Data Hold Time T
Byte Load Cycle Time T
Byte Load Cycle Time-out T

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

WC
AS
AH
CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

DS
DH
BLC
BLCO

- - 10 mS

0 - - nS

50 - - nS

0 - - nS

0 - - nS
10 - - nS
10 - - nS
70 - - nS
70 - - nS

150 - - nS

50 - - nS
10 - - nS

0.22 - 200
300 - -

µS
µS

Publication Release Date: July 1999

- 11 - Revision A12

Data Polling and Toggle Bit Timing Parameters

W29EE011

PARAMETER SYM.

MIN. MAX. MIN. MAX.

OE to Data Polling Output Delay
CE to Data Polling Output Delay
OE to Toggle Bit Output Delay
CE to Toggle Bit Output Delay

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A16-0

CE

OE

V

WE

DQ7-0

IH

High-Z

T
T
T
T

OEP
CEP
OET
CET

W29EE011-90 W29EE011-15

UNIT

- 45 - 70 nS

- 90 - 150 nS

- 45 - 70 nS

- 90 - 150 nS

T

RC

T

CE

T

OE

T

T

OLZ

T

CLZ

Data Valid

T

OH

TAA

Data Valid

T

CHZ

OHZ

High-Z

- 12 -

Timing Waveforms, continued

WE

BLCO

CE

AH

Controlled Write Cycle Timing Diagram

W29EE011

Address A16-0

DQ7-0

WE

T

AS

CE

OE

T

CS

T

OES

T

AH

T

WP

Controlled Write Cycle Timing Diagram

Address A16-0

TAS

CE

T

OES

OE

T

T

CP

Data Valid

T

T

CH

T

OEH

T

WPH

T

DS

T

DH

T

BLCO

T

CPH

T

OEH

T

WC

Internal write starts

T

WC

WE

T

DQ7-0

High Z

DS

Data Valid

T

DH

Internal Write Starts

Publication Release Date: July 1999

- 13 - Revision A12

Timing Waveforms, continued

DATA

Page Write Cycle Timing Diagram

Address A16-0

DQ7-0

CE

W29EE011

T

WC

OE

WE

Polling Timing Diagram

Address A16-0

WE

CE

OE

DQ7-0

T

WPH

TWP

Byte 0 Byte 1

T

CEP

T

OEH

T

OEP

X

TBLC

Byte 2 Byte N-1

X

T

WC

TBLCO

Byte N

Internal Write Start

T

X

X

OES

- 14 -

Timing Waveforms, continued

Toggle Bit Timing Diagram

Address A16-0

WE

CE

W29EE011

OEH T

T

OE

DQ6

WC

T

Page Write Timing Diagram Software Data Protection Mode

Byte/page load
cycle starts

Address A16-0

DQ6

Three-byte sequence for

software data protection mode

2AAA

5555

AA 55

CE

5555

A0

OES

T

WC

OE
WE

T

SW0

WP

T

BLC

T

WPH

SW1

SW2

Byte 0

Byte N-1

Byte N
(last byte)

T

BLCO

Internal write starts

Publication Release Date: July 1999

- 15 - Revision A12

Timing Waveforms, continued

Reset Software Data Protection Timing Diagram

W29EE011

Six-byte sequence for resetting

software data protection mode

Address A16-0

DQ7-0

CE

OE

WE

5555

AA

WP

T

SW0

2AAA

TWPH

SW1

5555

55 80 AA

TBLC

SW2

5555 2AAA

SW3

5 Volt-only Software Chip Erase Timing Diagram

Six-byte code for 5V-only software
chip erase

SW4

55

5555

20

TBLCO

SW5

Internal programming starts

TWC

T

WC

Address A16-0

DQ7-0

CE

OE

WE

5555

AA

WP

T

SW0

T

2AAA

WPH

SW1

55

TBLC

5555

80 AA

SW2

- 16 -

5555 2AAA

55

SW3

SW4

5555

10

BLCO

T

SW5

Internal programming starts

ORDERING INFORMATION

S)

W29EE011

PART NO. ACCESS

W29EE011-90 90 50 100 600 mil DIP 1K
W29EE011-15 150 50 100 600 mil DIP 1K
W29EE011T-90 90 50 100 Type one TSOP 1K
W29EE011T-15 150 50 100 Type one TSOP 1K
W29EE011P-90 90 50 100 32-pin PLCC 1K
W29EE011P-15 150 50 100 32-pin PLCC 1K
W29EE01190B 90 50 100 600 mil DIP 10K
W29EE01115B 150 50 100 600 mil DIP 10K
W29EE011T90B 90 50 100 Type one TSOP 10K
W29EE011T15B 150 50 100 Type one TSOP 10K
W29EE011P90B 90 50 100 32-pin PLCC 10K
W29EE011P15B 150 50 100 32-pin PLCC 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

TIME (n

POWER SUPPLY

CURRENT MAX. (mA)

STANDBY VDD

CURRENT MAX. (µA)

PACKAGE CYCLING

Publication Release Date: July 1999

- 17 - Revision A12

PACKAGE DIMENSIONS

32-pin P-DIP

W29EE011

32

1E

1

2

A

A

L

32-pin PLCC

5

13

14

L

θ

Seating Plane

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.155

0.150

2

A

0.016

0.018

B

0.050 1.27

B1
c

0.010

D

S

B

1

e

1

B

17

16

1A

Base Plane

Seating Plane

E

e

A

a

c

Symbol

H

E

E

1

324

30

29

D

H D

21

GD

0.008

1.650 1.660 41.91 42.16

D

0.6000.590

E

0.545

E

0.550

1

e

1

0.120

0.130

L

0 15

a

0.6500.630 16.00 16.51

e

A

S

Notes:

1.Dimensions D Max. & S include mold flash or
tie bar burrs.

2.Dimension E1 does not include interlead flash.

3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.

4.Dimension B1 does not include dambar
protrusion/intrusion.

5.Controlling dimension: Inches

6.General appearance spec. should be based on
final visual inspection spec.

Dimension in Inches Dimension in mm

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b

b
c
D
E
e

G

G
H
HE
L
y

θ

0.028

1

0.016

0.018

0.008

0.010

0.547

0.550

0.447

0.450

0.050

0.490

0.51

D

0.390

0.410

E

0.585

0.590

D

0.485

0.49

0.075

0.090

°

0

Dimension in mm

0.210 5.33

0.25

0.160

3.81

0.41

0.022

0.0540.048

0.014

0.20

15.24

0.610

14.99

0.555

0.110

2.29 2.54 2.790.090 0.100

0.140

3.05

0.670

0.085

.

0.140

0.50

0.66 0.81

0.41

0.20

13.89

11.35

1.12 1.420.044 0.056

12.45

9.91

14.86

12.32

1.91 2.29

°

10

0

°

2.802.67 2.93

0.71

0.46

0.25

13.97

11.43

1.27

12.9

10.41

14.99

12.45

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

3.94

4.06

0.46

0.56

1.371.22

0.25

0.36

15.49

14.10

13.9713.84

3.30

3.56
150

17.02

2.16

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

Notes:

20

2A

A

e

b

1b

E

G

A1

y

c

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final
visual inspection sepc.

- 18 -

Package Dimensions, continued

32-pin TSOP

M

e

0.10(0.004)

b

θ

L

L

1

W29EE011

H

D

D

c

E

A

A

2

1

A

Y

Dimension in Inches

Symbol

Min. Nom.

__

A

0.002

A

1

0.037

2

A

0.007 0.008

b
c

0.005 0.006

0.720 0.724

D

0.311 0.315

E

0.780 0.787

HD

__

e

0.016 0.020

L

__

L

1

0.000 0.004

Y

θ

Note:
Controlling dimension: Millimeters

Max.

__

0.047

__ __

0.006

0.041

0.039

0.009

0.007

0.728

0.319

0.795

0.020

0.024

0.031

__

1

3 5

__

__

Dimension in mm

Min. Nom.

__

__

0.05

0.95

0.17

0.20 0.23

0.12

0.15 0.17

18.30

18.40 18.50

7.90

8.00 8.10

19.80

20.00

__

0.50

0.40

0.50 0.60

__

0.80

__

0.00
1

3

Max.

1.20

0.15

1.051.00

20.20

__

__

0.10
5

Publication Release Date: July 1999

- 19 - Revision A12

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A9 Feb. 1998 6 Add pause 10 mS

7 Add pause 50 mS
8

1, 17 Add cycing 100 item
A10 Jun. 1998 1, 10, 11, 12, 17 Add 70 nS bining
A11 Aug. 1998 1, 2, 17, 19 Add TSOP package
A12 Jul. 1999 1, 17 Change endurance cycles as 1K/10K

1, 11, 12, 17 Delete 70,120 nS bining

1, 17, 18 Delete SOP package

Correct the time 10 mS to 10 µS

W29EE011

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

- 20 -

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]