Winbond Electronics W25P243AD-6, W25P243AD-5, W25P243AD-4A, W25P243AF-6, W25P243AF-5 Datasheet

W25P243A

LBO

ZZ

64K × 64 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

GENERAL DESCRIPTION

The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium burst mode and linear burst mode. The mode to be

executed is controlled by the the FT pin. A snooze mode can reduce power dissipation.

W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the device is deselected by CE2/CE3 .

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

pin. Pipelining or non-pipelining of the data outputs is controlled by

•

Synchronous operation

•

High-speed access time: 4.5/5/6 nS (max.)

•

Single +3.3V power supply

•

Individual byte write capability

•

3.3V LVTTL compatible I/O

•

Clock-controlled and registered input

•

Asynchronous output enable

BLOCK DIAGRAM

A(15:0)

CLK

CE(3:1)

GW

BWE

BW(8:1)

OE

ADSC

ADSP

ADV LBO

INPUT

REGISTER

CONTROL

REGISTER

LOGIC

•

Pipelined data output capability

•

Supports snooze mode (low-power state)

•

Internal burst counter supports Intel burst

(Interleaved) mode & linear burst mode

•

Support 2T/1T mode

•

Packaged in 128-pin QFP and TQFP

64K X 64

CORE

ARRAY

DATA I/O

REGISTER

I/O(64:1)

Publication Release Date: August 1999

- 1 - Revision A3

PIN CONFIGURATION

S

V D D Q

C

NCN

E 2

W25P243A

/

/ / C E

C

3

/

/ B W 5

/ / O E

/

B

/

C

B

W

G

L

W

E

W

K

4

V

S

D

S

D

B

C

W

E

8

6

7

/

B

V

/ B W 3

/

B

V

B

V

W

S

W

D

2

1

D

V

/

A

S

A

D

S

D

S

Q

V

C

P

VSSQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ VSSQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ VSSQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64

VDDQ

1

2

7

8

6

5

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

3 9

4

424

4

0

3

1

2

3

2

44454

1

2

1

2

1

9

8

7

0

48495

4

6

0

7

1

1 6

5 1

1

2

3

4

5

455

3

2

1

0

1

0

575

0

9

8

7

5

606

9

8

1

5 6

1

102

0

3

6

4

5

6

2

1

3

VDDQ

101

I/O32

100

I/O31

99

I/O30

98

I/O29

97

I/O28

96

I/O27

95

I/O26

94

I/O25

93

I/O24

92

I/O23

91

I/O22

90

VSSQ

89

VDDQ

88

I/O21

87

I/O20

86

I/O19

85

I/O18

84

I/O17

83

I/O16

82

I/O15

81

I/O14

80

I/O13

79

I/O12

78

VSSQ

77

VDDQ

76

I/O11

75

I/O10

74

I/O9

73

I/O8

72

I/O7

71

I/O6

70

I/O5

69

I/O4

68

I/O3

67

I/O2

66

I/O1

65

VSSQ

6 4

A

R

A

V

A

N

/

S

1

C

L

S

5

B

Q

O

V

A

V 1 4

A

S

1

D

1

3

D

S

2

A

1

8

1

9

0

1

A5A4A

A

S

7

6

V

A2A

V

3

D

S

D

S

Z

V

A

1

Z

D

0

D Q

- 2 -

PIN DESCRIPTION

CE1

GW

BWE

BW1

BWE

OE

ADV

ADSC

ADSP

LBO

SYMBOL TYPE DESCRIPTION

W25P243A

A0−A15

I/O1−I/O64

CLK Input, Clock Processor host bus clock

, CE2, CE3

−

BW8

ZZ Input, Asynchronous Snooze pin for low-power state, internal pull low

DDQ

V

I/O power supply

SSQ

V

I/O ground

VDD Power supply

VSS Ground

RSV Reserved pin, don't use these pins

NC No connection

Input, Synchronous Host address I/O, Synchronous Data Inputs/Outputs

Input, Synchronous Chip enables Input, Synchronous Global write Input, Synchronous Byte write enable from cache controller Input, Synchronous Input, Asynchronous Output enable input Input, Synchronous Internal burst address counter advance Input, Synchronous Address status from Chip Set

Input, Synchronous Address status from CPU

Input, Static Lower address burst order

Host bus byte enables used with

Connected to VSS: Device is in linear mode. Connected to VDD or unconnected: Device is in non-

linear mode.

Publication Release Date: August 1999

- 3 - Revision A3

W25P243A

LBO

ADSP

ADSC

ADV

LBO

BWE

GW

FUNCTIONAL DESCRIPTION

The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear

mode, which can be controlled by the and the burst counter is incremented whenever

BURST ADDRESS SEQUENCE

pin. The burst cycles are initiated by

is sampled low.

or

INTEL SYSTEM (

= VDD) LINEAR MODE (

= VSS)

A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] External Start Address 00 01 10 11 00 01 10 11 Second Address 01 00 11 10 01 10 11 00 Third Address 10 11 00 01 10 11 00 01 Fourth Address 11 10 01 00 11 00 01 10

The device supports several types of write mode operations. byte writes. The BE[7:0] signals can be directly connected to the SRAM BW[8:1]. The

and BW[8:1] support individual

signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor.

TRUTH TABLE

CYCLE

Unselected No 1 X X X 0 X X Hi-Z X Unselected No 0 X 1 0 X X X Hi-Z X Unselected No 0 0 X 0 X X X Hi-Z X Unselected No 0 X 1 1 0 X X Hi-Z X Unselected No 0 0 X 1 0 X X Hi-Z X Begin Read External 0 1 0 0 X X X Hi-Z X Begin Read External 0 1 0 1 0 X X Hi-Z Read Continue Read Next X X X 1 1 0 1 Hi-Z Read Continue Read Next X X X 1 1 0 0 D-Out Read Continue Read Next 1 X X X 1 0 1 Hi-Z Read Continue Read Next 1 X X X 1 0 0 D-Out Read Suspend Read Current X X X 1 1 1 1 Hi-Z Read Suspend Read Current X X X 1 1 1 0 D-Out Read Suspend Read Current 1 X X X 1 1 1 Hi-Z Read Suspend Read Current 1 X X X 1 1 0 D-Out Read

ADDRESS

USED

CE1

CE2

CE3 ADSP ADSC ADV

OE

DATA WRITE*

- 4 -

W25P243A

Truth Table, continued

CYCLE

Begin Write Current X X X 1 1 1 X Hi-Z Write Begin Write Current 1 X X X 1 1 X Hi-Z Write Begin Write External 0 1 0 1 0 X X Hi-Z Write Continue Write Next X X X 1 1 0 X Hi-Z Write Continue Write Next 1 X X X 1 0 X Hi-Z Write Suspend Write Current X X X 1 1 1 X Hi-Z Write Suspend Write Current 1 X X X 1 1 X Hi-Z Write

Notes:

1. For a detailed definition of read/write, see the Write Table below.

2. An "X" means don't care, "1" means logic high, and "0" means logic low.

3. TheOE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously with the bus clock except for theOE pin.

4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup to the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings

are met.

ADDRESS

USED

CE1

CE2

CE3 ADSP ADSC ADV

OE

DATA WRITE*

WRITE TABLE

READ/WRITE FUNCTION

Read 1 1 X X X X X X X X Read 1 0 1 1 1 1 1 1 1 1 Write byte 1 I/O1−I/O8 Write byte 2 I/O9−I/O16 Write byte 2, byte 1 1 0 1 1 1 1 1 1 0 0 Write byte 3 I/O17−I/O24 Write byte 3, byte 1 1 0 1 1 1 1 1 0 1 0 Write byte 3, byte 2 1 0 1 1 1 1 1 0 0 1 Write byte 3, byte 2, byte 1 1 0 1 1 1 1 1 0 0 0 Write byte 4, I/O25−I/O32 Write byte 4, byte 1 1 0 1 1 1 1 0 1 1 0 Write byte 4, byte 2 1 0 1 1 1 1 0 1 0 1 Write byte 4, byte 2, byte 1 1 0 1 1 1 1 0 1 0 0 Write byte 4, byte 3 1 0 1 1 1 1 0 0 1 1 Write byte 4, byte 3, byte 1 1 0 1 1 1 1 0 0 1 0 Write byte 4, byte 3, byte 2 1 0 1 1 1 1 0 0 0 1 Write byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 1 0 0 0 0 Write byte 5, I/O33−I/O40 Write byte 5, byte 1 1 0 1 1 1 0 1 1 1 0

GW

BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1

BWE

1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1

1 0 1 1 1 1 1 0 1 1

1 0 1 1 1 1 0 1 1 1

1 0 1 1 1 0 1 1 1 1

Publication Release Date: August 1999

- 5 - Revision A3

W25P243A

Write Table, continued

READ/WRITE FUNCTION

Write byte 5, byte 2 1 0 1 1 1 0 1 1 0 1 Write byte 5, byte 2, byte 1 1 0 1 1 1 0 1 1 0 0 Write byte 5, byte 3 1 0 1 1 1 0 1 0 1 1 Write byte 5, byte 3, byte 1 1 0 1 1 1 0 1 0 1 0 Write byte 5, byte 3, byte 2 1 0 1 1 1 0 1 0 0 1 Write byte 5, byte 3, byte 2, byte 1 1 0 1 1 1 0 1 0 0 0 Write byte 5, byte 4 1 0 1 1 1 0 0 1 1 1 Write byte 5, byte 4, byte 1 1 0 1 1 1 0 0 1 1 0 Write byte 5, byte 4, byte 2 1 0 1 1 1 0 0 1 0 1 Write byte 5, byte 4, byte 2, byte 1 1 0 1 1 1 0 0 1 0 0 Write byte 5, byte 4, byte 3 1 0 1 1 1 0 0 0 1 1 Write byte 5, byte 4, byte 3, byte 1 1 0 1 1 1 0 0 0 1 0 Write byte 5, byte 4, byte 3, byte 2 1 0 1 1 1 0 0 0 0 1 Write byte 5, byte 4, byte 3, byte 2,

byte 1 Write byte 6 1 0 1 1 0 1 1 1 1 1 Write byte 6, byte 1 1 0 1 1 0 1 1 1 1 0 Write byte 6, byte 2 1 0 1 1 0 1 1 1 0 1 Write byte 6, byte 2, byte 1 1 0 1 1 0 1 1 1 0 0

..... and so on ..... ... ... ... ... ... ... ... ... ... ...

Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 2, byte 1

Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3

Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 1

Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 2

Write all bytes 1 0 0 0 0 0 0 0 0 0 Write all bytes 0 x x x x x x x x x

GW

1 0 1 1 1 0 0 0 0 0

1 0 0 0 0 0 0 1 0 0

1 0 0 0 0 0 0 0 1 1

1 0 0 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 0 1

BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1

BWE

Power Down Mode

The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signals except for the ZZ pin. In the unselected mode, on the other hand, all the input signals are monitored.

- 6 -