winbond WMS7120, WMS7121 DATASHEET

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NON-VOLATILE DIGITAL POTENTIOMETERS

PRELIMINARY DATASHEET

WMS7120 / 7121

WITH UP/DOWN (3-WIRE) INTERFACE,

10KOHM, 50KOHM, 100KOHM RESISTANCE

64 TAPS

WITHOUT / WITH OUTPUT BUFFER

Publication Release Date: July 2003

- 1 - Revision 1.0

WMS7120 / 7121

1. GENERAL DESCRIPTION

The WMS7120/7121 is a single channel 64-tap non-volatile linear digital potentiometer available in
10KΩ, 50KΩ and 100KΩ resistance. The device consists of Up/Down serial interface, tap register,
decoder, resistor array, wiper switches, NV memory and control logics.

The WMS7120 device can be configured as a two-terminal variable resistor or a three-terminal voltage
divider without an output buffer, but the WMS7121 device, which has a built-in output buffer, can only
be configured as a three-terminal voltage divider. Both devices can be used in a wide variety of
applications.

The output of the potentiometer is determined by its wiper position, which varies linearly between its
end terminals, R

(

CS , INC and U/ D ) through the Tap Register (TR). In addition, the wiper position can also be

stored into a non-volatile memory location (NVMEM0), which is then automatically recalled upon
power up.

2. FEATURES

and RB/VB. The wiper position, Rw/Vw, is controlled by Up/Down serial interface

A/VA

• Drop-in replacement for many popular parts

• Single linear-taper channel

• 64 taps

• 10K, 50K and 100K end-to-end resistance

• V

• Automatic recall of wiper position when power-on

• Potentiometer control through Up/Down (3-wire) serial interface

• Endurance 100,000 cycles

• Data retention 100 years

• Package options:

• Industrial temperature range: -40° to 85°C

• Single supply operation : 2.7V to 5.5V

to VDD terminal voltages

SS

- 8-pin PDIP, SOIC or MSOP

- 2 -

r

3. BLOCK DIAGRAM

INC

CS

U /D

V

SS

INC

CS

U/D

Up/Down

Serial

Interface

NV Memory

Control

FIGURE 1 – WMS7120 BLOCK DIAGRAM (Rheostat/Divider Mode)

Up/Down

Serial

Interface

V

SS

NV Memory

Control

FIGURE 2 – WMS7121 BLOCK DIAGRAM (Divider Mode)

WMS7120 / 7121

RA/V

A

RW/V

W

Decoder

Tap Register

NV Memory

Tap Register

NVMEM0

Decode

NV Memory

NVMEM0

RB/V

V

DD

V

A

V

W

V

B

V

DD

B

Publication Release Date: July 2003

- 3 - Revision 1.0

WMS7120 / 7121

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 5

6. PIN DESCRIPTION ............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION............................................................................................................ 7

7.1. Rheostat And Divider Operations ........................................................................................... 7

7.1.1. Rheostat Configuration .......................................................................................................... 7

7.1.2. Divider Configuration.............................................................................................................. 7

7.2. Non-Volatile Memory (NVMEM0) ........................................................................................... 7

7.3. Serial Data Interface ................................................................................................................. 8

7.4. Operation Overview .................................................................................................................. 8

8. TIMING DIAGRAMS............................................................................................................................ 9

9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS .................................................. 11

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12

10.1 Test Circuits ............................................................................................................................ 14

11. TYPICAL APPLICATION CIRCUITS............................................................................................... 15

11.1. Layout Considerations.......................................................................................................... 17

12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18

13. ORDERING INFORMATION........................................................................................................... 21

14. VERSION HISTORY ....................................................................................................................... 22

- 4 -

5. PIN CONFIGURATION

WMS7120 / 7121

R

INC

U/D

A/VA

V

R

SS

INC

U/D

A/VA

1

2

3

4

8-MSOP

V

8

DD

CS

7

6

R

B/VB

5

Rw/V

W

1

INC

2

U/D

R

3

A/VA

V

45

SS

8

V

DD

CS

7

R

6

B/VB

Rw/V

W

8-SOIC

1

2

3

V

8

DD

7

CS

6

R

B/VB

45

V

SS

8-PDIP

Rw/V

W

Publication Release Date: July 2003

- 5 - Revision 1.0

6. PIN DESCRIPTION

Pin Name Description

WMS7120 / 7121

TABLE 1 – PIN DESCRIPTION

Chip Select: When

CS

U/D

INC

RA/VA

RB/VB

RW/VW

VSS Ground pin, logic ground reference

VDD Power Supply

Notes: The terminology of high and low terminals above references to the relative

position of the terminal with respect to the wiper moving direction and not the
voltage potential of the terminal.

When
standby mode

Up/Down Control: HIGH state enables the wiper to
move towards the R
implies the wiper moves towards the R

Increment Control: When

transition on

either up or down based on the U/

High terminal of the device

Low terminal of the device

Wiper Terminal: Output of the resistor array is determined

by the

CS is HIGH, the part is deselected and is in

INC will move the wiper one increment

INC , U/ D and CS inputs

CS is LOW, the device is enabled.

/ VA terminal, while LOW state

A

/ VB terminal

B

CS is LOW, a HIGH-LOW

D input

- 6 -

WMS7120 / 7121

7. FUNCTIONAL DESCRIPTION

7.1. RHEOSTAT AND DIVIDER OPERATIONS

The WMS7120 device can operate as either a two-terminal variable resistor or a three-terminal
voltage divider without an output buffer. However, the WMS7121 can only operate in a three-terminal
voltage divider with an output buffer.

7.1.1. Rheostat Configuration

In the rheostat mode, the WMS7120 can be configured as a two-terminal resistive element, where one
terminal is connected to one end of the resistor (R

The moving direction of the wiper depends upon the setting of U/

set to Up, then the wiper moves towards R

wiper moves towards R

. The wiper movement to either direction is controlled by toggling the INC

B

A

signal from HIGH to LOW.

This configuration controls the resistance between the wiper and either end. The wiper resistance can
be adjusted by either changing the wiper position or loading a stored wiper position value from
NVMEM0 upon power up.

or RB) and the other terminal is the wiper (RW).

A

D control signal. When the U/ D is

. Conversely, when the U/ D is set to Down, then the

7.1.2. Divider Configuration

Additionally, the WMS7120 can also be configured as a voltage divider. With an input voltage applied
to one end (usually V
cannot exceed the V
to the wiper position with respect to the voltage difference between V

the wiper depends upon the setting of the U/

wiper moves towards V

. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to

V

B

), the ground is connected to the other end (usually VB). These input voltages

A

level or go below the VSS level. The voltage on the wiper, VW, is proportional

DD

and VB. The moving direction of

A

D control signal. When the U/ D is set to Up, then the

. Conversely, when the U/ D is set to Down, then the wiper moves towards

A

LOW.

Nevertheless, the WMS7121 can only be configured as a voltage divider and operate similarly as the
WMS7120 device. The only difference is WMS7121 has an output buffer, but WMS7120 doesn’t have.

Besides, the resistance cannot be directly measured in this configuration.

7.2. NON-VOLATILE MEMORY (NVMEM0)

The WMS7120/7121 has one NVMEM0 location available for storing the current wiper position via the
Up/Down serial interface. This stored value is automatically recalled and loaded into the tap register
upon power up.

Publication Release Date: July 2003

- 7 - Revision 1.0