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W78E58B
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winbond W78E58B, W78E058B Technical data

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W78E58B/W78E058B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................... 3
2. FEATURES....................................................................................................................................... 3
3. PIN CONFIGURATIONS .................................................................................................................. 4
4. PIN DESCRIPTION .......................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION ......................................................................................................... 6
6. SECURITY...................................................................................................................................... 19
7. ELECTRICAL CHARACTERISTICS............................................................................................... 21
7.3.1 Clock Input Waveform...........................................................................................................23
7.3.2 Program Fetch Cycle ............................................................................................................23
7.3.3 Data Read Cycle...................................................................................................................24
7.3.4 Data Write Cycle...................................................................................................................24
7.3.5 Port Access Cycle.................................................................................................................24
Publication Release Date: December 4, 2006
- 1 - Revision A8
W78E58B/W78E058B
TIMING WAVEFORMS................................................................................................................... 25
8.
9. TYPICAL APPLICATION CIRCUITS .............................................................................................. 27
10. PACKAGE DIMENSIONS............................................................................................................... 29
11. APPLICATION NOTES................................................................................................................... 31
12. REVISION HISTORY...................................................................................................................... 36
- 2 -
W78E58B/W78E058B
1. GENERAL DESCRIPTION
The W78E058B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E058B is fully compatible with the standard 8052. The W78E058B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E058B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.
The W78E058B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
2. FEATURES
y Fully static design 8-bit CMOS microcontroller
y 32K bytes of in-system programmable Flash EPROM for Application Program (APROM)
y 4K bytes of auxiliary ROM for Loader Program (LDROM)
y 512 bytes of on-chip RAM (including 256 bytes of AUX-RAM, software selectable)
y 64K bytes program memory address space and 64K bytes data memory address space
y Four 8-bit bi-directional ports
y One 4-bit multipurpose programmable port
y Three 16-bit timer/counters
y One full duplex serial port
y Eight-sources, two-level interrupt capability
y Built-in power management
y Code protection
y Packaged in
− Lead Free (RoHS) DIP 40: W78E058B40DL
− Lead Free (RoHS) PLCC 44: W78E058B40PL
− Lead Free (RoHS) PQFP 44: W78E058B40FL
Publication Release Date: December 4, 2006
- 3 - Revision A8
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
W78E58B/W78E058B
VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
P0.0, AD0
38
P0.1, AD1
P0.2, AD2
37
P0.3, AD3
36
35
P0.4, AD4
34
P0.5, AD5
33
P0.6, AD6
32
P0.7, AD7
31
EA ALE
30
29
PSEN
P2.7, A15
28
P2.6, A14
27
P2.5, A13
26
P2.4, A12
25
P2.3, A11
24
P2.2, A10
23
P2.1, A9
22
P2.0, A8
21
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
44-Pin PLCC
P
P
P
1
1
1
.
.
.
3
4
2
6543
7
8
9
10
11
12
13
14
15
16 17
X
P
P
T
3
3
A
.
.
L
7
6
,
,
2
/
/
R
W
D
R
/
T
I
2
N
E
T
T
X
2
3
,
,
,
P
P
P
1
1
4
.
.
.
1
0
2
2 1 44 43 42
V
X
P
S
T
4
A
S
.
L
0
1
44-Pin QFP
/
T
I
2
N
T
E
A
A
A
A
D
D
D
D
3
1
2
0
,
,
,
,
P
P
P
P
0
0
V
0
0
.
.
.
D
.
3
1
D
2
0
40
41
39
P0.4, AD4
38
P0.5, AD5
37
P0.6, AD6
36
P0.7, AD7
35
EA
34
P4.1
33
ALE
32
PSEN
31
P2.7, A15
30
P2.6, A14
29
P2.5, A13
2827262524232221201918
P
P
P
P
P
2
2
2
2
2
.
.
.
.
.
3
4
1
0
2
,
,
,
,
,
A
A
A
A
A 8
1
1
9
1
1
2
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
P
1
1
.
.
3
4
43 42 41
44
1
2
3
4
5
6
7
8
9
10
11
12
P
P
3
3
.
.
7
6
,
,
/
/
R
W
D
R
2
X
,
,
P
P
P
1
1
1
.
.
.
0
1
2
40 39 38 37 36 35
X
V
X
S
T
T
S
A
A
L
L
1
2
T 3 , P
V
4
D
.
D
2
P
P
2
4
.
.
0
0
, A
8
A
A
A
A
D
D
D
D
3
2
1
0
,
,
,
,
P
P
P
P
0
0
0
0
.
.
.
.
3
2
1
0
34
33
P0.4, AD4
32
P0.5, AD5
31
P0.6, AD6
30
P0.7, AD7
29
EA
28
P4.1
27
ALE
26
PSEN
25
P2.7, A15
24
P2.6, A14
23
P2.5, A13
22212019181716151413
P
P
P
P
2
2
2
2
.
.
.
.
4
3
1
2
,
,
,
,
A
A
A
A
1
1
9
1
1
2
0
- 4 -
W78E58B/W78E058B
A
f
A
A
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus i
E
I
E
the
pin is high.
PROGRAM STORE ENABLE:
PSEN
ALE O H
RST I L
XTAL1 I
XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: Ground potential.
VDD I POWER SUPPLY: Supply voltage for operation.
P0.0 − P0.7
P1.0 − P1.7
P2.0 − P2.7
P3.0 − P3.7
P4.0 − P4.3
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
O H
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
Port 0 address/data bus. When internal ROM access is performed, no strobe signal outputs originate from this pin.
ADDRESS L separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
TCH ENABLE: ALE is used to enable the address latch that
PSEN enables the external ROM data in the
PSEN
Publication Release Date: December 4, 2006
- 5 - Revision A8
W78E58B/W78E058B
5. FUNCTIONAL DESCRIPTION
The W78E058B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.
5.1 RAM
The internal data RAM in the W78E058B is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
y RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
y RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
y AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory
with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing
from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2,
RD .
WR and
Example,
CHPENR REG F6H
CHPCON REG BFH
MOV CHPENR, #87H
MOV CHPENR, #59H
ORL CHPCON, #00010000B ; enable AUX-RAM
MOV CHPENR, #00H
MOV R0, #12H
MOV A, #34H
MOVX @R0, A ; Write 34h data to 12h address.
5.2 Timers 0, 1 and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
- 6 -
W78E58B/W78E058B
5.3 Clock
The W78E058B is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E058B relatively insensitive to duty cycle variations in the clock.
5.4 Crystal Oscillator
The W78E058B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground.
5.5 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
5.6 Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts
INT0 to INT1 when enabled and set to level triggered.
5.7 Reduce EMI Emission
The W78E058B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain.
5.8 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E058B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
Publication Release Date: December 4, 2006
- 7 - Revision A8
W78E58B/W78E058B
W78E058B Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
Notes:
1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
+B
00000000
+ACC
00000000
+P4
xxxx1111
+PSW
00000000
+T2CON
00000000
XICON
00000000
+IP
00000000
+P3
00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
RCAP2L
00000000
P4CONA
00000000
RCAP2H
00000000
P4CONB
00000000
TL2
00000000
SFRAL
00000000
00000000
SFRAH
00000000
A7
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
P43AL
00000000
P42AL
00000000
P41AL
00000000
TH0
00000000
P40AL
00000000
00000000
00000000
00000000
00000000
00000000
TH2
P43AH
P42AH
P41AH
TH1
P40AH
CHPENR
00000000
SFRFD
00000000
SFRCN
00000000
CHPCON
0xx00000
P2ECON 0000xx00
97
8F
AF
PCON
00110000
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
9F
87
- 8 -
W78E58B/W78E058B
5.9 Port 4
Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0 − P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt
INT3 and NT2I if enabled.
Mode 1: P4.0 − P4.3 are read strobe signals that are synchronized with addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0 − P4.3 are write strobe signals that are synchronized with addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0 − P4.3 are read/write strobe signals that are synchronized with specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode.
RD signal at specified
WR signal at specified
RD or WR signal at
5.10 INT2 / NT3I
Two additional external interrupts, interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB ( "SETB 0C2H" sets the EX2 bit of XICON.
INT2
and INT3 , whose functions are similar to those of external
CLR ) bit" instruction. For example,
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Publication Release Date: December 4, 2006
- 9 - Revision A8
Eight-source interrupt information
A
W78E58B/W78E058B
INTERRUPT
SOURCE
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
Timer/Counter 2 2BH 5 IE.5 -
External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
P4CONB (C3H)
BIT NAME FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
7, 6
P43FUN1
P43FUN0
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0.
5, 4
3, 2
1, 0
P43CMP1
P43CMP0
P42FUN1
P42FUN0
P42CMP1
P42CMP0
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register P43AH, P43AL.
01: Compare the 15 high bits (A15 register P43AH, P43AL.
10: Compare the 14 high bits (A15 register P43AH, P43AL.
11: Compare the 8 high bits (A15 register P43AH, P43AL.
The P4.2 function control bits which are the similar definition as P43FUN1, P43FUN0.
The P4.2 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.
- 10 -
− A1) of address bus with the base address
−
2) of address bus with the base address
− A8) of address bus with the base address
W78E58B/W78E058B
P4CONA (C2H)
BIT NAME FUNCTION
7, 6
P41FUN1
P41FUN0
P41CMP1
5, 4
P41CMP0
P40FUN1
3, 2
P40FUN0
P40CMP1
1, 0
P40CMP0
The P4.1 function control bits which are the similar definition as P43FUN1, P43FUN0.
The P4.1 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.
The P4.0 function control bits which are the similar definition as P43FUN1, P43FUN0.
The P4.0 address comparator length control bits which are the similar definition as P43CMP1, P43CMP0.
P2ECON (AEH)
BIT NAME FUNCTION
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal.
7 P43CSINV
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal.
0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1 - 0
0 - 0
5.11 Port 4 Base Address Registers
P40AH, P40AL
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address.
P41AH, P41AL
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address.
Publication Release Date: December 4, 2006
- 11 - Revision A8
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