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W78E51C
Technical data
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winbond W78E51C Technical data

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W78E51C Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS............................................................................................................. 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION.................................................................................................... 7
6.1 New Defined Peripheral.................................................................................................. 7
6.2 Reduce EMI Emission .................................................................................................... 8
6.3 Watchdog Timer ............................................................................................................. 9
6.4 Clock ............................................................................................................................. 10
6.5 Power Management...................................................................................................... 10
6.6 Reset............................................................................................................................. 11
7. SECURITY BITS ....................................................................................................................... 11
7.1 Lock Bit ......................................................................................................................... 11
7.2 MOVC Inhibit................................................................................................................. 12
7.3 Encryption ..................................................................................................................... 12
8. ELECREICAL CHARACTERISTICS......................................................................................... 12
8.1 Absolute Maximum Ratings .......................................................................................... 12
8.2 D.C. Characteristics...................................................................................................... 12
8.3 A.C. Characteristics ...................................................................................................... 14
9. TIMING WAVEFORMS ............................................................................................................. 17
9.1 Program Fetch Cycle .................................................................................................... 17
9.2 Data Read Cycle........................................................................................................... 17
9.3 Data Write Cycle........................................................................................................... 18
9.4 Port Access Cycle......................................................................................................... 18
Publication Release Date: April 20, 2005
- 1 - Revision A2
W78E51C
10.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 19
10.1 Expanded External Program Memory and Crystal ....................................................... 19
10.2 Expanded External Data Memory and Oscillator.......................................................... 20
11. PACKAGE DIMENSIONS ......................................................................................................... 21
11.1 40-pin DIP ..................................................................................................................... 21
11.2 44-pin PLCC ................................................................................................................. 21
11.3 44-pin PQFP ................................................................................................................. 22
12. REVISION HISTORY ................................................................................................................23
- 2 -
W78E51C
1. GENERAL DESCRIPTION
The W78E51C is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E51C is fully compatible with the standard 8051. The W78E51C contains an 4K bytes Flash EPROM; a 128 bytes RAM; four 8-bit bi-directional and bit­addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by seven sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78E51C allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.
The W78E51C microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
2. FEATURES
• Fully static design 8-bit CMOS microcontroller
• Wide supply voltage of 4.5V to 5.5V
• 128 bytes of on-chip scratchpad RAM
• 4 KB On-chip Flash EPROM
• 64 KB program memory address space
• 64 KB data memory address space
• Four 8-bit bi-directional ports
• One extra 4-bit bit-addressable I/O port, additional
(available on 44-pin PLCC/QFP package)
• Two 16-bit timer/counters
• One full duplex serial port(UART)
• Watchdog Timer
Seven sources, two-level interrupt capability
•
• EMI reduction mode
Built-in power management
•
• Code protection mechanism
Packages:
•
− DIP 40: W78E51C-40
− PLCC 44: W78E51CP-40
− PQFP 44: W78E51CF-40
- 3 - Revision A2
INT2 / INT3
Publication Release Date: April 20, 2005
3. PIN CONFIGURATIONS
W78E51C
- 4 -
W78E51C
A
4. PIN DESCRIPTION
SYMBOL DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
E
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
P3.0−P3.7
P4.0−P4.3
data will not be presented on the bus if on-chip ROM area.
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is performed, no
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND
POWER SUPPLY
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 are open­drain and should connect to pull up resistors if necessary while in programming.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output
INT0
INT1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input
WR
RD (P3.7) : External Data Memory Read Strobe
PORT 4:
function pins. It can be used as general I/O port or external interrupt input sources (
INT2
: Ground potential
(P3.2) : External Interrupt 0
(P3.3) : External Interrupt 1
(P3.6) : External Data Memory Write Strobe
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
).
/
INT3
strobe signal outputs from this pin.
PSEN
: Supply voltage for operation.
pin is high and the program counter is within
EA
Publication Release Date: April 20, 2005
- 5 - Revision A2
5. BLOCK DIAGRAM
W78E51C
P1.0
~
P1.7
P3.0 ~ P3.7
P4.0 ~ P4.3
INT2
INT3
Port
1
Port
3
Port
4
Port 1 Latch
Interrupt
Timer
Timer
UART
Port 3
Latch
Port 4 Latch
ACC
T1
Oscillator
PSW
Instruction
Decoder
&
Sequencer
Bus & Clock
Controller
ALU
SFR RAM
RAM & SFR
Watchdog
Reset Block
0
1
T2
Address
128 bytes
ROM
Timer
B
Stack
Pointer
Power control
Port 0 Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
Port 2
Latch
Port
Port
2
P0.0
0
~ P0.7
P2.0 ~ P2.7
XTAL1
XTAL2
PSENALE
RST
Vcc
Vss
- 6 -
W78E51C
6. FUNCTIONAL DESCRIPTION
The W78E51C architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.
6.1 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
/ INT3
INT2
Two additional external interrupts, interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
INT2
and
INT3 , whose functions are similar to those of external
PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information
INTERRUPT SOURCE
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
External Interrupt 2 33H 5 XICON.2 XICON.0
External Interrupt 3 3BH 6 (lowest) XICON.6 XICON.3
VECTOR
ADDRESS
POLLING SEQUENCE
WITHIN PRIORITY
LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT TYPE
EDGE/LEVEL
Publication Release Date: April 20, 2005
- 7 - Revision A2
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