winbond W78E516B User Manual

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W78E516B

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78E516B is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78E516B is fully compatible with the standard 8052.
The W78E516B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM
which allows the contents of the 64KB main MTP-ROM to be updated by the loader program located
at the 4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit­addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These
peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming
and verification, the MTP-ROM inside the W78E516B allows the program memory to be programmed
and read electronically. Once the code is confirmed, the user can protect the code for security.

The W78E516B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

• Fully static design 8-bit CMOS microcontroller up to 40 MHz.

• 64K bytes of in-system programmable MTP-ROM for Application Program (APROM).

• 4K bytes of auxiliary MTP-ROM for Loader Program (LDROM).

• 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)

• 64K bytes program memory address space and 64K bytes data memory address space.

• Four 8-bit bi-directional ports.

• One 4-bit multipurpose programmable port.

• Three 16-bit timer/counters

• One full duplex serial port

• Six-sources, two-level interrupt capability

• Built-in power management

• Code protection

• Packaged in

− DIP 40: W78E516B-24/40

− PLCC 44: W78E516BP-24/40

Publication Release Date: February 2000

- 1 - Revision A3

PIN CONFIGURATIONS

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

40-pin DIP (W78E516B)

T2, P1.0

T2EX, P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
RXD, P3.0
TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VDD1

P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE

PSEN
P2.7, A15

P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8

W78E516B

44-pin PLCC (W78E516BP)

T
2
E
X
,

P

P

P

P

1

1

1

1

.

.

.

.

2

1

3

4

6 5 4 3

7

P1.5

8

P1.6

9

P1.7

10

RST

P4.3

11
12
13
14
15
16

17

X

X

P

P

T

T

3

3

A

A

.

.

L

L

7

6

1

2

,

,

/

/

R

W

D

R

RXD, P3.0

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

A

T

D

2

0

,

,

P

P

P

1

V

0

4

.

D

.

.

0

D

0

2

2 1 44 43 42

V

P

P

P

S

2

2

4

S

.

.

.

1

0

0

,

,

A

A

9

8

A

A

A

D

D

D

3

2

1

,

,

,

P

P

P

0

0

0

.

.

.

3

1

2

40

41

39
38
37

36
35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

P

P

2

2

2

.

.

.

3

4

2

,

,

,

A

A

A

1

1

1

1

2

0

- 2 -

PIN DESCRIPTION

EA

W78E516B

SYMBOL TYPE

P0.0−P0.7
P1.0−P1.7
P2.0−P2.7

P3.0−P3.7
P4.0−P4.3

PSEN

ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

RST I L RESET: A high on this pin for two machine cycles while the oscillator is

XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an

XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

VSS I GROUND: ground potential.

VDD I POWER SUPPLY: Supply voltage for operation.

I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the

external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.

O H

I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no

strobe signal outputs originate from this pin.

separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.

running resets the device.

external clock.

provides the upper address bits for accesses to external memory.

DESCRIPTIONS

PSEN

* Note:

PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,

Example:
P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.
MOV A, P4 ; Read P4 status to Accumulator.
SETB P4.0 ; Set bit P4.0
CLR P4.1 ; Clear bit P4.1

- 3 - Revision A3

I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

TYPE

Publication Release Date: February 2000

BLOCK DIAGRAM

W78E516B

P1.0

P1.7

P3.0

P3.7

P4.0
P4.3

Port

1

Port

Port

Port 1

Latch

ACC

Interrupt

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4

Latch

XTAL1

Oscillator

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALE

ALU

Reset Block

PSEN

T2T1

SFR RAM

Address

512 bytes

RAM & SFR

B

Stack

Pointer

Power control

VssVCCRSTXTAL2

Port 0

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

64KB

MTP-ROM

4KB

MTP-ROM

Port 2

Latch

Port
0

Port
2

P0.0

P0.7

P2.0

P2.7

FUNCTIONAL DESCRIPTION

The W78E516B architecture consists of a core controller surrounded by various registers, four
general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM,
three timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be
switched to port2. The processor supports 111 different opcodes and references both a 64K program
address space and a 64K data storage space.

RAM

The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.

•

RAM 0H−127H can be addressed directly and indirectly as the same as in 8051. Address pointers

are R0 and R1 of the selected register bank.

•

RAM 128H−255H can only be addressed indirectly as the same as in 8051. Address pointers are

R0, R1 of the selected registers bank.

- 4 -

W78E516B

INT1

•

AUX-RAM 0H−255H is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 255H will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal

program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer
0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer
1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled
by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter
or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.

Clock

The W78E516B is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E516B relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78E516B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must
be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from
each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC
bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a

hardware reset or external interrupts INT0 to

when enabled and set to level triggered.

Reduce EMI Emission

The W78E516B allows user to diminish the gain of on-chip oscillator amplifier by using programmer

Publication Release Date: February 2000

- 5 - Revision A3

W78E516B

to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect
the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1, C2
may need some adjustment while running at lower gain.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E516B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

W78E516B Special Function Registers (SFRs) and Reset Values

F8

F0 +B

00000000

E8

E0 +ACC

00000000

D8

D0 +PSW

C8 +T2CON

C0 XICON

B8 +IP

B0 +P3

A8 +IE

A0 +P2

98 +SCON

90 +P1

88 +TCON

80 +P0

Notes:

1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.

2. The text of SFR with bold type characters are extension function registers.

+P4

xxxx1111

00000000

00000000

00000000

00000000

00000000

00000000

11111111

00000000

11111111

00000000

11111111

E7

DF

D7

RCAP2L

00000000

A7

SBUF

xxxxxxxx

TMOD

00000000

SP

00000111

SFRAL

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

00000000

TH0

00000000

TH2

00000000

SFRAH

00000000

TH1

00000000

CHPENR

00000000

CF

SFRFD

00000000

B7

97

8F

PCON

00000000
CHPCON
0xx00000

00110000

F7

EF

SFRCN

AF

FF

C7

BF

9F

87

- 6 -

W78E516B

Port 4 (D8H)

BIT NAME FUNCTION

7 - Reserve
6 - Reserve
5 - Reserve
4 - Reserve
3 P43 Port 4 Data bit which outputs to pin P4.3.
2 P42 Port 4 Data bit. which outputs to pin P4.2.
1 P41 Port 4 Data bit. which outputs to pin P4.1.
0 P40 Port 4 Data bit which outputs to pin P4.0.

In-System Programming (ISP) Mode

The W78E516B equips one 64K byte of main MTP-ROM bank for application program (called
APROM) and one 4K byte of auxiliary MTP-ROM bank for loader program (called LDROM). In the
normal operation, the microcontroller executes the code in the APROM. If the content of APROM
needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode
by setting the CHPCON register.

specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON
write attribute. Writing CHPENR register with the values except 87H and 59H will close
CHPCON register write attribute.

including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the
bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode.
Because device needs proper time to complete the ISP operations before awaken from idle mode,
software may use timer interrupt to control the duration for device wake-up from idle mode. To
perform ISP operation for revising contents of APROM, software located at APROM setting the
CHPCON register then enter idle mode, after awaken from idle mode the device executes the
corresponding interrupt service routine in LDROM. Because the device will clear the program counter
while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service
routine will jump to 00H at LDROM area. The device offers a software reset for switching back to
APROM while the content of APROM has been updated completely.

1 and 7 to logic-1 will result a software reset to reset the CPU

external reset. This in-system programming feature makes the job easy and efficient in which the
application needs to update firmware frequently. In some applications, the in-system programming
feature make it possible to easily update the system firmware without opening the chassis.

The CHPCON is read-only by default, software must write two

The W78E516B achieves all in-system programming operations

Setting CHPCON register bit 0,

. The software reset serves as a

SFRAH, SFRAL:

SFRFD:
SFRCN:

- 7 - Revision A3

The programming data for on-chip MTP-ROM in programming mode.

The control byte of on-chip MTP-ROM programming mode.

The objective address of on-chip MTP-ROM in the in-system programming mode.
SFRFAH contains the high-order byte of address, SFRFAL contains the low-order
byte of address.

Publication Release Date: February 2000

W78E516B

0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is

SFRCN (C7)

BIT NAME FUNCTION

7 - Reserve.
6 WFWIN On-chip MTP-ROM bank select for in-system programming.

= 0: 64K bytes MTP-ROM bank is selected as destination for re-programming.

= 1: 4K bytes MTP-ROM bank is selected as destination for re-programming.
5 OEN MTP-ROM output enable.
4 CEN MTP-ROM chip enable.

3, 2, 1, 0 CTRL[3:0] The flash control signals

MODE WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD

Erase 64KB APROM 0 0010 1 0 X X
Program 64KB APROM 0 0001 1 0 Address in Data in
Read 64KB APROM 0 0000 0 0 Address in Data out
Erase 4KB LDROM 1 0010 1 0 X X
Program 4KB LDROM 1 0001 1 0 Address in Data in
Read 4KB LDROM 1 0000 0 0 Address in Data out

In-System Programming Control Register (CHPCON)

CHPCON (BFH)

BIT NAME FUNCTION

7 SWRESET

(F04KMODE)

6 - Reserve.
5 - Reserve.

ENAUXRAM

4

3 0 Must set to 0.
2 0 Must set to 0.
1 FBOOTSL The Program Location Select.

When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation. To
read this bit in logic-1 can determine that the F04KBOOT mode is running.

1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM

destination for re-programming.
1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is

destination for re-programming.

- 8 -