winbond W78E354 User Manual

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W78E354

MONITOR MICROCONTROLLER

GENERAL DESCRIPTION

The W78E354 is a stand-alone high-performance microcontroller ASIC specially designed for use in
monitor control applications. Using the Winbond 0.8µ DPDM process, the W78E354 integrates an
embedded 8031 microcontroller core, 16K bytes of Flash cell, 512 bytes of RAM and a number of
dedicated hardware functions. These hardware functions include a 6-bit A/D converter, two/fourteen
12/8-bit PWM static DACs, one/three 12/8-bit PWM dynamic DACs, a sync processor, one DDC port,
a watchdog timer and other custom glue logic. Additional special function registers are incorporated to
control the on-chip peripheral hardware.

The chip is used to control the interface signals of other devices in the monitor and to process the
video sync signals. Because of high integration and the incorporation of Flash cell for program
memory, the device offers the user the competitive advantages of low cost and reduced development
time.

FEATURES

• 80C31 MCU core included

• 16K bytes Flash OTP memory for program storage

• Total 512 bytes of on-chip data RAM:

256 bytes accessed as in the 80C32, 256 bytes accessed as external data memory via "MOVX
@Ri".

• One SPI/RS232 port (a serial port of 8051 standard)

• One external interrupt input

• Two timers/counters

• PWM DACs:

− Two 12-bit PWM/BRM Static DACs

− Fourteen 8-bit PWM Static DACs

− One 12-bit PWM/BRM Dynamic DAC

− Three 8-bit PWM Dynamic DACs

• One 6-bit ADC with 4 multiplexed analog inputs

• Sync Processor:

− Horizontal & Vertical Polarity Detector

− Sync Separator for composite sync

− Horizontal & Vertical Frequency Counter

− Programmable dummy frequency generator

− Programmable H-clamp pulse output

− SOA output (hardware H frequency change detection)

• One DDC port (master/slave mode I

• One 8-bit Auto-reload timer for software time base

2

C with two slave address reg., support DC1/DDC2B/DDC2B+)

Publication Release Date: April 1997

- 1 - Revision A1

• Watchdog Timer

132149876

5

3

0

5

1

6

5

6

7

8

9

7

D

4

3

2

4

3

1

• Two 15 mA output pins for driving LEDs

• Power down reset

• Clock: DC to 20 MHz

• Packaged in 68-pin PLCC, 48-pin DIP and 40-pin DIP

PIN CONFIGURATIONS

P

P

2

2

.

.

5

4

/

/

S

S

D

D

A

A

C

A

C

1

1

S

S

S

S

S

D

P

D

P

D

D

D

A

A

A

C

C

C

4

A

4

C

V

.

C

.

D

W78E354

S

S

S

P

D

3

A

A

.

C

S

D

D

P

P

D

A

4

3

A

C

C

.

.

C

SDAC10
SDAC11

P2.6/SDAC12

P2.7/SDAC13

OSCOUT

OSCIN

VSS

P2.0

P2.1

SDAC12

SDAC13

P2.2

P2.3/STP

P3.4/T0

P3.5/T1

HIN

VIN

676866656463626

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44

272829303132333435363738394041424

V

H

B

O

O

S

U

U

D

T

T

A

C
0

P

B

3

S

.

D

0

A

/

C

R

1

X
D

W78E354P

(PLCC-68)

V

P

V

R

S

3
1
T

X
D

S

E

S

.

S

S

A

E

/

T

A

V

A

A
D
C
0

A

A

D

D

D

A

C

C

C

1

2

3

/

/

P

P

1

1

.

.

7

6

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

P

P

T

3

3

e

.

.

s

2

6

t

/

C

I

L

N

K

T
0

60

SDAC0
BDDAC
DDAC2
DDAC1
DDAC0
P4.3
VPP
P4.2
VDD
P1.5/SOA
P1.4/HCLAMP
P1.3/DSDA
P1.2/DSCL
P1.1
P1.0

P4.1
P4.0

- 2 -

Pin Cinfigurations, continued

SDAC5
SDAC6

SDAC7
P2.4/SDAC10
P2.5/SDAC11
P2.6/SDAC12
P2.7/SDAC13

OSCOUT

OSCIN

VSS

P2.0
P2.1
P2.2

P2.3/STP

P3.4/T0

P3.5/T1

HIN

VIN
HOUT
VOUT

BSDAC0
P3.0/RXD
P3.1/TXD

RESET

W78E354

V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

DD

SDAC4
SDAC3
SDAC2
SDAC1
P3.3
SDAC0
BDDAC
DDAC2
DDAC1
DDAC0
V

PP

P1.5/SOA
P1.4/HCLAMP
P1.3/DSDA
P1.2/DSCL
P1.1
P1.0
P3.6
P3.2/INT0
TestCLK
VAA
ADC0
VSSA

SDAC5
SDAC6

SDAC7
P2.4/SDAC10
P2.5/SDAC11
P2.6/SDAC12
P2.7/SDAC13

OSCOUT

OSCIN

V
P2.0
P2.1
P2.2

P2.3/STP

HIN

VIN

HOUT

VOUT

BSDAC0

P3.0/RXD

DD

V

1
2
3
4
5
6
7
8
9
10

SS

11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

SDAC4
SDAC3
SDAC2
SDAC1
SDAC0
BDDAC
DDAC0
V

PP

P1.5/SOA
P1.4/HCLAMP
P1.3/DSDA
P1.2/DSCL
P1.1
P1.0
P3.2/INT0
TestCLK
ADC0

RESET
P3.1/TXD

PIN DESCRIPTION

PIN NO.

35
36
37
38
39

1
2
3

-

-

-

-

-

-

NAME

SDAC0
SDAC1
SDAC2
SDAC3
SDAC4
SDAC5
SDAC6
SDAC7

SDAC8

SDAC9
SDAC10
SDAC11
SDAC12
SDAC13

68P 64P 48P 40P

60

57

42

62

59

44

63

60

45

65

61

46

66

62

47

3

1

1

4

2

2

5

3

3

6

4

-

7

5

-

10

8

-

11

9

-

19

17

-

20

18

-

W78E354E

(DIP-48)

PIN

I/O

TYPE

I/O

O/P

TEST

NAME

A0
A1
A2
A3
A4
A5
A6
A7

-

-

-

-

-

-

W78E354
(DIP-40)

FUNCTIONAL DESCRIPTION

8-bit PWM static DAC output.
Sink/Source current 4 mA/-4 mA.
With slew rate control and output delay:

1. Delay about 5 nS:
SDAC2, 5, 8, 11.

2. Delay about 10 nS:
SDAC0, 3, 6, 9, 12.

3. Without delay: the others.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
SDAC0−7: A0−A7 inputs.
* In the functional test mode

(CPU executes out of ext. program memory):
SDAC0−7: A0−A7 outputs.

Publication Release Date: April 1997

- 3 - Revision A1

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

2930272821-19-BSDAC0

56

53

38

33

57

54

39

58

55

40

59 56 41 34 BDDAC I/O A10 12-bit PWM/BRM dynamic DAC output.

-

-

PIN

NAME

BSDAC1

DDAC0

DDAC1

DDAC2

I/O

TYPE

I/O

O/P

I/O

O/P

TEST

NAME

A8

-

A9

-

-

FUNCTIONAL DESCRIPTION

12-bit PWM/BRM static DAC output.
Sink/Source current 8 mA/-8 mA.
With slew rate control and output delay:

1. Delay about 5ns: BSDAC1

2. Without delay: BSDAC0.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
BSDAC0: A8 input.
* In the functional test mode
(CPU executes out of ext. program memory):
BSDAC0: A8 output.

8-bit PWM dynamic DAC output.
Sink/Source current 8 mA/-8 mA.
With slew rate control and output delay:

1. Delay about 5 nS: DDAC1.

2. Delay about 10 nS: DDAC2.

3. Without delay: DDAC0.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
DDAC0: A9 input.
* In the functional test mode
(CPU executes out of ext. program memory):
DDAC0: A9 output.

Sink/Source current 8mA/-8mA.
With slew rate control.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
BDDAC: A10 input.
* In the functional test mode
(CPU executes out of ext. program memory):
BDDAC: A10 output.

- 4 -

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

36

34

26

37

35

-

39

37

-

40

38

-

46474445313226

48494647333428

23

27

29

PIN

NAME

ADC0

-

ADC1

-

ADC2
(P1.6)

­ADC3
(P1.7)

P1.0
P1.1

P1.2

(DSCL)

P1.3

(DSDA)

I/O

TYPE

I/P -

I/O A13

I/O A13CTRL

TEST

NAME

A14

A14CTRL

FUNCTIONAL DESCRIPTION

Analog signal input channel to ADC.

-

-

-

Alternate function:
ADC2: P1.6 input (input only).
ADC3: P1.7 input (input only).

General purpose I/O.
Open-drain, Sink current 2mA.
Schmitt trigger I/P.
No PMOS ESD cell.

VIH = 3.0V (min), VIL = 1.5V (max)

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
P1.0 and P1.1: A13 and A14 inputs.
* In the functional test mode
(CPU executes out of ext. program memory):
P1.0 and P1.1: do not output A13 and A14, but function in

their normal operational state.

General purpose I/O.
Open-drain, Sink current 6mA.
Schmitt trigger I/P.
No PMOS ESD cell.

VIH = 3.0V (min), VIL = 1.5V (max)

Alternate function:
P1.2: DDC port serial clock DSCL.
P1.3: DDC port serial data DSDA.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
P1.2: A13CTRL input.
P1.3: A14CTRL input.

Publication Release Date: April 1997

- 5 - Revision A1

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

50 48 35 30 P1.4

51 49 36 31 P1.5

17181516111211

12

PIN

NAME

(HCLAMP)

(SOA)

P2.0
P2.1

I/O

TYPE

I/O A9CTRL General purpose I/O.

I/O A11 General purpose O/P.

I/O D0

TEST

NAME

D1

FUNCTIONAL DESCRIPTION

Sink/Source current 4 mA/-100 µA.
Alternate function:
P1.4: HCLAMP (H-clamp pulse) output.

While outputing special function, P1.4's Sink/Source
current is 4 mA/-4 mA.

--------------------------------------------------------­* In the Flash/RAM-test mode

(when the chip is in reset state):
P1.4: A9CTRL input.

Sink/Source current 4 mA/-4 mA.
Alternate function:
P1.5: SOA (Safe Operation Area) outpout.

--------------------------------------------------------­* In the Flash/RAM-test mode

(when the chip is in reset state):
P1.5: A11 input.
* In the functional test mode
(CPU executes out of ext. program memory):
P1.5: doesn't output A11, but functions as

its normal operation.

General purpose I/O.
Sink/Source current 15mA/-100µA.
With slew rate control .

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
P2.0−P2.1: D0−D1 data inputs/outputs.
* In the functional test mode
(CPU executes out of ext. program memory):
P2.0−P2.1: D0−D1 program inputs.

- 6 -

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

21

19

13

20

22

8

9
12
13

31
32
42

61
23
24
43
67

10
11

29
30
40

58
21
22
41
63

14

6

4

7

5
6
7

22
23
29

43
15
16
30

-

13
14

4
5
6
7

20
21
25

-

-

-

-

-

PIN

NAME

P2.2
P2.3

(STP)

P2.4

(SDAC10)

P2.5

(SDAC11)

P2.6

(SDAC12)

P2.7

(SDAC13)

P3.0

(RXD)

P3.1

(TXD)

P3.2

(INT0)

P3.3
P3.4 (T0)
P3.5 (T1)

P3.6

P3.7

I/O

TYPE

I/O D2

I/O -

TEST

NAME

D3
D4
D5
D6
D7

-

A12

(PSEN)

-

-

-

-

-

FUNCTIONAL DESCRIPTION

General purpose I/O.
Sink/Source current 4 mA/-100 µA.
Alternate function:
P2.3: STP (Self-Test Pattern) output.
P2.4−P2.7: SDAC10−13 outputs.

While outputing special function, P2.3−P2.7's
Sink/Source current is 4mA/-4mA.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
P2.2−P2.7: D2−D7 data inputs/outputs.
* In the functional test mode
(CPU executes out of ext. program memory):
P2.2−P2.7: D2−D7 program inputs.

General purpose I/O.
Sink/Source current 2 mA/-100 µA.
Alternate function:
P3.0: 8051 serial input port.
P3.1: 8051 serial output port.
P3.2: External interrupt input.
P3.4 and P3.5: Timer/counter 0 and 1 external inputs.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
P3.2: A12 input.
* In the functional test mode
(CPU executes out of ext. program memory):
P3.2: PSEN output (the read strobe to

external program memory) instead of A12.

Publication Release Date: April 1997

- 7 - Revision A1

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

44

42

-

45

43

-

53

51

-

55

-

-

64

-

-

1

-

-

2

-

-

25262324171815

16

27282526192017

18

33 31 24 22

41 39 28 24 TestCLK I/P

PIN

NAME

-

P4.0

-

P4.1

-

P4.2

-

P4.3

-

P4.4

-

P4.5

-

P4.6

HIN
VIN

HOUT
VOUT

RESET

I/O

TYPE

O/P -

I/P

I/O OECTRL

I/P - Reset the controller (active low).

TEST

NAME

-

-

-

-

-

-

OE
CE

PROG

EA

FUNCTIONAL DESCRIPTION

Output port (Latch output).
Sink/Source current 2 mA/-2 mA.

HIN: Hsync/Composite sync input.
VIN: Vsync input.
Schmitt trigger I/P.
With Internal high value pull-down (about 200 KΩ).

No PMOS ESD diode.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):

HIN: OE input.
VIN: CE input.

HOUT: Hsync output.
VOUT: Vsync output with internal weak pull-up (above 200

KΩ).
Sink/Source current 4 mA/-4 mA.

--------------------------------------------------------­* In the Flash/RAM-test mode
(when the chip is in reset state):
HOUT: OECTRL input.

VOUT: PROG input.

Schmitt trigger I/P.
With internal pull-up (about 30 KΩ).
Clock input while in internal (glue logic's) function test.
With internal pull-up (about 30 KΩ).

--------------------------------------------------------­* If the EA (TestCLK) pin is pulled low when the chip is

being reset, and remains low for at least 24 clock periods
after the reset, the CPU will execute from the external
program memory regardless of the PC value. i.e., the CPU is
forced to enter the functional test mode.

- 8 -

Pin Description, continued

W78E354

PIN NO.

68P 64P 48P 40P

141512138989OSCOUT

54 52 37 32 VPP - VPP In the Test/Flash mode, this pin is the power supply input for

68 64 48 40 VDD - - Positive digital power supply, +5V.
16 14 10 10 VSS - - Digital ground.
52 50 - - VDD - - Positive digital power supply, +5V.

34 32 - - VSS - - Digital ground.

38 36 27 - VAA - - Positive analog power supply, +5V.
35 33 25 - VSSA - - Analog ground.

PIN

NAME

OSCIN

I/O

TYPE

O/P

I/P

TEST

NAME

-

-

FUNCTIONAL DESCRIPTION

Output from the inverting oscillator amplifier.
Input to the inverting oscillator amplifier.
Freq.: 16 MHz to 24 MHz.

the Flash cell.

Internally connected to the other power source.

Internally connected to the other power source.

Publication Release Date: April 1997

- 9 - Revision A1

BLOCK DIAGRAM

W78E354

W78E354

DD

V

RESET

OSCIN

OSCOUT

HIN, VIN

HOUT, VOUT

HCLAMP (P1.4)

SOA (P1.5)

RXD (P3.0)
TXD (P3.1)

T0 (P3.4)
T1 (P3.5)

SS

V

Power
Source
Supervisor

Reset
Circuit

WDT

OSC/Timing
Generator

Sync
Processor

Srial Port

Timer 0
Timer1

Autoload
Timer

8031 MCU core
with 256B
Scratchpad RAM

16KB
Flash ROM

256B
Data Memory

Interrupt
Processor

SDAC

DDAC

ADC

DDC

I/O Port

Vpp

INT0 (P3.2)

SDAC0~13

BSDAC0~1

DDAC0~2
BDDAC

ADC0~3

AA, VSSA

V

DSCL (P1.2)

DSDA (P1.3)

Port 1, 2, 3

(except P1.5)

P1.5, Port 4

- 10 -

W78E354

FUNCTIONAL DESCRIPTION

A. 80C31 Core

The W78E354's 80C31 (CMOS MCU) core architecture consists of a CPU surrounded by various
Special Function Registers or SFRs. Some of these SFRs are standard 80C31 registers while others
are new additions, cf. Table 1. The device includes three general purpose I/O ports (P1, P2 and P3),
one output-only port (P4), 256 bytes of scratchpad RAM, two timer/counters (Timer0 and Timer1) and
one 8051 standard serial port. The processor supports 109 different instructions (without "MOVX
A,@DPTR" and "MOVX @DPTR,A") all of which are compatible with those of the MCS-51 family.

One distinguishing feature of the device architecture is the SFR address space into which all the
registers, peripherals and scratchpad RAM are mapped. Many of the instructions operate on an SFR
address rather than a specific register, greatly increasing the power of the instruction set.

The core controller has been designed around a state machine rather than utilizing a microcode
approach, a design methodology which offers several advantages. The first of these is that faster
circuits can be produced due to the fact that flip-flops are inherently faster than ROMs. Secondly, a
ROM-free approach allows the design to be directly utilized in ASIC gate array implementations, an
important factor for cost reductions. Finally, an entire digital logic approach provides better supply
noise immunity in most applications.

Table 1. W78E354's Special Function Registers (SFRs)

F8 FF
F0 + B F7
E8 EF

E0 + ACC E7
D8 + S1CON S1STA S1DAT S1ADR DF
D0 + PSW D7
C8 + CONTREG4 CF
C0 C7

B8 + IP SBRM0 SBRM1 PORT4 SOAREG SOACLR BF

B0 + P3 ADC INTVECT STATUS HFCOUNTL HFCOUNTH VFCOUNTL VFCOUNTH B7

A8 + IE SDAC7 SDAC8 SDAC9 SDAC10 SDAC11 SDAC12 SDAC13 AF

A0 + P2 SDAC0 SDAC1 SDAC2 SDAC3 SDAC4 SDAC5 SDAC6 A7

98 + SCON SBUF BSDAC0 BSDAC1 WDTCLR DDAC0 DDAC1 DDAC2 9F

90 + P1 AUTOLOAD DHREG DVREG DDC1 INTMSK BDDAC DBRM 97

88 + TCON TMOD TL0 TL1 TH0 TH1 PARAL PARAH 8F

80 + CONTREG1 SP DPL DPH CONTREG5 CONTREG2 CONTREG3 PCON 87

Notes:

1. The SFRs with a "+" are both byte- and bit-addressable.

2. The registers in the shaded region are new additions to the 80C31 SFRs.

A.1 Address Space (cf. Figure 1)

The W78E354 CPU operates out of three separate address spaces:

- 11 - Revision A1

Publication Release Date: April 1997

W78E354

1. The first of these is the internal program space (internal Flash memory) with 16K byte size
(0000H− 3FFFH). The program space can be accessed by both opcode fetches and the
"MOVC" instructions.

2. The second is referred to as the data memory space and has a size of 256 bytes (0000H−00FFH).
The data memory is integrated within the chip rather than being outside as in the case of the
standard 8031. The "inside" data memory space is accessed by the "MOVX @Ri" instruction.

3. The third address space has 256 locations while it is used by 384 bytes (256 bytes of RAM and 128
bytes of SFRs).

• The lower 128 locations of this address space (00H−7FH) are for the lower 128 bytes of scratchpad

RAM. Any of these 128 bytes may be used by a programmer but some of them have special uses.
The lowest 32 bytes are organized to four 8-byte register banks. The bank select bits (RS0 and RS1
in the PSW register) selects one of these four banks which is to be used currently as an operand in
the instruction set. Registers 0 to 7 in the bank are referenced by the register direct opcodes.
Registers 0 and 1 may also contain an address that is referenced by the register indirect opcodes.

• The higher 128 locations of this address space (80H−FFH) are shared by the higher 128 bytes of

scratchpad RAM and the Special Function Registers (SFRs). The SFRs are accessed only by "direct"
addressing while the higher 128 bytes of scrachpad RAM are accessed only by "indirect" addressing.
The higher 128 bytes of scratchpad data RAM are also available for stack space.

Address spaces 20H to 2FH are bit-addressable and can be used by the Boolean Variable
Manipulation instructions. For example, bit 0 of address 20H has a Boolean address 00H, and bit 7 of
address 2FH has a Boolean address 7FH. The higher Boolean addresses (80H−FFH) are mapped
into the SFR address space. To determine a Boolean address in some bit-addressable SFR, the
higher 5 bits of the SFR's address can be combined with the 3 lower bits that specify the desired bit in
the SFR.

3FFFH

0000H

On-Chip
Program
Memory

On-Chip
Data
Memory

FFH

(MOVX @Ri)

00H

Figure1. Addres Space

- 12 -

FFH

(Direct Addressing)

80H
7FH

00H

SFR

Scratchpad
RAM

(Direct/Indirect
Addressing)

Scratchpad
RAM

(Indirect Addressing)

A.2 The Modified 80C31 SFRs

1. Timer/Counter Control Register: TCON

BIT NAME FUNCTION

TCON.7 TF1 Timer 1 overflow flag.

Set by hardware on timer/counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine.

TCON.6 TR1 Timer 1 run control bit.

Set/cleared by software to turn the timer/counter on or off.

TCON.5 TF0 Timer 0 overflow flag.

Set by hardware on timer/counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine.

TCON.4 TR0 Timer 0 run control bit.

Set/cleared by software to turn the timer/counter on or off.
TCON.3 - (Reserved, not used by users.)
TCON.2 - (Reserved)

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TCON.1 IE0 Interrupt 0 edge flag.

Set by hardware when an external interrupt edge is detected. Cleared when

the interrupt is processed.
TCON.0 IT0 Interrupt 0 type control bit.

Set/cleared by software to specify falling edge/low level triggered external

interrupt.

2. Power Control Register: PCON

BIT NAME FUNCTION

7 SMOD Double baud rate bit.
6 - (Reserved)
5 - (Reserved, not used by users.)
4 - (Reserved for testing, not used by users.

Normally 0. If set, P2.4−P2.7 will output SDAC8-11 after reset (not power-

on reset).)
3 GF1 General-purpose flag bit.
2 GF0 General-purpose flag bit.
1 PD Power-down mode bit.
0 IDL Idle mode bit.

Publication Release Date: April 1997

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3. Interrupt Enable Register: IE

BIT NAME FUNCTION

IE.7 EA

If EA = 0, no interrupt will be acknowledged (disable all interrupts).

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its enable bit.

IE.6 ­IE.5 *1
IE.4 ES
IE.3 ET1
IE.2 *1
IE.1 ET0
IE.0 EX0

Notes:

*1: No name for ASSEMBLER, must be used via "IE.x".
*2 = (DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT).

(Reserved)

Set/clear to enable/disable the DDC port's I2C interrupt.

Set/clear to enable/disable the serial port 0 interrupt.

Set/clear to enable/disable the Timer 1 overflow interrupt.

Set/clear to enable/disable the *2 interrupt.

Set/clear to enable/disable the Timer 0 overflow interrupt.

Set/clear to enable/disable the external interrupt 0.

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4. Interrupt Priority Register: IP

BIT NAME FUNCTION

IP.7 - (Reserved)
IP.6 - (Reserved)
IP.5 *1 Define the DDC port's I2C interrupt priority level.

If IP.5 = 1, the priority level is higher.

IP.4 PS Define the serial port interrupt priority level.

If PS = 1, the priority level is higher.

IP.3 PT1 Define the Timer 1 interrupt priority level.

If PT1 = 1, the priority level is higher.

IP.2 *1 Define the *2 priority level.

If IP.2 = 1, the priority level is higher.

IP.1 PT0 Define the Timer 0 interrupt priority level.

If PT0 = 1, the priority level is higher.

IP.0 PX0 Define the external interrupt 0 priority level.

If PX0 = 1, the priority level is higher.

Notes:

*1: No name for ASSEMBLER, must be used via "IP.x".

*2 = (DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT).

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