White Electronic Designs W3EG6433S-D3, W3EG6433S-JD3 User Manual

White Electronic Designs

256MB – 2x16Mx64 DDR SDRAM UNBUFFERED

FEATURES DESCRIPTION

W3EG6433S-D3

-JD3

PRELIMINARY*

 DDR266 and DDR333

 Double-data-rate architecture

 Bi-directional data strobes (DQS)

 Differential clock inputs (CK & CK#)

 Programmable Read Latency 2,2.5 (clock)

 Programmable Burst Length (2,4,8)

 Programmable Burst type (sequential & interleave)

 Edge aligned data output, center aligned data input.

 Auto and self refresh

 Serial presence detect

 Dual Rank

 Power supply: 2.5V ± 0.2V

 JEDEC 184 pin DIMM package

• JD3 PCB height: 30.48 (1.20")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

OPERATING FREQUENCIES

DDR333@CL=2.5 DDR266 @CL=2 DDR266 @CL=2 DDR266 @CL=2.5

Clock Speed 166MHz 133MHz 133MHz 133MHz

CL-t

RCD-tRP

2.5-3-3 2-2-2 2-3-3 2.5-3-3

The W3EG6433S is a 2x16Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
component. The module consists of sixteen 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

November 2005
Rev. 2

1

White Electronic Designs Corporation • [phone] • www.wedc.com

White Electronic Designs

W3EG6433S-D3

-JD3

PRELIMINARY

PIN CONFIGURATION

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1V
2 DQ0 48 A0 94 DQ4 140 NC
3VSS49 NC 95 DQ5 141 A10
4 DQ1 50 V
5 DQS0 51 NC 97 DQM0 143 V
6 DQ2 52 BA1 98 DQ6 144 NC
7VCC53 DQ32 99 DQ7 145 V
8 DQ3 54 V

9 NC 55 DQ33 101 NC 147 DQ37
10 NC 56 DQS4 102 NC 148 V
11 V
12 DQ8 58 V
13 DQ9 59 BA0 105 DQ12 151 DQ39
14 DQS1 60 DQ35 106 DQ13 152 V
15 V
16 CK1 62 V
17 CK1# 63 WE# 109 DQ14 155 DQ45
18 V
19 DQ10 65 CAS# 111 CKE1 157 CS0#
20 DQ11 66 V
21 CKE0 67 DQS5 113 NC 159 DM5
22 V
23 DQ16 69 DQ43 115 NC 161 DQ46
24 DQ17 70 V
25 DQS2 71 NC 117 DQ21 163 NC
26 V
27 A9 73 DQ49 119 DM2 165 DQ52
28 DQ18 74 V
29 A7 75 CK2# 121 DQ22 167 NC
30 V
31 DQ19 77 V
32 A5 78 DQS6 124 V
33 DQ24 79 DQ50 125 A6 171 DQ55
34 V
35 DQ25 81 V
36 DQS3 82 V
37 A4 83 DQ56 129 DM3 175 DQ61
38 V
39 DQ26 85 V
40 DQ27 86 DQS7 132 V
41 A2 87 DQ58 133 DQ31 179 DQ63
42 V
43 A1 89 V
44 NC 90 NC 136 V
45 NC 91 SDA 137 CK0 183 SA2
46 V

47 NC 93 V

REF

96 V

SS

100 V

CCQ

57 DQ34 103 NC 149 DM4

SS

61 DQ40 107 DQM1 153 DQ44

CCQ

64 DQ41 110 DQ15 156 V

SS

68 DQ42 114 DQ20 160 V

CCQ

72 DQ48 118 A11 164 V

SS

76 CK2 122 A8 168 V

CCQ

80 DQ51 126 DQ28 172 V

SS

84 DQ57 130 A3 176 V

CC

88 DQ59 134 NC 180 V

SS

92 SCL 138 CK0# 184 V

CC

104 V

SS

108 V

CCQ

112 V

SS

116 V

CC

120 V

SS

123 DQ23 169 DQM6

CCQ

127 DQ29 173 NC

SS

128 V

CCID

131 D30 177 DM7

CC

135 NC 181 SA0

SS

SS

CCQ

SS

CCQ

CC

CCQ

SS

CC

SS

CCQ

SS

CCQ

139 V

SS

142 NC

CCQ

SS

146 DQ36

CC

150 DQ38

SS

154 RAS#

CCQ

158 CS1#

SS

162 DQ47

CCQ

166 DQ53

CC

170 DQ54

CCQ

174 DQ60

SS

178 DQ62

CCQ

182 SA1

CCSPD

PIN NAMES

A0-A11 Address input (Multiplexed)
BA0-BA1 Bank Select Address
DQ0-DQ63 Data Input/Output
DQS0-DQS8 Data Strobe Input/Output
CK0, CK1, CK2 Clock Input
CK0#CK1#, CK2# Clock Input
CKE0, CKE1 Clock Enable input
CS0#, CS1# Chip Select Input
RAS# Row Address Strobe
CAS# Column Address Strobe
WE# Write Enable
DM0-DM7 Data-in-mask
V

CC

V

CCQ

V

SS

V

REF

V

CCSPD

SDA Serial data I/O
SCL Serial clock
SA0-SA2 Address in EEPROM
NC No Connect

Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply

November 2005
Rev. 2

2

White Electronic Designs Corporation • [phone] • www.wedc.com

CS1#
CS0#

DQS0
DM0

DQS1
DM1

DQS2
DM2

DQS3
DM3

White Electronic Designs

FUNCTIONAL BLOCK DIAGRAM

DQS4
DM4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM# CS# DM# CS# DM# CS# DM# CS#

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

DM# CS# DM# CS# DM# CS# DM# CS#

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

DM# CS# DM# CS# DM# CS# DM# CS#

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

DM# CS# DM# CS# DM# CS# DM# CS#

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

DQS

DQS

DQS

DQS

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQS

DQS

DQS

DQS

DQS5
DM5

DQS6
DM6

DQS7
DM7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2

DQS

DQS

DQS

DQS

W3EG6433S-D3

-JD3

PRELIMINARY

DQS

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQS

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQS

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQS

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

SCL

Serial PD

WP

A0

A1

A2

SA0 SA1

SA2

BA0 - BA1 BA0-BA1 : DDR SDRAMs

A0 - A11 A0-A11 : DDR SDRAMs

RAS# RAS# : DDR SDRAMs

CAS# CAS# : DDR SDRAMs

CKE0/1 CKE : DDR SDRAMs

WE# WE# : DDR SDRAMs

November 2005
Rev. 2

SDA

V

CCSPD

V

CC/VCCQ

VREF

V

SS

Clock
Input

*CK0/CK0#
*CK1/CK1#
*CK2/CK2#

*Clock Net Wiring

* Clock Wiring

DDR SDRAMs

4 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs

3

DDR SDRAMs

SPD

DDR SDRAMs

DDR SDRAMs

DDR SDRAMs

DDR SDRAMs

R=120

Card
Edge

Ω

CK0/1/2

CK0/1/2#

Notes :

1. DQ-to-I/O wiring is shown as recommended
but may be changed.

2. DQ/DQS/DM/CKE/CS# relationships must be
maintained as shown.

3. DQ, DQS, DM#/DQS# resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS#, CAS#, WE# resistors: 3 Ohms + 5%.

DDR SDRAMs

*

DDR SDRAMs

*

DDR SDRAMs

DDR SDRAMs

DDR SDRAMs

White Electronic Designs Corporation • [phone] • www.wedc.com

W3EG6433S-D3

White Electronic Designs

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Units

Voltage on any pin relative to V

Voltage on VCC supply relative to V

SS

SS

Storage Temperature T

Power Dissipation P

Short Circuit Current I

Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability

VIN, V

VCC, V

STG

OS

OUT

CCQ

-0.5 to 3.6 V

-1.0 to 3.6 V

-55 to +150 °C

D

24 W

50 mA

-JD3

Recommended perating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C)

DC OPERATING CONDITIONS

Parameter Symbol Min Max Unit Note

Supply Voltage (for device with a nominal V

I/O Supply Voltage V

I/O Reference Voltage V

I/OTermination Voltage V

Input Logic High Voltage V

Input Logic Low Voltage V

Input Voltage Level, CK and CK# Inputs V

Input Differential Voltage, CK and CK# Inputs V

of 2.5V) V

CC

CC

CCQ

REF

TT

IH

IL

IN(DC)

ID(DC)

V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4

Input leakage current I

Output leakage current I

Output High Current(Normal strengh driver); V

Output High Current(Normal strengh driver); V

Output High Current(Half strengh driver); V

Output High Current(Half strengh driver); V

NOTES:

1. V

is expected to be equal to 0.5*V

REF

value.

2. V

is not applied directly to the device. V

TT

V

REF.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

4. The ratio of the pullup current to the pulldown current is specifi ed for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source
voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio
of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

CCQ

= V

= 0.84V I

OUT

TT

= V

= 0.84V I

OUT

TT

= V

= 0.45V V

OUT

TT

= V

= 0.45V V

OUT

TT

of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on V

is a system supply for signal termination resistors, is expected to be set equal to V

TT

I

OZ

OH

OL

OH

OL

2.3 2.7 V

2.3 2.7 V

0.49*V

CCQ

V

-0.04 V

REF

V

+ 0.15 V

REF

-0.3 V

-0.3 V

0.36 V

0.51*V

CCQ

+0.04 V 2

REF

+ 0.3 V

CCQ

-0.15 V

REF

+ 0.3 V

CCQ

+ 0.6 V 3

CCQ

V1

-2 2 uA

-5 5 uA

-16.8 uA

16.8 uA

-9 uA

9uA

may not exceed +/-2% of the dc

REF

, and must track variations in the DC level of

REF

November 2005
Rev. 2

4

White Electronic Designs Corporation • [phone] • www.wedc.com