■ Commercial, Industrial and Military Temperature Ranges
■ 32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
■ 36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
■ Single +5V (±10%) Supply Operation
FIG. 1 PIN CONFIGURATION
36 PIN
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 PIN
TOP VIEW
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
Voltage on any pin relative to Vss-0.5 to 7.0V
Operating Temperature TA (Ambient)
Commercial0 to +70°C
Industrial-40 to +85°C
Military-55 to +125°C
Storage Temperature, Plastic-65 to +150°C
Power Dissipation1.5W
Output Current20mA
Junction Temperature, T
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Address LinesCIVIN = Vcc or Vss, f = 1.0MHz 12 pF
Data LinesC
These parameters are sampled, not 100% tested.
TRUTH TABLE
IL-0.3—+0.8V
CAPACITANCE
(TA = +25°C)
OVOUT = Vcc or Vss, f = 1.0MHz 14 pF
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C TO +125°C)
ParameterSymbol ConditionsUnits
Input Leakage CurrentILIVIN = 0V to VCC-1010µA
Output Leakage CurrentILOVI/O = 0V to VCC-1010µA
Operating Power Supply CurrentICC1WE, CS = VIL, II/ O = 0mA, Min Cycle (17ns)—250mA
Standby (TTL) Power Supply CurrentICC2CS ³ VIH, VIN£ VIL, VIN³ VIH—60mA
Full Standby Power Supply CurrentI CC3CS ³ VCC -0.2V CA—25mA
Output Low VoltageVOLIOL = 8.0mA—0.4V
Output High VoltageV
NOTE: DC test conditions: V
IL = 0.3V, VIH = Vcc -0.3V
(20 -55ns)—225mA
VIN³ Vcc -0.2V or VIN£ 0.2V LPA—20mA
OHIOH = -4.0mA2.4—V
MinMax
AC TEST CONDITIONS
Figure 1Figure 2
Q
255Ω
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
Vcc
480Ω
30pF
Vcc
Q
255Ω
480Ω
5pF
Input Pulse LevelsVSS to 3.0V
Input Rise and Fall Times5ns
Input and Output Timing Levels1.5V
Output LoadFigure 1
NOTE: For t
2
EHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
EDI88512CA
ParameterJEDEC Alt.Min Max Min Max Min Max Min Max Min Max M in Max Min Max Units
Symbol 15ns 17ns 20ns 25ns 35ns 45ns 55ns
Read Cycle TimetAVAVtRC15172025354555n s
Address Access TimetAVQVtAA15172025354555ns
Chip Enable Access TimetELQVtACS15172025354555ns
Chip Enable to Output in Low Z (1)tELQXtCLZ2333333ns
Chip Disable to Output in High Z (1)tEHQZtCHZ07 07 08 010015020020ns
Output Hold from Address ChangetAVQXt OH0000000ns
Output Enable to Output ValidtGLQVtOE881012152530ns
Output Enable to Output in Low Z (1)tGLQXtOLZ0000000ns
Output Disable to Output in High Z(1)t
GHQZtOHZ07 07 08 010015020020ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
ParameterJEDEC Alt.Min Max Min Max Min Max M in Max Min Max Min Max Min Max Units
Write Cycle TimetAVAVtWC15172025354555ns
Chip Enable to End of Writet
Address Setup Timet
Address Valid to End of Writet
Write Pulse Widtht
Write Recovery Timet
Data Hold Timet
Write to Output in High Z (1)tWLQZt WHZ080808010025030030ns
Data to Write Timet
Output Active from End of Write (1)t
1. This parameter is guaranteed by design but not tested.