White Electronic Designs EDI88512LP70CC, EDI88512LP70CB, EDI88512LP100NM, EDI88512LP100NI, EDI88512LP100NC Datasheet
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White Electronic Designs Corporation • www.whiteedc.com • (602) 437-1520
HI-RELIABILITY PRODUCT
EDI88512C
512Kx8 Monolithic SRAM CMOS
FEATURES
■ 512Kx8 bit CMOS Static
■ Random Access Memory
• Access Times of 70, 85, 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
■ 32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic SOJ (Package 140)
■ Single +5V (±10%) Supply Operation
February 2001 Rev. 11
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
A0-18 Address Inputs
WE Write Enables
CS Chip Selects
OE Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
Ø-18
I/O
Ø-7
WE
CS
OE
FIG. 1 PIN CONFIGURATION
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. Both the DIP and CSOJ packages are
pin for pin upgrades for the single chip enable 128K x 8, the
EDI88128C. Pins 1 and 30 become the higher order addresses.
A Low Power version with Data Retention (EDI88512LP) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
2
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
EDI88512C
ABSOLUTE MAXIMUM RATINGS
Parameter Unit
Voltage on any pin relative to Vss -0.5 to 7.0 V
Operating Temperature T
A (Ambient)
Commercial 0 to +70 °C
Industrial -40 to +85 °C
Military -55 to +125 °C
Storage Temperature, Plastic -65 to +150 °C
Power Dissipation 1 W
Output Current 20 mA
Junction Temperature, TJ 175 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Voltage VSS 000V
Input High Voltage VIH 2.2 — Vcc +0.5 V
Input Low Voltage V
IL -0.3 — +0.8 V
Parameter
Symbol
Condition Max Unit
Address Lines CI
VIN = Vcc or Vss, f = 1.0MHz
12 pF
Data Lines C
O
V
OUT
= Vcc or Vss, f = 1.0MHz
14 pF
These parameters are sampled, not 100% tested.
CAPACITANCE
(T
A = +25°C)
TRUTH TABLE
OE CS WE Mode Output Power
X H X Standby High Z Icc
2, Icc3
H L H Output Deselect High Z Icc
1
L L H Read Data Out Icc1
X L L Write Data In Icc1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 1.5V
Output Load Figure 1
NOTE: For t
EHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
30pF
480Ω
Vcc
Q
Figure 1 Figure 2
255Ω
5pF
480Ω
Vcc
Q
255
Ω
AC TEST CONDITIONS
Parameter Symbol Conditions Units
Min Typ* Max
Input Leakage Current ILI VIN = 0V to VCC ——±10 µA
Output Leakage Current ILO VI/O = 0V to VCC ——±10 µA
Operating Power Supply Current ICC1 WE, CS = VIL, II/O = 0mA, Min Cycle (70-100ns) — 45 75 mA
Standby (TTL) Power Supply Current ICC2 CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH —3 10mA
Full Standby Power Supply Current ICC3 CS ≥ VCC -0.2V C — — 5 mA
VIN ≥ Vcc -0.2V or VIN ≤ 0.2V
LP — — 2 mA
Output Low Voltage VOL IOL = 2.1mA — — 0.4 V
Output High Voltage V
OH IOH = -1.0mA 2.4 — — V
NOTE: DC test conditions: V
IL = 0.3V, VIH = Vcc -0.3V
DC CHARACTERISTICS
(V
CC
= 5V, *TA = -55°C to +125°C)
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
EDI88512C
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, VSS = 0V, TA
= 0°C to +70°C)
Symbol 70ns 85ns 100ns
Parameter JEDEC Alt. Min Max Min Max Min Max Units
Read Cycle Time tAVAV tRC 70 85 100 ns
Address Access Time tAVQV tAA 70 85 100 ns
Chip Enable Access Time tELQV tACS 70 85 100 ns
Chip Enable to Output in Low Z (1) tELQX tCLZ 10 10 10 ns
Chip Disable to Output in High Z (1) tEHQZ tCHZ 25 30 30 ns
Output Hold from Address Change tAVQX tOH 10 10 10 ns
Output Enable to Output Valid tGLQV tOE 35 45 50 ns
Output Enable to Output in Low Z (1) tGLQX tOLZ 55 5 ns
Output Disable to Output in High Z(1) t
GHQZ tOHZ 025030 030ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, VSS = 0V, TA
= 0°C to +70°C)
Symbol 70ns 85ns 100ns
Parameter JEDEC Alt. Min Max Min Max Min Max Units
Write Cycle Time tAVAV tWC 70 85 100 ns
Chip Enable to End of Write t
ELWH tCW 60 70 80 ns
tELEH tCW 60 70 80 ns
Address Setup Time t
AVWL tAS 00 0 ns
tAVEL tAS 00 0 ns
Address Valid to End of Write t
AVWH tAW 65 70 80 ns
tAVEH tAW 65 70 80 ns
Write Pulse Width t
WLWH tWP 50 55 60 ns
tWLEH tWP 50 55 60 ns
Write Recovery Time t
WHAX tWR 00 0 ns
tEHAX tWR 00 0 ns
Data Hold Time t
WHDX tDH 00 0 ns
tEHDX tDH 00 0 ns
Write to Output in High Z (1) tWLQZ tWHZ 025030 0 30ns
Data to Write Time t
DVWH tDW 40 40 40 ns
tDVEH tDW 30 35 40 ns
Output Active from End of Write (1) t
WHQX tWLZ 55 5 ns
1. This parameter is guaranteed by design but not tested.
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