White Electronic Designs EDI88130CS Technical data

查询EDI88130CS供应商

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns

■ Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

■ CS1, CS2 & OE Functions for Bus Control

■ Inputs and Outputs Directly TTL Compatible

■ Organized as 128Kx8

■ Commercial, Industrial and Military Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)

• 32 lead Ceramic SOJ (Package 140)

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

■ Single +5V (±10%) Supply Operation

The EDI88130CS is a high speed, high performance, 128Kx8 bits
monolithic Static RAM.

An additional chip enable line provides system memory security
during power down in non-battery backed up systems and memory
banking in high speed battery backed systems where large mul­tiple pages of memory are required.

The EDI88130CS has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data retention
function for battery back-up applications.

Military product is available compliant to MIL-PRF-38535.

*15ns access time is advanced information, contact factory for availability.

EDI88130CS

HI-RELIABILITY PRODUCT

FIG. 1 PIN CONFIGURATION

32 DIP
32 SOJ
32 CLCC
32 FLATPACK

TOP VIEW

NC
A16
A14
A12

A7

A6

A5

A4

A3

A2

A1

AØ

I/OØ

I/O1
I/O2

V

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

SS

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

CC

A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3

I/O

5

A

7

6

A

6

7

A

5

8

A

4

9

A

3

10

A

2

11

A

1

12

A

0

13

0

32 QUAD LCC

TOP VIEW

A12A14A16NC

4321

14 15 16 17 18 19 20

2

I/O1I/O

VCCA15CS

32 31 30

VSS

I/O3I/O4I/O5I/O

PIN DESCRIPTION

I/O0-7 Data Inputs/Outputs

2

29

WE

28

13

A

27

A

8

26

A

9

25

A

11

24

OE

23

10

A

22

CS

1

21

I/O

7

6

Ø-16

A

WE

CS

1

CS

2

OE

BLOCK DIAGRAM

Address

Buffer

A0-16 Address Inputs

WE Write Enable

CS1, CS2 Chip Selects

OE Output Enable

VCC Power (+5V ±10%)
VSS Ground
NC Not Connected

Memory Array

Address
Decoder

I/O

Circuits

I/O

Ø-7

July 2001 Rev. 10

1

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EDI88130CS

ABSOLUTE MAXIMUM RATINGS

Parameter Unit

Voltage on any pin relative to Vss -0.2 to 7.0 V
Operating Temperature TA (Ambient)
Industrial -40 to +85 °C
Military -55 to +125 °C
Storage Temperature, Ceramic -65 to +150 °C
Power Dissipation 1.7 W
Output Current 40 mA
Junction Temperature, T

NOTE:

Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi­cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

J 175 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 V
Supply Voltage VSS 000V
Input High Voltage VIH 2.2 — Vcc +0.5 V
Input Low Voltage V

IL -0.5 — +0.8 V

OE CS1 CS2 WE Mode Output Power

X H X X Standby High Z Icc
X X L X Standby High Z Icc2, Icc3
H L H H Output Deselect High Z Icc1
L L H H Read Data Out Icc1
X L H L Write Data In Icc1

Parameter

Address Lines CI
Data Lines C

These parameters are sampled, not 100% tested.

TRUTH TABLE

CAPACITANCE

(T

Symbol

VIN = Vcc or Vss, f = 1.0MHz

OVOUT

= Vcc or Vss, f = 1.0MHz

A = +25°C)

Condition

Max

CSOJ,DIP,

LCC

Flatpack

612pF
814pF

DC CHARACTERISTICS

(V

CC

= 5V, TA = -55°C to +125°C)

Parameter Symbol Conditions Units

Input Leakage Current ILI VIN = 0V to VCC ——±5 µA
Output Leakage Current ILO VI/O = 0V to VCC ——±10 µA

(15-17ns) — 300 mA

Operating Power Supply Current ICC1 WE, CS1 = VIL, II/O = 0mA, CS2 = VIH (20ns) — 225 mA

(25-55ns) — 200 mA

Standby (TTL) Power Supply Current ICC2

Full Standby Power Supply Current ICC3 CS (15ns) — — 15 mA

Output Low Voltage VOL IOL = 8.0mA — — 0.4 V
Output High Voltage V

CS1 ≥ VIH and/or CS2 ≤ VIL,
VIN ≥ VIH or ≤ VIL

CS1 ≥ VCC -0.2V and/or CS2 ≤ 0.2V
VIN ≥ Vcc -0.2V or VIN ≤ 0.2V LPS — — 5 mA

OH IOH = -4.0mA 2.4 — — V

(17-55ns) — 25 mA

(15ns) — 60 mA

CS (17-55ns) — 3 10 mA

Min Typ Max

2, Icc3

Unit

AC TEST CONDITIONS

Figure 1 Figure 2

Q

255Ω

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Vcc

480Ω

30pF

Q

Ω

255

Vcc

480Ω

5pF

Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Levels 1.5V
Output Load Figure 1

NOTE: For t

EHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)

2

EDI88130CS

AC CHARACTERISTICS – READ CYCLE (15 to 20ns)

(V

CC

= 5.0V, VSS = 0V, TA = -55°C to +125°C)

Symbol 15ns* 17ns 20ns

Parameter JEDEC Alt. Min Max Min Max Min Max Units

Read Cycle Time tAVAV tRC 15 17 20 ns
Address Access Time tAVQV tAA 15 17 20 ns
Chip Enable Access Time t

Chip Enable to Output in Low Z (1) t

Chip Disable to Output in Low Z (1) t

Output Hold from Address Change tAVQX tOH 333ns
Output Enable to Output Valid tGLQV tOE 667ns
Output Enable to Output in Low Z (1) tGLQX tOLZ 000ns
Output Disable to Output in High Z(1) tGHQZ tOHZ 568ns
Chip Enable to Power Up (1) t

Chip Enable to Power Down (1) tE1HICCL tPD 15 17 20 ns

1. This parameter is guaranteed by design but not tested.
* 15ns access time is advanced information, contact factory for availability.

E1LQV tACS 15 17 20 ns

tE2HQV tACS 15 17 20 ns

E1LQX tCLZ 555ns

tE2HQX tCLZ 555ns

E1HQZ tCHZ 678ns

tE2LQZ tCHZ 678ns

E1LICCH tPU 000ns

tE2HICCH tPU 000ns

tE2LICCL tPD 15 17 20 ns

AC CHARACTERISTICS – READ CYCLE (25 to 55ns)

(V

CC

= 5.0V, VSS = 0V, TA = -55°C to +125°C)

Symbol 25ns 35ns 45ns 55ns

Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units

Read Cycle Time tAVAV tRC 25 35 45 55 ns
Address Access Time tAVQV tAA 25 35 45 55 ns
Chip Enable Access Time tE1LQV tACS 25 35 45 55 ns
Chip Enable Access Time tE2HQV tACS 25 35 45 55 ns
Chip Enable to Output in Low Z (1) t

Chip Disable to Output in Low Z (1) t

Output Hold from Address Change tAVQX tOH 0000ns
Output Enable to Output Valid tGLQV tOE 10 15 20 25 ns
Output Enable to Output in Low Z (1) tGLQX tOLZ 0000ns
Output Disable to Output in High Z(1) tGHQZ tOHZ 10 15 20 20 ns
Chip Enable to Power Up (1) tE1LICCH tPU 0000ns

Chip Enable to Power Down (1) t

1. This parameter is guaranteed by design but not tested.

E1LQX tCLZ 5555ns

tE2HQX tCLZ 5555ns

E1HQZ tCHZ 10 15 20 20 ns

tE2LQZ tCHZ 10 15 20 20 ns

tE2HICCH tPU 0000ns

E1HICCL tPD 25 35 45 55 ns

tE2LICCL tPD 25 35 45 55 ns

3

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