Western Digital AC160l, AC2120 Technical Reference Manual

Caviar AC160lAC2120

Technical Reference Manual

~

WESTERN

DIGITAL

Information furnished no responsibility is assumed patents or

or

other rights

otherwise under any patent

tion reserves the right to Western

Digita~

QY

Western Digital Corporation is believed

by

Western Digital Corporation for its use; nor for any infringements of

of

third parties whicb

or

patent rights of Western Digital Corporation. Western Digital Corpora-

may

result from its use. No license is granted by implication

change specifications at any time without notice.

to

be accurate and reliable. However,

..'

AutoSwitch, and Paradise are registered trademarks and CacheFlow,Caviar,

FIT. Lab, Hyperseek, Interarchitecture, PinScan, Piranha, SAM, Tidbit, and TrueShade ,are trademarks of Western Digital

Cp rpo rat

jon.

.

Other marks may be mentioned herein that Jjelong to other companfes.

Western Digital

Western Digital Plaza,

For

Service

(714) 932-4900

Corporation

and

Literature, call:

8105.

Irvine Center Drive, Irvine, CA

~2718

CONTENTS

1.0

2.0

DESCRIPTIONS

1.1

1.2 SPECIFICATIONS

2.1

2.2

2.3

2.4

2.5

2.6

AND GENERAL ADVANCED

PERFORMANCE PHYSICAL

2.2.1

2.2.2

2.2.3 ELECTRICAL

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5 ENVIRONMENTAL

2.4.1

2.4.2

2.4.3

2.4.4 AGENCY RELIABILITY

DESCRIPTION

SPECIFICATIONS Physical Weight Mechanical

Typical Power Power Ripple Power

Shock

Temperature Atmospheric Acoustics

APPROVALS

FEATURES

PRODUCT

SPECIFICATIONS

SPECIFICATION

FEATURES

SPECIFICATIONS

Dimensions

Specifications

Current Management -Drive Management -Drive

Connectors

and

And

Power

and

Cables

SPECIFICATIONS

Vibration

and

Humidity

Pressure

Dissipation

Spinning Not

Spinning

1 1 2

5 5 6 7 7 8

9 9 9

·

10

·

10

·

11

·

12

·

12

·

12

·

12

·

13

·

13

·

13

3.0

PRINCIPLES

3.1

OF

DRNE

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

3.1.7

3.1.8

3.1.9

3.1.10

OPERATION

ELECTRONICS

WD42C22 Buffer

RAM WD60C11 WD10C23 Microprocessor Pulse

Detector Spindle Actuator Gate Frequency

Motor

Array

Western Digital Corporation

Winchester Servo

Controller

Data

Separator ROM

Driver

Fusion

II

Synthesizer

Disk

and

Controller

RAM

·

15

·

15

·

15

·

15

·

16

·

16

·

16

·

16

.17 .17 .17

·

17

Caviar AC160lAC2120 Technical Reference Manual

HEAD

DISK

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

ASSEMBLY Base/Cover Spindle Disk

Stack Headstack Voice

Coil

Air

Filtration

(HDA)

Assembly

Motor

Assembly Assembly

Assembly

System

~

·

20 .20 .

20

·

21

·

21

·

21 .22

4.0

5.0

ADVANCED

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9 HOST

5.1

5.2

5.3

PRODUCT

CACHEFlOW

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5 DEFECT CHARACTERISTICS

4.2.1

4.2.2 ERROR TRANSLATION DUAl POWER DMA BLOCK ZONED

INTERFACE

J2

HOST

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

5.2.10

5.2.11

5.2.12

5.2.13 CAVIAR

FEATURES

Purpose Benefits CacheFlow Sequential Repetitive

MANAGEMENT

Defect Format

RECOVERY

ORNE

CONSERVATION

COMPATIBILITY

MODE

RECORDING

AND

ASSIGNMENTS

INTERFACE

Register Data Error Write Sector Sector Cylinder SDH Status Command Alternate Fixed Digital

AC160/AC2120

of

CacheFlow

of

Cache Operation

Mode

AND

Management

Characteristics

OPTION

AT

COMMAND

REGISTERS

Address Register Register

Precompensation

Count

Register

Number

Register

Disk

Input

Register

low

And

Register

Status

Control

Register

COMMANDS

Flow

FORMAT

SET

Map

Register

Cylinder

Register

High

Registers

.23 .23 .23

·

23 .24 .24 .24

.26 .26 .26 .27 .28 .28 .29 .30 .30 .30

·

31

·

31 .34 .34

.34 .35 .37 .37 .37 .38 .39

.40

·

41

·

41

·

41 .42

.43

ii

Western Digital Corporation

5.4

5.5

5.6

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.12

5.3.13

5.3.14

5.3.15

5.3.16

5.3.17

5.3.18

5.3.19

5.3.20

5.3.21

5.3.22

5.3.23 HOST

INTERFACE

HOST

INTERFACE

ERROR

REPORTING

Recalibrate Seek

(70H)

Read

Sector

Write

Sector

Format

Track

Read

Verify Execute Set Write Read Read Write Set Standby Idle Standby Idle Read Check Sleep

Write Identify Set

Diagnostics

Drive

Parameters

DMA DMA(C8H) Multiple

Multiple

Immediate

(E2)

(E3H)

Buffer

Power

(E6) Buffer

Drive

Buffer

Mode

READ

WRITE

(1XH)

(2XH)

(30H) (50H)

(40H)

(CAH)

(C4H)

(C5H)

(C6H)

(E1H)

(E4H)

Mode

(E8H)

(ECH)

(EFH)

TIMING

(90H)

(91

H)

(EOH)

(E5)

.44

·

45

.46

·

47

.48

·

49

.50

·

51

·

52

·

53

.54

.55

.56

·

57

.58

·

59

·

60

·

61

·

62

·

63

·

64

·

65

·

67

.68

·

69

·

70

6.0

INSTALLATION

6.1

6.2

6.3

6.4

AND

UNPACKING

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5 MOUNTING

6.2.1

6.2.2 INSTALLATION

6.3.1

6.3.2

6.3.3 INSTALLING

6.4.1

6.4.2

SETUP

Handling Inspection Removal Removal Moving

Orientation Screw

Determining Dual

Jumper Mounting

Cabling

Precautions

RESTRICTIONS

Size

CONFIGURATION

Installations

Settings

THE

CAVIAR

and

Western Digital Corporation

- -

-------

PROCEDURES

Precautions

of

Shipping

From

Shipping

From

Antistatic

Limitations

Your

DRIVE

the

Drive

Installation

.

Container

Bag

Configuration

Steps

·

71

·

.71

·

71

·

71

·

71

.72 .72 .72 .72 .72

·

73

·

73

·

73

·

73

·

75

·

75

·

75

iii

Caviar AC160/AC2120 Technical Reference Manual

6.5

6.6

7.0

B.O

9.0

10.0

MAINTENANCE WESTERN TROUBLESHOOTING GLOSSARY

FIGURES

Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure

2-1. 2-2. 3-1. 3-2. 4-1. 5-1. 5-2. 5-3. 6-1. 6-2. 6-3. 6-4.

Caviar

+

12V Caviar Mechanical CacheFlow

Standard

Host Host

Jumper Standard

Caviar

Y-Adapter

INSTAlLING SETUP

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

6.6.6

DIGITAl

AC160/AC2120

Current

Block

Interface Interface

Settings

Connector

THE

PROCEDURES

Preparing Selecting Partitioning High-level Booting Preparing

DRIVE

Draw

Diagram

Exploded

.....

Factory

Read Write

Factory

Cabling

ADAPTER

. . . . . . . . .

the

Caviar

Drive

Tables

the

Drive

DOS

Formatting

the

System

the

Caviar

UTILITY

Mounting

During

Spin

. . . . .

View

AC2120

Connectors

Timing

....

Connectors

Locations

. . . .

CARD

Up

. .

.

. . . .

Drive

for

.....

For

Use

.....

Drive

for a Novell

Dimensions

(Master

Use

Under

...

Mode)

. .

DOS

. .

Network

.79 .79 .79

·

BO

·

81

·

81

.82

·

82

.83

.85

·

87

.89

· 8

·

10

·

18

·

19

·

25

·

31

.68

.69

.74 .76

.77

.7B

TABLES

Table Table Table Table Table Table

5-1. 5-2. 5-3. 5-4. 5-5. 6-1.

J2 Task Standard

Error Drive

Description

File

Identify

Reporting

Table

Map

Command

Drive

Command

Parameters

Opcodes

·

32

.34

.43

.66 .70

·

BO

Western Digital Corporation

Radio

Frequency Interference Statement

This

Western

a

Class B computing

does

not

guarantee

Digital

that

product

device

has

pursuant

interference

been

to

will

verified

Part

15,

not

occur

to

comply

subpart

in

individual

with

B,

of

the

FCC

insta

limits

rules.

lIations.

for

This

Western ference

If owner's relocation placing

This

digital apparatus of

Communications.

Digital

caused

interference

manual

of

the

apparatus

setout

is

not

by

unauthorized

problems

for

suggestions.

the

computer

does

inthe

Radio

responsible

do

occur,

system

AC

power

not

exceed

Interference

for

any

television,

modifications

please

consult

Some

of

these

away

from

connection

the

on a different

Class B limits

Regulations

radio,

of

this

product.

the

suggestions

the

television

for

of

the

or

other

system

radio

Canadian

circuit

noise

equipment

include

or

Department

inter-

the

radio,

outlet.

for

digital

or

Western Digital Corporation

v

Caviar

AC160lAC2120

Technical Reference Manual

Western Digital Corporation

DESCRIPTIONS AND FEATURES

1.0

DESCRIPTIONS AND FEATURES

1.1

GENERAL

The

Caviar

of

formatted

Designed

that

Caviar disk during performance. and

Caviar shipment.

•

for

achieves

features

caching

disk

80486SX

drives

Additional

•

Linear

•

Automatic Embedded DMA

Cache Power 56-bit

DESCRIPTION

series

of

Western

storage

use

in

AT-compatible

unsurpassed

CacheFlow,

system,

operations

systems,

logical/physical

and

Flow Conservation

error

which

To

meet

are

preformatted

Caviar

head

servo

Block

correction

Digital

in a 3.5-inch

reliability

Western dynamically

to

the

optimum

the

demands

Caviar

has

features

address

parking

control

Mode

data

code

intelligent

form

factor

systems,

and

optimum

Digital's

partitions

caching

of

high

an

average

(low-level)

include:

translation

on

each

transfers

drives

and

Caviar

is

performance.

exclusive

the

mode

performance

seektime and

defects

track

provides

low

the

multi-segmented

32-KByte

to

dramatically

of

62/125

profile

premier

80386,

less

than

are

mapped

1-inch

storage

buffer

80386SX,

15

megabytes

height.

solution

adaptive

and

adapts

enhance

milliseconds.

out

read

80486

before

Western design computer communication

Designers first-hand

interaction

compatibility

Digital

and

manufacturing

functions,

in

each

knowledge

between

Western Digital Corporation

offers

including

functions

arena

and

build

reliable,

into a process

storage,

are

integrated

work

closely

of

all

the

component

in

designers

exclusive

cost-effective

known

intelligent

into a variety

with

each

components

functionality.

that

means

storage drive

other,

solutions

as

interarchitecture.

control.

of

platform-specific

developing

interact

Western

core

in

the

Digital

by

integrating

Critical

logic,

video

solutions.

solutions

platform.

can

guarantee

and

with

This

a

1

Caviar

AC160lAC2120

Technical

R~ference

Manual

1.2

ADVANCED

CacheFlow

Designed rotational multi-segmented size is Caviar's

selects

Power

The allows

of

power consumption

DMA

ATA implementing improvements transfers. the

exclusively

latency

of

the

data

sequential,

32-KByte

the

appropriate

ConselTJation

Caviar

supports

the

host

power

management

saving

while

compatible

The

Caviar

drive

PRODUCT

by

Western

delays,

disk

caching

request

random,

(optional

the

to

reduce

feature

the

DMA

Read

EISA

type B DMA.

in

data

transfer

system

transfers

system.

but

the

or

repetitive.

64-KByte)

caching

ATA

Power

the

power

commands.

which drive

is

and

rates

CPU

is

freed

data

FEATURES

Digital

to

CacheFlow

type

of

data

request, CacheFlow RAM

mode

for

optimum

management

consumption

In

addition

results

directly

in a substantial

spinning

DMA

and

up

at

Write

DMA

CPU

allowing

with

its

the

minimize

is

buffer

the

rated

commands

data

bandwidth

disk-seeking

the

industry's

constantly

that

then

into

system

command

of

the

Caviar

speed.

transfers

it

to

accomplish

system

operations

first

evaluates

is,

whether dynamically equal-sized

performance.

set.

drive

by

provides a vendor-unique

saving

are

supported

provide

over

conventional

memory.

not

the

partitions

segments

This

command

issuing a variety

of

average

other

tasks

and

adaptive,

only

the

application

the

and

set

power

in

systems

significant

PIO

data

while

2

Zoned

The the the

Block

ATA maximum sectors. between

Recording

AC160/

AC2120

outer

tracks

innermost

Mode

compatible

blocking

Block

system

Automatic

Head

parking

down,

the

heads

improving

data

drives

of

the

tracks,

thereby

Read

Multiple

tactorforthe

mode

increases

interrupts.

Head

is

automatic

retract

integrity

employ

drive.

The

increasing

and

Caviar

overall

Parking

with

to a safe,

and

resistance

Zoned

Recording

outermost

the

Write

drive

data

the

Caviar

non-data

to

to tracks total

capacity

Multiple

with

32

transfer

series

landing

shock.

increase

contain

commands

KB

of

rates

of

intelligent

zone

the

data

20%

more

of

the

drive.

are

supported.

CacheFlow

by

transferring

and

buffer

drives. lock

into

density

sectors

is

more

On

position.

Western Digital Corporation

on

than

The

eight

data

power

DESCRIPTIONS AND FEATURES

Advanced

The

Caviar complement manufacturing out

with

modifications

Embedded

The

Caviar information each

data

high

sampling

well

as

The

Caviar

Dual

The

Caviar

assembly

Defect

is

preformatted

of

defect

process,

Western

are

required

Digital's

Sector

features

to

sector

highly

records

an

the

head

and

rate

supports

accurate

servo

Drive Operation

supports

and

configuration

InteUigent Drive

Management

(low

management

media

defects

high

performance

before

installation.

Sel"Do

embedded

position

provides

head

data

dual

Control

sector

servo

position

the

servo

positioning.

on

every

drive

operation

options

level)

at functions. found

servo

system.

updates

bandwidth

sector

by a means

for

master

the

factory

Extensively

during

intelligent

defect

as

the

The

embedded

on a sector

required

for

precise

or

slave

and

comes

tested

burn

management

means

for

head

of

drive

technique.

of

providing

information

by

sector

fast

access

positioning.

a

"daisy

designation.

with a full

during

in

are

mapped

feedback precedes

basis.

times

chain"

the

No

This

as

cable

The

Caviar

does

not

controller

circuitry

Universal

The

Caviar addresses compatibility

Error

Caviar correction

provides a linear

to

Recovery

uses a 56-bit

of

require a slot-mounted

and

4O-pin

Data

with

errors

Translation

physical

numerous

in

the

sector

Error

Correction

data

drive

ATA

IDE

disk

addresses

types.

field.

controller

connector

address

which

Code

card.

attached

translator

provides

(ECC)

for

The

hard

directly

to

convert

for

easy

automatic

disk

has

to

the

drive.

logical

installation

detection

sector

the

and

Western Digital Corporation 3

Caviar AC160lAC2120 Technical Reference Manual

Guaranteed Compatibility

Western

(FIT

operating

Digital

Lab.)

performs

to

ensure

systems.

extensive

compatibility

testing

with

in

AT-compatible

its

Functional

Integrity

computers

Testing

and

standard

Labs

4

Western Digital Corporation

SPECIFICATIONS

2.0

SPECIFICATIONS

2.1

PERFORMANCE SPECIFICATIONS

Average Track-to-Track Maximum

Index Average Rotational Controller Data

Interleave Buffer

Error Error Spindle

Spindle Start/Stop

Seek

Pulse

Latency

Speed

Overhead

Transfer

-

Buffer

-

Buffer

Size

Rate -Recoverable Rate -Unrecoverable

Start Stop

Cycles

*

Seek

Period

Rate

to

Disk

to

Host

Time

**

Sub-15 6 28

16.67

8.34 3605

0.3 Zone

Zone

6.0 1:1 32-KByte optionall

<1 <1 5 15 6 10,000

Milliseconds

Revolutions/min.

Milliseconds

1 =

15.375

2 =

12.5

MBytes/second

Static

in

10 0 bits

12

in

10

bits

seconds seconds

typical,

seconds

maximum

cycles

average

Mbits/second

RAM

(64-KByte

read read

minimum

"Average

*

between

of

all

ordered

* *

"Data

Transfer

transfer

Western Digital Corporation

Seek"

all

possible

pairs. Rate

of

buffered

is

determined

ordered

from

the

data

in

by

dividing

pairs

of

..

Buffer

to

MBytes

track

the

per

second.

the

total

addresses

Host"

is

based

time

by

required

the

total

on

the

sustained

to

seek

number

5

Caviar AC160lAC2120 Technical Rt;{erence Manual

2.2

PHYSICAL SPECIFICATIONS

Physical Specifications

Recommended Parameters

Formatted Interface Actuator Number Data

Surfaces

Number

Average Formatted

Capacity Bytes

per

Setup

*

Capacity

Type

of

Disks

of

Heads

of

Cylinders

Track

Density

Cylinder

(Bytes)

Sector

(Hd)

(Cyl)

Caviar

1024x (Cyl x Hd

62.4MBytes 4O-pin Rotary 1 2 2 4 Zone 1 =970

Zone

1712

Zone Zone

512

AC160

7 x

x

PCI

AT

Voice

2=379 TPI 1 =

48,640

2 =

40,448

17

spn

IDE

Coil

Caviar

872x8x35 (Cyl x Hd x SPT)

125MBytes 4O-pin Rotary 2 4

Zone 1 =970 Zone

1712

Z1 Z2 = 80,896

512

AC2120

PC/AT Voice

2=379

TPI

=97,280

IDE

Coil

User

Sectors

Physical per

Track

User

Sectors

Cylinder Servo Recording Recording Flux

Density ECC Head

BPI -Bits FCI -Flux IDE -Integrated

Sectors

(SPT)

Type

Method Density

Park**

Per Changes

per

Inch

Drive

Per

Drive

122,091

Z1

=48

Z2=4O Z1 = (2 x 48)

Z2 = (2 x 40) Embedded 2,7

Rll 33,666 22,444FCI 56

bit

Automatic Parking

Inch

Electronics

-1 =

95

-1 =

79

BPI

Head

Rll-

Run

length SPT -Sectors TPI -Tracks

244,182 Z1

Z2=4O

(4 x 48) (4x40)-2=158

Embedded 2,7 33,666 22,444 56

Automatic

Parking

limited

Per

Track

Per

Inch

=48

RLL

bit

-2 =

BPI FCI

Head

190

6 Western Digital Corporation

*

Do

AC160 number limits returning

**

Seeking

read/write

causes

not

exceed

and

of

results

to a sector

the

244.182

cylinders.

in

the

an

ID

NDT

heads

and

Caviar

to

maximum

sectors

drive

greater

for

heads

and

parking,

FOUND

perform

spins

error

than

down

sector

capacity

Caviar

sectors

spinning

to

or

equal

the

an

automatic

AC2120)

per

track.

down

the

host.

to

maximum

drive.

head

SPECIFICATIONS

(122.091

Turning

sectors

when

specifying

Exceeding

and

the

cylinder.

the

park

operation.

for

the

disk

controller

system

Caviar

the

specified

parks

the

power

off

2.2.1

2.2.2

Physical

Height Length

Width

Weight

I

Weight

Dimensions

1.00

5.75

4.00

1.12

inch

(+0.02)

inches

(+0.02)

inches

(+0.02)

Pounds

(.508

grams)

Western Digital Corporation

7

Caviar AC160lAC2120 Technical Reference Manual

2.2.3

Mechanical Specifications

Figure

2·1

shows

the

Caviar

intelligent

.-------1.:-----1'

r

4.000

II

drive.

, ,

:'-1.000-":

, ,

,

1.200

,

-r--

t--------

--rJ-

I

__

mounting

---

,

--

I'

.250

dimensions

and

locations

I I

~!.--------4mo--------~.!

1

:.

0

o

6-32

.250

of

3.;

........

v

.......

lJNC.,2B

max.

deep

the

screw

holes

0

~i----I-"''''-''

.

2.375

for

the

8

Figure

2-1.

l

Caviar

AC160jAC2120

........

__

rooo01

I

o

..........

-L.

_____

II

...

Mounting

Western Digital Corporation

@

_______

~J

Dimensions

l

SPECIFICATIONS

2.3

2.3.1

2.3.2

ELECTRICAL SPECIFICATIONS

Nominal

Operating

Read Write Random Spin

Power

(No

media

Operating

Idle

Current

Mode

Seek

up

Requirements

12VDC±5%

.24 .24 .28 .60

.80 A Max.

Management -Drive

access/no

Mode

active

command)

12VDC±5%

.18A

Current

A A A A

Spinning

Current

and

Average

5VDC±5%

.35 A Max.

Average

5VDC±5%

Power

.30

A

.30

A .30A .30

A

.14A

Dissipation

Power.

Average

4.38W

4.86W

8.70W

Average

2.86W

NOTE:

IDLE -Power inactivity mode user saving exceed age usage

timer.

is

dependent

specified

can

occur

the

length

of

time

in

of

the

saving

The

via

the

if

the

of

this

mode

drive.

mode

entered

contribution

on

the

inactivity

drive

configuration

period(s)

the

inactivity

varies

depending

after

due

to

this

time

of

command

timer

expiration

power

interval

data.

interval.

No

inactivity

on

the

which

The

specific

of

the

saving

can

power

do

percent-

be

not

Western Digital Corporation 9

Caviar AC160lAC2120 Technical Reference Manual

Please

refer

to

management

context.

0.80

Section

l-

4.6

for

details

on

the

I

I-

A

M

P

S

0.60

0.40

0.20

-

J

Idle

mode

operation

in a power

2.3.3

2.3.4

I I I I I

1

2 3 4 5

Time

in

Current

Draw

Figure

0.00 r

2-2.

Typical + 12V

Power Management - Drive Not

Operating

Standby Sleep

Ripple

l2VDC 5VDC

Mode

l2VDC

.04 .04

Maximum

200

mV

(peak-to-peak)

100

mV

(peak-to-peak)

Current

A A

Average

seconds

During

Spin

Spinning

5VDC

.16A .16A

Frequency

0-20 0-20

Up

Power.

MHz MHz

(Master

Typical

1.28W

Mode)

10

Western Digital Corporation

SPECIFICATIONS

2.3.5

Power

Power Mating

Power

Connectors

Connector

Cable

Wire

Gauge

and

Cables

4-pin

MOlEX

Body

(AMP

Pins

(AMP

18

AWG

(PIN

15-24-4041

1-480424-0

60619-4

or

equivalent)

or

equivalent)

Western Digital Corporation 11

Caviar AC160lAC2120 Technical l1eference Manual

2.4

2.4.1

2.4.2

ENVmONMENTAL SPECIFICATIONS

Shock

Temperature

and

V"lbration

Shock

Operating Non-operating

Note:

Half-sine

maximum,

Vibration

Operating

Non-Operating

Sweep

Temperature

Operating

Non-Operating

Note:

Relative

Rate

The

system

the

castina

Humidity

10Gs 75Gs

wave

of

11

ms

duration,

with

no

non-recoverable.

5-17

Hz,

0.034"

17-400

Hz,

0.756

5-20

Hz,

0.195"

20-500

Hz,

4G

(Peak)

Half-octave/minute

and

Humidity

5°~to

5Q°C

10

C/hour

Max.

_40°C

to

60°C

20°C/hour

efNironment

temoerature

Max.

must at

(double

(Peak)

(double

Thermal Thermal

allow

or

below

two

half-sine

errors.

amplitude) amplitude)

Gradient Gradient

sufficient

~

c.

air

waves

flow

to

per

second

maintain

12

2.4.3

Operating

Maximum

Non-operating

Maximum

Atmospheric

Altitude -Operating Altitude -Non-Operating

Wet

Bulb

Wet

Bulb

Pressure

8%

to

2SoC 5%

to

2SoC

-1000

80%

RH

non-condensing

95%

RH

non-condensing

to

10,000

feet

to

40,000

feet

Western Digital Corporation

SPECIFICATIONS

2.4.4

2~5

Acoustics

Max.

sound

power

level

Idle

Mode

Seek

Mode

*

The

maximum

difference

between

AGENCY APPROVALS

The

Caviar

meets

the

standards

Underwriters

UL-Standard Equipment;

Federal

Verified 15,

Canadian

CSA-Standard Equipment;

laboratories

1950,

Standard

File

Number -E101559

Communication

to

comply

Subpart

Standards

File

Commission

with

B,

for

Class B Equipment

Association

C22.2,

Number

FCC

No.950 -MB9

LR

per

ISO

adjacent

of

the

for

Safety,

Rules

68850

7779.5

octave

following

Information

for

Radiated

Information

*

40

dBA

at 1 meter

43

dBA

at 1 meter

bands

is

regulatory

Processing

and

Conducted

Processing

12

db

(no

agencies:

and

Emission,

and

Business

pure

tones).

Business

Part

TUV

Essen

laboratories

IEC

950

(EN

Electrical

2.6

RELIABll..ITY SPECIFICATION

MTBF MTIR

Component

Warranty

Period

Western Digital Corporation

60

950)

Business

Design

Equipment

Life

Safety

of

Information

100,000 10

Minutes

Five

Years

Two

Years

Technology

Predicted

typical

Hours

Equipment

Including

13

Caviar

AC160lAC2120

Technical Reference Manual

14

Western Digital Corporation

PRINCIPLES OF OPERATION

3.0

PRINCIPLES

This

section

viewpoints:

•

Drive

•

Head

3~1

DRIVE ELECTRONICS

Caviar's the drive

intelligence

four-layer

electronic

•

WD42C22C

•

BufferRAM

•

WD60C11

•

WD10C23

•

Microprocessor

•

Pu

lse

•

Spindle

•

Actuator

•

Gate

•

Frequency

OF

OPERATION

describes

Electronics Disk

Assembly

resides

printed

detector

Array

circuit

components:

Winchester

Servo Data

Motor

Driver

Fusion

Synthesizer

the

principles

(HDA)

in

the

board

Disk

Controller Separator ROM

and

RAM

II

of

operation

specialized

assembly.

Controller

The

of

the

Caviar

electronic

Caviar

from

the

components

consists

mounted

of

the

following

on

following

3.1.1

3.1.2

WD42C22C

The

WD42C22C formatter/controller, manager decodes generator/checker connects controls drive

into a single,

data

to

the

buffer

controller.

ButTer RAM

A

32-KByte buffering buffers

(optional

sector

read/write

Western Digital Corporation

Winchester Disk

integrates a high

CRC/ECC

84-pin

to

and

from

calculates

host

system

RAM

and

6~KByte)

data

between

data

and

generator/checker,

QPFP

the

WD10C23

ECC

for

bus

via

handles

static

the

Caviar

ECC

information.

Controller

performance,

device.

the

The

the

data

internal

arbitration

RAM

and

low

host

interface

controller/formatter

data

separator.

field.

The

host

12

rnA

buffer

the

The

drivers.

between

enhances

AT

system

buffer

The

the

bus.

is

cost

Winchester

encodes

The

interface

buffer

host

interface

data

throughput

The

accessed

and

buffer

and

CRC/ECC

directly

manager

and

by

RAM

only

by

two

15

Caviar AC160lAC2120 Technical Reference Manual

3.1.3

3.1.4

3.1.5

channels, channels data

WD60CII

The servo embedded WD6DC11

WDIOC23

The and 12 with sends data clocked

each

having a separate

operate

paths.

simultaneously,

Servo

WD60C11

burst

provides

amplitudes. A servo

servo

control

also

provides

Data

WD10C23

the

megabits-per-second

phase,

clean

to

read

channel

frequency

digital

be

recorded

to

the

WD10C23.

handles

read

on

Microprocessor

15-bit

accepting

Controller

servo

discrimination,

burst

implementations,

spindle

motor

Separator

the

sensitive

circuitry

for

Zone

and

write

signals

the

drive.

ROM

and

read/write

at a rate

2.

Read

splice

to

the

WD42C22C.

Data

RAM

address

is a momentary usually

control.

of

15

data

noise.

to

and

read

and

write

track

address

poSitioned

signals

megabits-per-second

refers

to

The

WD1

0C23

The

WD1

from

the

byte-count

capture

servo

between

previously

removes

DCn

WD42C22C

register.

operations

and

pattern

the

for

written

the

conditions

The

from

two

measures

used

in

sectors.

WD42C22C

Zone 1 and

is

The

data,

noise

and

write

precisely

16

3.1.6

A

16-bit

microprocessor WD42C22C. information monitors microprocessor's writes

to microprocessor RAM. multi-segmented

Pulse

The

pulse preamplifier using

level compensates input

level

The

over

an

spindle

interrupt

the

Command

uses

Firmware

cache,

Detector

detector

on

the

qualifications

for

variations

to

the

pulse

controls

microprocessor

internal

and

actuator

Register

64

KBytes

controlling

resides

amplifies

flex

circuit.

of

qualification

and

multiplexed

activity

line.

The

WD42C22C

or

at

of

external

all

in

the

and

qualifies

Pulse differentiated in

head

circuitry.

coordinates receives

address/data

the

end

these

microprocessor

qualification

preamp

the

and

until

the

asserts

of

either a host

ROM

and

functions,

the

Rll-encoded

input

zero

output

in

Western Digital Corporation

activity

sends

2/8

ROM.

read

croSSings.

levels,

of

the

command

bus.

The

microprocessor

WD42C22C

the

interrupt

or

disk

KBytes

of

external

including

mode

presenting a constant

the

signals

is

An

HDA

and

the

or

status

asserts

when

transfer.

accomplished

AGC

the

host

The

static

adaptive

from

the

amplifier

In

write

mode, switches a

to a lower

write-to-read

the

circuitry

level

to a II

transition.

is

disabled.

ow

fast

PRINCIPLES OF OPERATION

The

AGC

gain

stage

input

impedance

settling

of

the

input

coupling

capacitors

during

3.1.7

-3.1.8

3.1.9

3.1.10

Spindle

A

three-phase

WD60C11

Motor

Servo

Actuator

The

actuator

of

the

voice

coil

H-bridge

Gate

This the

"expanded

address 48MHz are are

driver.

Array

IC

performs

VSU

devices

I/O'

space

oscillator provided provided

Frequency

Driver

spindle

motor

Controller.

driver

is

Driver

driver

provides

motor. A digitaI-to-analog

Fusion

the

to

devices.

to

provide

to

provide

as

the

sole

by

this

device

precision

II

memory

the

and

microprocessor.

The

design

additional

40/60%

clock

source

as

well.

I/O

Synthesizer

employed.

placement

converter

decode

This

uses a 74lS387

output

duty

cycle

for

the

The

of

the

functions

device

ports.

The

12

MHz

drive.

driver

read/write

in

the

WD60C11

necessary

also

latch

gate

and

The

DMA

is

controlled

heads

for

provides

in

the

array

also

16

MHz

and

IOCS16

by

the

by

means

controls

interface

for

expanded

clocks

this

control

divides

which

control

of of

I/O

a

The

AV91

04-14

IC

to

generate

one

at

12.5

MHz

clock

frequency

Western Digital Corporation

Frequency

the

and

to

maintain a fairly

clock

the

Synthesizer

for

other

the

data

separator.

at

15.375 uniform

uses

MHz.

the

bit

12

MHz

The

Caviar

The

firmware

density

clock

outputfrom drive

across

uses

selects

the

media.

the

two

the

Fusion

lones,

output

17

.....

~

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~

mmr

fd

HINTRQ RAM

~

IOCS18

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rn

HACT

i

HRESH

~

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WD42C22

AND

BUFFER

••••

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CONT.

RG -WG EARLY -lATE

WClK RDATA

18

MHz

t~o

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AV91

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SYNTHESIZER z

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RAW

HCLK2X

DATA

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m

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.

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DACOUT

A.

B. C POS

A.

B. C NEG

ABEMF

sy

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~-

PMMO

~

DETECTOR

ACTUATOR

DRIVER

SPINDLE

MOTOR A WIND DRIVER B WIND

~'2V

~

J5

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CONNECTORS

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~~

+5V

RWC

HDATA

HS1

HSO

RDX

RDY

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fd

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l

PRINCIPLES OF OPERATION

•

THIN

FI

DISK

SPACE~

Western Digital Corporation

Figure

3-2.

Mechanical

Exploded

View

FILTER

AC2120

19

Caviar AC160lAC2120 Technical Rl1ference Manual

3.2

3.2.1

BEAD

DISK

The

functional

cover.

The

assembly headstack clean

The

•

and

environment

HDA

consists

Base/Cover Spindle Disk

Headstack Voice Air

filtration

ASSEMBLY

parts

voice

of

motor

stack

assembly

coil

assembly

Base/Cover Assembly

The

single-piece assembly. spindle HDA, a tape

motor,

cast

The

base/cover

voice

seal

is

of

the

HDA provides coil

through

is

also

maintained

the

following

assembly

system

base

provides a mounting

assembly

coil

and

pivot.

wrapped

around

(BOA)

are

mounted

exact

mechanical

precise

mechanical

To

the

to a die-cast

relationships

machined

within

the

HDA

subassemblies;

platform

has

machined

ensure a Class

base

and

cover

housing

between

dimensions

enclosure.

for

mounting

100

castings.

on

the

components

environment

with a sealed

the

spindle,

the

housing.

surfaces

for

within

of

A

the the the

20

3.2.2

Spindle

The bearing spindle casting.

Proprietary monitoring sensing, lowers dynamically

Motor

spindle

assembly,

motor

The

the

instead

the

power

motor

spindle

brake

assembly

disk

assembly

motor

rotates

electronics

spindle

of

the

consumption

the

spindle

consists

mounting

is

motor's

Conventional

hub

completely

the

spindle

sense

back

Hall

and

during

motor

of a brush

and a ferrofluid

enclosed

shaft

motor

electromotive

effect

increases

less

three-phase

magnetic

in

the

HDA

at

approximately

speed

force

or

inductive

reliability.

spin

down.

and

angular

(BEMF).

motor

Motor

seal.

bolted

3600

position

Western Digital Corporation

motor,

The

to

the

RPM.

position

Using

sensors,

driver

spindle

entire

base

by

BEMF

circuits

PRINCIPLES OF OPERATION

3.2.3

3.2.4

Disk

Stack

The

disk

Caviar

AC2120,

place.

The

platters

plated

with a layer

of

carbon

the

read/write

between

Headstack

The

headstack

•

Read/write

•

Actuator

•

Flex

Assembly

stack

assembly

two

Caviar

of

the

overcoat

heads.

the

read/write

Assembly

assembly

arm

Circuit

disks

AC160

Caviar

of

nickel,

protects

heads

ReadlWrite Heads

Read/Write system.

heads

The

consist

Caviar

actuator

consists

and

one

has

one

drives

followed

the

The

final

heads

and

consists

ofthin

is

statically

of

disks,

spacer

disk

and a spacer.

are

thin

by

magnetic

lubricant

media

of

the

following

film

slider

balanced

disk

spacers

are

placed

inflexible

the

magnetic

material

layer

during

take-offs

mounted

and a disk

on

the

hub

aluminum

media

against

wear

provides

mechanical

on a Whitney

above

additional

and

the

pivot

clamp.

and

disks.

coating. A thin

and

abrasion

landings.

subassemblies:

class

center.

In

the

clamped

Each

suspension

into

disk

film

from

protection

is

3.2.5

Actuator

This

assembly

servo

Fkx

The

head

the

HDA.

and

the

maximizes

Voice Coil Assembly

The

voice

coil, a bidirectional

The

pivot

Arm

data

embedded

Circuit

conductors The

voice

the

coil

assembly

Western Digital Corporation

Assembly

is

servo-controlled

in

all

disk

are

flex

circuit

assembly

coil

actuator

read/write

assembly

consists

crash fits

in

heads'

stop

the

and

derives

tracks.

cables

routed

transfers

motor. A preamplifier

signal

of

an

upper

and a pivot

actuator

through

signals

strength

and

bearing.

block

bore.

position

while

lower

information

the

flex

circuit between IC,

located minimizing

magnetic

from

assembly

the

read/

on

the

noise.

plate, a flat

the

write

flex

sector

inside heads

circuit,

rotary

21

Caviar

AC160lAC2120

Technical

R~ference

Manual

3.2.6

Air

Filtration

It

is

absolutely

HDA

is

assembled

To

retain

this

the

recirculating particles recirculating This

forcing any and

which

strategic

air

through external external

System

essential

in a Class

clean

environment,

filter,

cleans

may

be

generated

filter

placement

the

recirculating

air

entering

air

pressure.

that

the

of

the

The

air

circulating

100

the

air

within

disk

the

filter

HDA.

breather

within

purified

during

places

air

environment,

Caviar

is

equipped

the

HDA.

head

landings

the

filter

allows

the

rotating

filter. A second

The

breather

filter

is

located

the

drive

with

The

recirculating

or

in

the

disks

filter,

filter

also

on

be

free

then

sealed

two

filters.

take-offs. direction

to

act

the

breather

equalizes

the

bottom

of

particles.

with

One

filter

traps

Mounting

of

the

as

an

filter,

the

of

the

The tape. filter,

any

the

air

flow.

air

pump

cleans

internal

HDA.

22

Western Digital Corporation

ADVANCED PRODUCT FEATURES

4.0

ADVANCED PRODUCT FEATURES

Western capacities features.

4.1 CACHEFLOW

CacheFlow

4.1.1

Purpose

Digital's

•

CacheFlow

•

Defect

•

Error

•

Translation

•

Dual

•

Power

•

DMA

•

Zoned

•

BlockMode

Caviar

for

the

AT

This

section

management

recovery

drive

option

Conservation

Capability

Recording

is

the

industry's

of

CacheFiow

series

and

compatibles

describes

and

process

first

of

intelligent

the

following

format

adaptive

drives

provides a choice

with a full

characteristics

complement

Caviar

multi-segmented

advanced

of

disk

caching

of

data

advanced

product

features:

system.

storage product

4.1.2

CacheFlow and not

only the partitions selects

Benefits

In a typical adaptive operations been other similar

was

the

overhead

the

size

application

the

appropriate

of

application,

design

by

analyzed.

hand,

request

performance

Western Digital Corporation

designed

due

to

rotational

of

the

data

is

sequential.

Caviar's

32-KByte

caching

CacheFiow

most

enables

immediately

Applications

the

same

edge

by

Western

request

random

host

the

implementing

such

switching

Digital

latency

but

or (optional mode

for

requests

Caviar

as

Core

data

over

to

minimize

delays.

the

type

repetitive.

64-KByte)

optimum

are

for

to

eliminate

the

Sequential

Test

or

and

over

the

Repetitive

disk

CacheFIow

of

data

request,

CacheFIow

RAM

buffer

system

other

performance.

sequential

unnecessary

mode

benchmark

again.

CacheFlow

mode

seeking

constantly

into

data.

once

of

operations

that

is,

then

dynamically

segments

CacheFlow's

disk

the

utilities,

provides

operation.

evaluates

whether

and

seeking

data

has

on

the

a

23

Caviar AC160lAC2120 Technical Reference Manual

4.1.3

4.1.4

CacheFiow

Sequential pa

rtitions

As

seeking

and

sector

either

increase

CacheFlow operations host-requested the

cache

CacheFlow operation Only

the

Operation

mode

is

the

32-KByte

operations

count

parameters.

or

switches

if

the

same

data

hit

score

transfers

does

not

sectors

that

the

decrease

has

can

affect

Sequential Mode

The

Sequential

of

the

host-requested

until

the

new

cache

host.

Based

size

of

segments

Caching

cache

is

beginning

on

the

full.

hit

to

optimize

default

mode

(optional

begin.

Cache

CacheFlow

the

from

Sequential

block

is

been

read.

be

significantly

host

write

the

buffer's

are

written

Mode

is

data

into

After

the

is

established score

algorithm.

segment

of

operation

64-KByte)

Flow

segment

accessed

By

storing

improved.

data

immediately

cache

are

purged

the

standard

the

segment(s).

host

reads

following

performance.

for

cache

buffer

monitors

then

size

Mode

twice.

segments

sequential

the

uses a simple

for

optimal

to

Repetitive

Both

read-ahead

from

the

read-ahead

Cache

the

requested

the

last

Cache

Flow.

into

four

data's

logica I sector

performance.

modes

data

to

the

sector

since

write

«;ache

buffer.

cache.

Flow

continues

data

sector

buffer

mode

adapts

The

Caviar

caching

hit

score

algorithm

Mode

during

read

ahead

in

the

sector

buffer. A write

data

is

not

After

to

read

from

the

returned

the

number

initially

segments.

address

to

read

after

the

buffers.

cached.

reading

all

ahead

cache.

to

the

and

a

24

4.1.5

The

default larger not

store

effectiveness

mode

number

enough

for

of

four

of

segments

sequential

random

Repetitive Mode

The

Repetitive accessed and

can

maximum

the

host-requested

Caching

twice.

the

override

hit

score.

Repetitive

the

Unlike

data

cache

segments

may

limit

sectors. A smaller

reads.

Mode

resembles a static

Mode

number

of

segments

Sequentia I Mode.

remains

valid

provides

cache

effectiveness

is

selected.

after

the

optimum

number

buffer.

Repetitive

to

build

however.

host

because

one

the

reads

cache

of

segments

If

the

Mode

large

segment sector the

data.

performance.

the

segment

same also

reads

buffer

may

limit

blocks

ahead

with

containing

are the

Western Digital Corporation

A

ADVANCED PRODUCT FEATURES

SequenIlaI

Mode Selected

(Defau. Mode)

•

Read

Host·RequesIed

Dara

•

MonItor

SectorAdd..-

and

Sector

Count

Pararnal8lS

1

HilScare

AIgorIIhm

I

Read Ahead

and Partition

New

Segments

Host

Daraand

E"lItIes

Reads

BuffelS

!

..

Sequential

Mode

Selacted

II

Same

Blocks

Acc:essed

Twice?

Read and

Pan~ion

New

Segments

Ahead

t

•

Figure

4-1.

CacheFlow

RepeIftIve

Mode

SeIecIed

Algorithm

r-+

Host

Daraand

Data

Reads

Retained

Western Digital Corporation

25

Caviar AC160lAC2120 Technical

R~terence

Manual

4.2

4.2.1

4.2.2

DEFECT MANAGEMENT AND FORMAT

CEUUlACT~Sl1CS

Defect

Every and manufacturing The

of

tracks

Format

The mapped

In programs, command, host's

the

Management

Caviar

maps

list

contains

the

spare

after

Caviar

out.

order

to

be

the

interleave

sector

tolfrom

undergoes

out

facility.

sector/track

they

factory-level

defective

Following

the

cylinder,

have

been

sectors

head

map

assigned.

Characteristics

is

shipped

compatible

Caviar

from

the

with

supports

performs a logical

table

request

an

alternate

on

the

and

is

to

manage

factory

existing

logical

format.

for

good

sector.

intelligent

the

media

factory

tests, a primary

sector

numbers

the

preformatted

industry

When

version

and

bad

standard

bum

in,

which

before

for

all

reallocation

(low

defect

the

host

of

this

command

sector

marking

the

level)

issues

thoroughly

drive

leaves

defect

list

is

defects.

of

The

spare

sectors

with

all

management

the

Format

in

response

or

assign/unassign

tests

for

the

created.

purpose

and

defects

utility

Track

to

the

26

If

the

host

data

fields interleave must

contain

for

each

entry

The

first

byte

sector

or

to

an

alternate

issues

of

the

table

identifies

an

appropriate

in

the

is

set

20H

to

location.

the

Format

specified

interleave

to

OOH

unassign

The

Track

Command

track

are

any

bad

sectors

number

to

the

second

of

table.

The

indicate a good

alternate

byte

during

filled

with a data

on a given

data

bytes.

first

byte

sector

designates

normal

There

marks

or

to

the

operating

pattern

track.

are

the

sector

or

to

SOH

40H

to

logical

of a II

The

interleave

two

bytes

as

to

indicate a bad

assign

sector

Western Digital Corporation

modes,

zeros.

per

good

the

sector

ID

number.

the

The

table

sector

or

bad.

to

ADVANCED

PRODUCT

FEATURES

4.3

ERROR

The

Caviar

•

Read/Write

•

Extended

The

Caviar's

•

10

•

Data

•

Error

The

host Commands. operations Caviar

will

the

appropriate

The

Read/Write succeed continues

validate

Caviar'S

RECOVERY

has

two

means

Retry

Procedure

Read

Retry

retry

procedures

Not

Found

(lDNF) Address Correction

may

All

are

not

in

reading

executing

the

10

Error

Register

Mark

Code

explicitly

always

perform

bit

fields

enable/disable

other

commands

performed

any

in

the

Error

Retry

Procedure

or

writing a specified

the

command.

on a specified

and

of

error

recovery:

Procedure

are

implemented

Not

Found

(ECC)

and

with

disk

controller

Register.

will

the

command

for

(DAMNF)

retries

in

the

controller's

retries

enabled.

retry

operations

perform

For a write

track,

up

sector.

then

is

terminated.

the

following

the

Read,

internal

If

retries

and

to

ten

basic

If

recovery

operation,

an

IDNF

errors:

Write

disk

will

retry

is

achieved,

if

these

error

is

and

Read

Verify

read

and

write

are

disabled,

immediately

operations

the

Caviar

retries

fail

reported

to

the

set

to to

the

For a read recover combinations recover the offset reports In

the consecutive spans status are (uncorrectable)

the

read

retry

before

the

case eleven

register

not

found,

operation,

data.

operation

appropriate

of

matching

Western Digital Corporation

the

The

of

early/late

This

is

successfu

continuing

error

an

ECC

error,

syndromes.

bits

or

less,

and

the

command

or

if

the

error

to

the

Caviar

will

Extended

window

procedure

I.

the

with

the

command.

to

the

Error

the

drive

the

data

continues.

spans

more

Error

Register.

perform

Read

Retry

shifts

is

used

Caviar

Register,

performs

If

matching

is

corrected,

than

the

Extended

Procedure

and

positive/negative

for

the

IDNF,

clears

any

existing

If

the

retry

with

the

up

to

eight

syndromes

the

CORR

If

two

consecutive

eleven

bits,

Read

Retry

employs

DAMNF

operation

and

window

exception

retries

are

found,

bit

is

matching

the

Caviar

Procedure

up

track

ECC

shift

failed,

of

an

to

obtain

and

set

in

syndromes

reports

to

sixteen

offsets

errors.

or

track

the

Caviar

ECC

error.

the

error

the

host's

an

to to

If

two

ECC

27

Caviar AC160lAC2120 Technical Reference Manual

4.4

TRANSLATION

The

Caviar

implements translated command universal can than must The 122,091

The

any

Sectors/Track

Heads Cylinders/drive

The

Per

will setup

drive

to

issue

translation,

be

assigned

the

physical

be

equal

to

maximum

minimum

translation

values

Track

always

parameters.

and

244,182

value

in

the

(SPT)

be

number

configurations

head

to

the

limits.

or

less

parameter

Sector

and

heads.

in

the

linear

address

and

sector/track

therefore,

drive,

as

The

product

than

the

of

sectors

respectively.

for

any

translation

is

as

follows:

255 16 2048

Count

Register

Regardless

translation

translation.

are

selected

counts

any

valid

long

as

the

of

the

maximum

per

drive

for

Each

sector

parameter

and

of

the

mode.

Refer

The

by

using

the

to

the

translator.

combination

total

number

cylinder,

number

the

values

of

the

Caviar

consists

is

SDH

of

to

section

head

sectors

AC160

one.

Register

the

translation

Set

of

cylinder,

of

sectors

and

sectors/track

available

and

of

512

bytes.

The

maximum

determine

SPT

and

2.2

for

the

mode

Drive

Parameters

Caviar

supports

head

and

is

not

greater

counts

to

the

user.

the

AC2120

value

the

Sectors

the

heads,

Caviar

recommended

and

SPT

are

for

28

4.5

DUAL

The

Caviar

for

master

area

implemented

described The

SOH

signal

I/O

interface.

the

master reset. completion Caviar the

slave

DRIVE

or

for

both

in

Register

is a time-rnultiplexed

DASP

will

bit

OPTION

supports

slave

drive

master

by

means

section

contains

At

reset,

drive,

showing

is

asserted

of

the

command.

not

respond

is

selected

ATA

dual

designation. A jumper

and

of

6.

this

atthe

to

in

drive

operations

slave

configurations.

a

daisy-chain

the

master/slave indicator signal

that a slave

commands

the

of

is

an

beginning

If

the

master

or

SDH

Register.

by

means

of

configuration

must

be

placed

in

the

drive's

cable

assembly.

select

Drive

Active

output

from

drive

is

of

command

drive

shaw

Connection

bit

or

Slave

the

present.

processing

option

drive

status

These

for slave

For

has

to

the

configurations

the

Caviar.

Present

on

drive

and

all

times

and

been

configured,

the

interface

on

released

Western Digital Corporation

options host

The

the

Caviar's

an

input

other

option

is

are

DASP

to

than

upon

the

when

ADVANCED PRODUCT FEATURES

4.6

POWER

Power

saving

when

the completes computer.

by

commanding

set

includes

are

used

Idle

mode

is

specified seconds command disabled Idle

state

regain

servo

CONSERVATION

takes

two

forms.

One

drive

is

idle.

The

idle

state command The

the

to

initiate

is

entered in

and

specifies

until

by

modifying

requires a time

control.

execution

other

form

the

drive

industry

the

upon

the

drive

the

Idle

the

and

is

host

computer

to

park

the

standard

park

and

spin

an

inactivity

configuration

elapsed

mode

configuration

about

time

becomes

equal

is

Automatic

is

entered

another heads

and

ATA

command

down

timer

sector.

(in

seconds)

active.

sector

control

to

one

Power

automatica

command

controlled

stop

the

set

functions.

time

out.

The

timer

from

Entry

parameters.

long

seek

Reduction

Ily

is

not

received

power

saving

spindle.

power

save

The

inactivity is

typically

the

completion

to

APR

time

to

(APR)

that

whenever

from

that

is

The

drive

command

commands

timer

set

of

Idle

mode

Recovery

allow

the

occurs

the

drive

the

host

realized

that

interval

to

two

the

last

may

be

from

the

driv~

to

Western Digital Corporation

29

Caviar AC160lAC2120 Technical Reference Manual

4.7

4.8

DMA

By

engaging increased high

speed

peripheral With

the

and

Write

must

DMA basis.

BLOCK MODE

Block transfers on

Iy

one sector between multiple

ATA

in

two

DMA

data

exception

DMA

be

performed

or

PIO

data

mode

data

because

hardware

of

data.

the

sectors

compatible

ways.

channel.

transfer

command,

transfer

transfers

multiple

interrupt.

The

host

and

of

First,

burden

of

DMA

using

PIO. mode

are

reduced

the

data.

EISA

type B DMA,

throughput

Second,

data

all

sectors

Standard system Caviar

the

is

off-loaded

transfers,

commands,

selection

faster

than

of

overhead

drive

is

increased

CPU

bandwidth

to

which

including

is

performed

standard

data

are

PIO

transfers

translates

for

applications

the

system's

the

system's

are

limited

on a command-by-command

Programmable

transferreq

generate

performance

through

is

increased

DMA

to a single

Read

Long

with

an

into

faster

requiring

use

of

the

controller.

and

Input

the

occurence

interrupt

data

the

because

Read

Write

Output

throughput

transfer

level

is

system's

the

DMA Long,

(PIO)

of

for

every

of

30

4.9

Before

the

first

block

mode

Read

can

be

issued

to

the

drive,

the

number

and

for a Caviar

with

Write

64

KBytes

of

sectors

Multiple

drive

with

of

buffer

per

block

commands. A maximum

32

KBytes

RAM.

ZONED RECORDING

Zoned

Recording increasing Track

capacity

is

increased

number

on The

track.

the

disk

AC160

of

the

new

surface

is a mechanism number (number

when

and

of

the

sectors.

creates a series

AC2120

data

sectors

of

sectors)

tracks

This

incremental

drives

Multiple

Set

Multiple

that

are

of

buffer

for

is

consistent

are

sufficiently

of

concentric

have

(C4H)

or

Write

Multiple

(CSH)

to

be

transferred

RAM

increasing

written

increase

two

zones

command

of

eight

and

16

the

on

the

longer

with

in

long

to

in

track

zones

containing

must

during

future sectors sectors

groups

with

per

block

per

block

capacity

outer

tracks

of

tracks

accommodate a significant

capacity

different

48

and

Western Digital Corporation

(C5H)

command

be

issued

Read

can

for a Caviar

of

the

of

the

or

zones

moving

data

densities.

40

sectors

to

set

Multiple

be

set

drive

by

drive.

and

outward

per

HOST

INTERFACE AND

AT

COMMAND

SET

5.0

HOST INTERFACE AND

This

5.1

section

•

J2 PIN

The

Caviar

in

Figure

corresponding

describes:

J2

assignments

Host

Interface

Host

interface

Host

interface Caviar Caviar Error

reporting DMA

read

DMA

write

registers commands

Electrical read

write

timing

ASSIGNMENTS

interfaces

5-1.

Table

signal

with

the

5-1

identifies

names

host

and

Specification

signal

AT

COMMAND SET

I/O

bus

via

the

4O-pin

connector

the

numbers

of

the

functions.

J2

connector

(J2)

illustrated

and

the

39

1

••••••••••••••••••••

••••••••••

40 2

o

Empty

boxes

J2

20

of

Note:

keyed

pins

For

Row

connector

5-1.

Western Digital Corporation

represent

removed

Figure

Caviar

J2 J8 J3

4 3 2 1

1

t'

Connectors

position

0

•••••••••

removed

pins.

to

separate

J2

from

J8

5-1.

Standard

AC160/AC2120

J3

is

rotated

drives

180 0 from

531

1

0

•••

0

•••

642

Factory

manufactured

the

••

~

before

shown

L+12V

4/1/92, in

Figure

GND

+5V

31

Caviar AC160lAC2120 Technical Reference Manual

Number

1

3,5,7,9, 11,13,15,

17

4,6,8,10, 12,

14,

16,

18

2,

19,22,

24,26,30,

40

20 21

Mnemonic

-

RST

HD7-0

HD8-15

GND

DMARQ

Signal

--

Reset

Host Bits

Host

Ground

DMARequest

Data

7-0

Data

Name

Bus

110

I

I/O

I

0

Function

Initializes asserted.

The

tristate, 8 bit,

tional

bus

status

and

tion

between

the

Caviar.

The

upper

Bus

Bits

fer

only

transferl.

Key-Not Drive

to

connected.

DMA

host.

the

Caviar

for

control

the

data

during

8-15

(16-bit

signal

when

bidirec-

transferring

informa-

host

and

bus

is

used

data

trans-

data

Request

32

27 29

23

25

RESERVED DMACK

-

lOW

-

lOR

Table

DMA Acknowledge

---

I/O

Write

---

I/O

Read

5-1.

J2

Descriptions

I

Host

DMA

I

signal Model

The

host

lOW

when a data

byte

is

The

host

lOR

when a data

byte

is

Acknowledge

to

drive.

controller

written

controller

read

from

to

(ATA

asserts

or

control

the

Cavia

asserts

or

status

the

Caviar.

DMA

r.

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

Number

31

32

35,33,36

34

37

38

39

Mnemonic

INTRO

I/OCS16

HAO-2

PDlAG

--

HCSO

--

HCS1

--

DASP

Signal

Interrupt Request

I/O Select

Host Bus

Passed Diagnostics

--

Host Select

Host

---

Select

--

Drive Act/Slave Present

Name

Channel

16

Address

e!!jp

0

Chip

1

I/O

The

0

to

request

from

Identifies

0

or

from

wide. AD,

I

ports 0 through Output

I/O

when

nostics.

drive. The

I

dress with

channel.

The

I

dress with

registers.

This

I/O

a

time dicating slave signal slave the that a slave

For reset

serted

slave mand

Function

Caviar

asserts

interrupt

the

host.

data

the

host

A1

and

A2

from

it

has

passed

Input

host

asserts

and

communicate

the

Caviar

host

asserts

and

communicate

the

Caviar

open

collector

multiplexed

drive

present.

is

an

output

drive

and

master

all

drive,

drive

times

DASP

should

by

the

drives

execution.

INTRO

service

transfers

as

16

address

7.

slave

its

to

master

-

eso

to

on

the

-

CS1

to

auxiliary

output

signal

active

At

reset.

from

an

input

showing

is

present.

other

be

master

during

to

bits

I/O

drive

diag-

ad-

I/O

ad-

is

in-

or

this

the

to

than

as-

and

com-

Western Digital Corporation

Table

5-1.

J2

Descriptions

(cont.)

33

Caviar AC160lAC2120 Technical Reference Manual

5.2

5.2.1

HOST INTERFACE REGISTERS

Register Address Map

This

Task

File

occupies

registers

Caviar. bits Alternate

eso

All

wide.

-

eS1

pass

command,

registers

These

Status

0 1 0 1 0 0 1 0 1 0 1 0

1

0 1 1

0 0

1 1

1 1 1 1 1 1 1

0 0

the

are

eight

registers

Register

HAZ

HA1

0

0 0

1

1 1

address

status

and

bits

are

accessed

is

always

HAD

0

1

1 1

0 0 0

1

space

shown

data

information

wide,

except

via

control

accessible

Read

Data

0

Error Sector

0

Sector Cylinder

1

Cylinder

0

SOH Status

AlternateStatus

0

Oigitallnput

1

in

table

for

the

lines

with

CSl

Registers

Function

Count Number

Low High

5,.2.

The

between

Data

Register

HAD-

2,

active.

Write

Data

Sector Sector CylinderLow CylinderHigh SOH Command

Fixed

Task

File's

the

host

and

which

CSD

active.

Function

Count Number

OiskControl

ten the

is

16

The

34

5.2.2

Data Register

The

Data

Register

and

write

commands.

for

the

ECC

bytes

bits

wide.

Table

holds

all

the

All

data

transferred

5-2.

data

transfers

during

Task

to

be

read

File

Map

transferred

are

high

long

or

speed

write

to

or

from

and

16

long

commands

the

bits

host

wide,

which

on

Western Digital Corporation

read

except

are

8

HOST

INTERFACE

AND

AT

COMMAND

SET

5.2.3

Error

The The The cases Register's

If

drive's the when

Register

Error

Register register only

01 = No 02 = Not 03 = Buffer 04 = WD42C22C 05 = Microprocessor 8X = Slave

a

slave

SHD

7

BBD

contains a valid

exceptions

the

Error

Register

error

applicable

drive

is

status

bits.

Register.

asserted.

6 5

ECC

bit.

RAM

drive

present

contains

are

power-up contents

These

two

error

register

internal

failed

and

To

read

the

In

all

other

0

an

error

code

and

are

exceptions

error

RAM

has

failed

slave's

cases

Bit

4

IDNF

code

that

only

issuance

va

lid

regardless

cause

error

its

diagnostic,

error

code,

the

Error

Positions

3 0

indicates a particular

if

the

Status

Register

of

a

the

or

ROM

the

Register

2

AC

diagnostic

of

following

checksum

BOH

host

the

condition

is

ORed

should

bits

are

1 0

TKO

command. error

type

error

of

values:

error

with

select

defined

DAMNF

of

failure.

bit 0 is

In

these

the

Status

the

master

the 0 bit

as

follows

set.

in

BBD ECC IDNF AC

TKO

DAMNF

Western Digital Corporation

Bad

Block

Detected

Error

Correction

10

Not

Found

(target Aborted Track 0 (unable

Data

Command

Address

Mark

Code

(uncorrectable

sector

to

find a valid

Not

Found

could

track

not

0)

error

be

found)

detected)

35

Caviar AC160lAC212 0 Technical Reference Manual

Error

Register

If

bit 7 is

sector

10

Error

Register

If

bit 6 is

while

reading a target

Error

Register

Not

used.

Error

Register

If

bit 4 is

for

the

specified

Error

Register

Not

used.

Error

Register

If

bit 2 is

This

is

due

Bit 7 (BBD)

asserted,

field

while

Bit 6 (ECC)

asserted,

Bit

Bit 4 (lDNF)

asserted,

logical

Bit

Bit 2 (AC)

asserted,

to

the

it

following:

it

indicates

that

attempting a read

it

indicated

thatthe

sector.

5

it

indicates

that

address.

3

indicates

that

the

Caviar

or

write.

Caviar

has

detected

detected a Bad

an

uncorrectable

was

unable

to

terminated

Block

Mark

locate a valid

the

current

command.

in

data

10

the

error

field

36

Illegal

No

seek

Drive

not

Invalid

Error

Register

If

bit 1 is

asserted,

indication.

Error

Register

If

bit 0 is

asserted,

Address

Mark

write

current

complete

ready

condition

command

This

(DAM)

code

Bit 1 (TKO)

it

indicates

bit

is

only

Bit 0 (DAMNF)

it

indicates

within a given

condition

valid

(write

that

the

after a Recalibrate

that

the number

fault)

Caviar

was

unable

to

locate a valid

command.

Caviar

was

unable

to

locate a valid

of

byte

times

after

the

10

field.

Western Digital Corporation

track

Data

0

HOST

INTERFACE

AND

AT

COMMAND

SET

5.2.4

5.2.5

Write

The the contents

Sector

The a During a format

(SPT)

command. any. Register

Precompensation

Write

Precompensation

Caviar

automatically

of

this

Count

Sector

Count

read.

write

or

and

must

When

that

were

not

contents

Read

Sector Standby Write Idle Format Read

Set

Read

Write Set

Read

Power

Sector

Power

Track

Verify

Drive

Parameters

Multiple

DMA

determines

register

are

Register

verify

operation.

correspond

read

are

Mode

Write

indicates

operation

with

by

the

or

written

used

by

Mode

DMA

Register

only

used

the

(A

value

this

register the

values

host.

this

during

the

following

is

ignored

the

by

the

number

of

contains

register

the

during

normal

proper

write

Set

Buffer

Mode

of

sectors

zero

indicates a count

the

number

indicated

by

indicates

command.

write

operations

precompensation.

Command.

to

be

transferred

of

256

sectors).

of

the

sectors

Set

Drive

number

The

per

Parameters

of

sectors.

Sector

since

The

during

track

if

Count

5.2.6

Sector

The

written

commands:

Number

Sector

Number

to

by

Read

Sector

Write

Sector

Read

Verify

Read

Multiple

Write

Multiple ReadDMA WriteDMA

Western Digital Corporation

the

Register

host.

The

defines

contents

the

target

of

this

sector

for

register

the

are

current

used

by

operation

the

when

following

37

Caviar AC160 IAC212 0 Technical Reference Manual

5.2.7

Cylinder Low And Cylinder High Registers

The

Cylinder

for

commands register document). starting bits

of

7

lSB

0 0 0

The

contents

following

Seek Read Write Format Read Read Write Read

Write

low

and

Cylinder

that

require

for

extended

The

cylinder

the

starting

6

LSB LSB LSB

commands:

Sector

Track

Verify

Multiple

DMA

Cylinder

number.

cylinder

of

the

commands

5

Cylinder

High

an

address.

(extended

low

Register

The

Cylinder

number.

4

0

low

Registers

These

contains

High

Bit

Positions

3

LSB

0

and

Cylinder

contain

registers

commands

Register

also are

the

contains

2 1

LSB

MSB MSB

High

the

eight

logical serve a 16-bit

beyond

low-order

the

LSB

Registers

cylinder

command

the

scope

bits

three

high-order

0

LSB

MSB

are

used

address

of

this

of

the

by

the

38

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.2.8

SDH Register

The

SOH

Register

bit

assignments

7 1

SS1-SS0

0

HS3-HSO

SS1

and

sector

size

When

the 0 bit logical commands:

head

Recalibrate Seek Read Write Format Read Set

Drive

Identify

are

6

SS1

Sector Drive logical

SSO

(sector

at

512

is

number.

Sector

Track

Verify

Parameters

Drive

selects

as

follows:

5 4

SSO

Size

Select

Head

size)

bytes

per

reset.

The

the

(512

Bit

Select

are

sector.

the

master

contents

drive

and

Bit

0

byte) = 01

Bits

set

to 0 and

When

drive

head

number

Positions

3

HS3

1.

respectively.

the 0 bit

is

selected.

of

this

register

Read

Multiple

Write

Multiple

Set

Multiple

Read

Buffer

Write

Buffer

Set

Buffer ReadOMA WriteOMA

for a particular

2 1

is

set.

the

HS3-HSO

are

Mode

HS1

HS2

This

slave

specify

used

operation.

0

HSO

setting drive

by

is

the

following

fixes

selected.

The

the

desired

Western Digital Corporation

39

Caviar AC160lAC2120 Technical Reference Manual

5.2.9

Status Register

The

Status

Register

Status

Register

7

BSY BSY

ROY WF

SC ORO CORR lOX ERR

Status

Bit 7

This

bit

reflects

and

it

is

task

file

receiving

resets

6 5

ROY

BuSY,

Ready, Write requested Seek Data Data

Index, Unrecoverable

(BSY)

the deactivated register

the

other

contents

contains

WF

indicates

Fault,

Complete Request Was

index

state

at

the

any

pending

state

indicates

command

Corrected

pulse

error

of

the

command

than

the

of

the

Status

drive's

interrupt.

Bit

Positions

4

SC

state

ORO

of

controller

of

target

hazardous

of

target

controller.

completion.

Status

Register

Register.

status

following a command.

These

are

the

CORR

drive

condition

It

is

activated An

2 1

and

with a command

attempt

while

BSY

3

drive

bit

assignments:

lOX

aborts

by

the

= 1

ERR

host

results

Reading

0

the

to

read

in

the

request,

any

the

host

40

Status

Bit &

This

bit

reflects

o

is

not

honored.

the

command

Status

Bit 5

This

bit

indicates of a write command

Status

When

Status

This

bit

Bit 4

set,

Bit 3

is

fa

requests

this

high

(RDY)

the

If a

is

aborted.

(WF)

the

u It

condition

(SC)

bit

(DRQ)

when

state

of

the

command

occurrence

causes

are

not

honored

indicates

data

is

to

target

request

of

a

the

current

the

last

be

transmitted

drive.

Any

is

executed

write

fault

command

until

the

condition

requested

between

Western Digital Corporation

command

and,

at

the

target

request

clears.

seek

has

the

requested

if

ROY

drive.

to

been

completed.

host

and

while

becomes

The

presence

abort.

Subsequent

target

controller.

ROY

=

inactive,

HOST

INTERFACE

AND

AT

COMMAND

SET

5.2.10

5.2.11

5.2.12

Status

When a

Status

This

Status

When may

Bit2

this

bit

correctable

Bit 1

bit

reflects

Bit 0

this

bit

ascertain

Command

The

host

requests a controller/drive

Command

Register.

Alternate

The

Alternate

pending

Fixed

interrupt,

Disk

(CORR)

is

set.

it

error

in

the

(DX)

the

target

(ERR)

is

set.

it

the

type

Register

The

Status

as

the

Control

indicates

data

field

drive's

indicates

of

error

write

action

Register

provides

Status

Register

that

one

which

index

that

an

by

reading

function

sets

Register

or

more

of

the

was

corrected

pulse.

unrecoverable

the

Error

the

BSY

the

same

at a different

error

Register.

by

writing a function

bit

in

information,

address.

sectors

via

the

has

the

Status

sent

to

the

ECC

algorithm.

occurred.

code

Register.

without

resetting

host

The

in

had

host

the

a

The

Fixed

Disk

provides

Bit2(RST)

The as

microseconds,

In signal completing for

the

ability

7 0 0 0 0 0

software-controlled

long

dual

the

6

as

it

drive

configurations,

and

asserts

its

slave

drive

Western Digital Corporation

Control

is

active

then

PDIAG

reset

to

Register

to

enable

5

reset

(high).

off,

to

complete

after

routines

assert

allows

or

disable

Bit

4

bit

(RST)

This

bit

the

slave

completing

and

before

PDlAG.

for a programmable

control

Positions

maintains

must

drive

negating

3

reset

function.

negates

its

reset

of

the

2 1

RST

the

be

turned

PDIAG

routines.

BSY.

fixed

waits

controller

disk

priority

0

IDS

disk

on

for a minimum

upon

The

up

0

in a reset

receiving

master

to

100

reset

and

interrupt.

condition

of

5.0

the

reset

drive,

after

milliseconds

41

Caviar AC160lAC2120 Technical Reference Manual

Bit 1

(IDS)

The

interrupt controller Disabling interrupts

disable

interrupts.

interrupts

are

re-enabled.

control Disabling

also

tristates

Interrupts

bit

an the

(IDS)

is

interrupt

INTRQ

are

used

line. A pending

disabled

to

disable

does

not

following a system

(high)

clear a pending

interrupt

or

enable

interrupt.

executes

master

(low)

once

reset.

5.2.13

Digital Input Register

The

Digital

Input

the

fixed

option

on

7

DCG DCG

WTG HS3 -HSO DS2 -DS1

disk

drive's

the

adapter

6 5

WTG

Diskette Write Drive Drive

Register

reflects

select,

board

HS3 HS2

Change

Gate

On

Head

Select

head is

not

4

Flag

(binary)

the

current

select

and

installed,

Bit

Positions

3

HS1

state

of

the

write

gate

signals.

bit 7 remains

2

HSO

DS2

floppy

change

If

tristated.

1

DS1

the

0

flag

floppy

and

disk

42

Western Digital Corporation

HOST

INTERFACE

AND

AT

5.3 CAVIAR AC160/AC2120 COMMANDS

Table

5-3

lists

the

binary

and

supported

by

Western

Digital's

hexadecimal

Caviar

intelligent

codes

drives.

specific

COMMAND

to

each

command

SET

Command

Recalibrate

Seek

Read

Write Format

Read

Execute

Set

Track

Verify

Diagnostic

Drive

Parameters

WriteDMA Read

DMA

Read

Multiple

Write

Multiple

Set

Multiple Standby Idle

Immediate

Standby

.

Idle Read

Buffer

Check

Power

Sleep

Write

Buffer Identify Set

Drive

Buffer

Mode

CD

:::I:

xu

CD

"'C

0

Q.

7

0

lX 7X

2X

3X

50 4X 90

91

CA

C8

C4

C5 C6

EO

El

E2

E3

E4 E5 E6 E8 EC EF

6

0 0 0

1 1 1 X X X X

0 0 0 0 0

1

0

1

0

1

0 0

1

0 0

1

1 1 1 1 1 1 1

1 1 1

1 1 1 1 1 1 0 0 1 1 1

1

1 1

1 1 1

1 1 1 1 1 1

1

1 1 1

Binary 5

Opcode

4

3

1 X X X X

1

0

0 0

1 1 0

1

0

0 0 0 0

0 0 0 0 0

0

1 1

0 0

0 0 0

1

0

1

0 0 0 0 0 0 0 0

0 1 1 0

0 0 0 0 0 0 0 0 0

0

0 0 0 1 0

1

0 0 0

1

1 1 1 1

1

0 0

0 0 0 0 0

0

2

0

1 1

1

0

R

L L R

R 0

1

1 0

0

1

0

1

0

1 0

0

1

0

1

0

L -

Long

Mode

R -

Retry

bit o =

X =

Don't

care

Western Digital Corporation

bit o =

1 = 1 =

Table

5-3.

Normal Long

Error Error

mode,

mode retries

retries

Standard

normal

and

ECC

disabled

Command

Opcodes

ECC

functions

enabled

43

Caviar

AC160lAC2120

To

initiate a controller

to

the

task validates function.

Technical Reference Manual

file

the

contents

The

Caviar

and

writes

commands

operation,

of

the

command

the

task

are

the

file

briefly

host

first

to

registers

defined

the

transfers

Command

and

in

the

Register.

then

the

following

pertinent

The

performs

subsections.

information

controller

the

desired

5.3.1

Recalihrate

The

Recalibrate

anywhere

drive assertion setting TKO

The any read/cache

Register

Command SOH Write

Sector Sector Cylinder Cylinder

on

the

asserts

bit

Recalibrate

segment

BSYand

of

SEEK

INTRO.

are

asserted

associated

segment.

Precomp

Count Number

low High

(1m)

Command

disk

COMPLETE

If

the

Command

causes

to

cylinder

issues a seek

read/Write

in

the

Status

does

with

7 0 0 0

X X X 0 X X X X

Don't Don't Don't Don't Don't

zero.

before

heads

and

not

the

new

6 5

Care Care Care Care Care

the

Caviar

Upon

receipt

to

cylinder

updating

cannot

Error

Registers,

invalidate

physical

Binary

to

move

of

zero.

the

Status

reach

any

cache

cylinder

Opcode

4

1 X

the

read/write

the

command,

The

intelligent

Register,

cylinder

3

zero,

respectively.

segments,

number

becomes

2 1

X

heads

the

intelligent

drive

waits

clearing

the

ERR

but

ensures

the

0

X X

from

for

BSYand

bit

and

that

current

44

o =

Drive

Designation

Bit

X =

Don't

Care

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.2

Seek

(70B)

The

Seek

Command

the

task

file's

cylinder asserts seek before COMPLETE

Seek

associated segment.

BSY

in

is

not

completed

SEEK

COMPLETE

is

does

not

with

Register

Command SOH

Write

Precomp Sector Sector Cylinder Cylinder

Count Number

Low

High

positions

number

the

Status

asserted

invalidate

the

new

Register,

before

is

asserted,

when

the

any

physical

7

0

Drive Don't Don'teare Don't Starting Starting

the

read/write

registers.

starts

the

Caviar

the

heads

cache

cylinder

6 5

1 1 1 X X

and

Care Care

Cylinder Cylinder

heads

When

the

seek

returns

Caviar

can

reach

the

segments,

number

Binary

Ope

4

Head

LSB MSB

command

operation the receive

specified

but

becomes

over

the

is

interrupt.

another

cylinder.

ensures

the

ode

2 1

3

cylinder

received,

and

sets

If

BSY

command.

that

any

current

X X

specified

the

INTRQ.

is

read/cache

in

Caviar

The

cleared

SEEK

segment

0

X =

Don't

Care

Western Digital Corporation

45

Caviar AC160lAC2120 Technical Reference Manual

5.3.3

Read

For a Read location 256 of an along enabled

from With

monitored partitioning segments be

Sector

of

the

sectors,

zero

specifies

implied

used

Register

Command SOH

Write

Sector Sector Cylinder Cylinder

seek

with

the

and

each

sector

CacheFlow,

to

are

to

read

Pre

Count Number

(2XB)

Sector

Command,

sectors

but

only

256

occurs.

data.

the

long

is

transferred

the

perform

changes

checked

data

camp

low High

the

transferred

single-sector

sectors.

If

Single

mode

requested

segment

are

not

for

data.

from

disk

to

If

the

long

burst

errors

is

not

selected.

to

the

sector

partitioning

required,

If

there

and

7

6 5

o

.-

0

Sector Don't

Care

1-256

Sectors Starting Starting Starting

task

file's

the

host.

reads

are

drive

is

mode

of

host.

address

the

is

no

to

store

Binary

1

Size,

Drive

Sector Cylinder Cylinder

registers

The

allowed

not

positioned

bit

is

set,

up

to

An

interrupt

and

sequential/repetitive

currently

cache

read-ahead

4

determine

host

can

in

long

four

11

bits

are

occurs

and

sector

active

hit,

the

data

Opcode

3 2 1

at

ECC

least

0 0 0

and

Head

to

be

Read

Number

LSB MSB

the

number

request a maximum

mode. A sector the

specified

bytes

are

corrected

before

count

segment

after

if

the

parameters

switching.

used

segment

the

last

and

count

cylinder,

transferred

retries

are

data

read

are

and

other

will

sector.

0

L R

of

If

46

l = R=

long

Retry

Mode

Bit

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.4

Write

For a Write drive. single-sector

is

will An

The the

DRQ segment. segments referenced

Sector

starting

not

positioned

transfer

interrupt

first

data

request

must

Sector

four

is

be The remain

by

Register

Command

SOH

Write

Precomp Sector Sector Cylinder Cylinder

Count Number

low High

(30B)

Command.

at

the

writes

are

at

the

ECC

bytes

generated

buffer

contents

status

set

before

base

segment

valid.

the

disk

write

the

logical

address

allowed

specified

along

as

the

are

bit

is

"on".

the

Caching

operation

7 6

0 0

Sector Oon'tCare 1-256 Starting Starting Starting

host

in

long

address.

with

data

sent

host

write

is

reserved

segments

become

Size,

Sectors

Sector Cylinder Cylinder

transfers a number

specified

mode.

the

for

after

Binary

5

1 1

Drive

If

the

data.

each

sector

the

buffers

for

inva

4

and

to

be

by

the

An

implied

long

mode

is

host

has

begin

write

operations.

that

contain

lid

before

Opcode

3 2

0 0

Head

Written

Number

LSB MSB

of

sectors

task

file

registers.

seek

occurs

bit

is

set.

required.

issued

transferring

sectors

the

except

the

write

1 l R

(1-256)

command

Other

to

the

Only

ifthe

drive

then

the

host

the

first.

and

to

the

base

caching

that

were

is

compl~ted.

0

l = long R=

Retry

Mode

Bit

Western Digital Corporation 47

Caviar AC160 IAC212 0 Technical Reference Manual

5.3.5

Format

The with Sectors-Per-Track values contain present, to

zeros.

contain

•

Unused the allowed. with generated

Track (50H)

track

specified

the

interleave

are

totally

descriptors

then

The

512

bytes

The

first

cate a bad

sector The

second

bytes

Sector

Count

The

the

value

upon

by

(SPT)

dependent

no

operation

interleave

of

byte

sector

or

to

"40H" byte

may

be

and

Sectors-Per-Track

indicated

completion

Register

the

task

file

table

transferred

entries, 1 through

upon

for

the

current

is

executed

table

identifies

data.

Thistable

is

set

to

'OOH"

or

to

"20H"

to

assign

designates

uninitialized.

SOH

Registers,

value

by

the

Set

of

the

is

formatted

to

the

sector

SPT

the

translation

on

that

any

is

comprised

to

indicate a good

to

unassign

this

sector

the

logical

The

SPT

and

respectively.

in

the

Sector

Orive

Parameters

command.

Binary

with

10

buffer.

for

the

mode

SPT

value.

sector.

bad

sectors

of

two

the

alternate

to

an

alternate

sector

10

Sector-Size

Only

Count

Opcode

and

data

fields

The

buffer

track's

10

selected.

If

these

The

data

fields

on a given

bytes

per

sector

or

location

sector.

number

values

512

bytes

Register

Command.

in

contains

files.

The

entries

are

track

sector

to

·SOH"

for

(l-SPT).

are

per

must

An

accordance

the

These

SPT

buffer

must

are

not

initialized

and

must

as

follows:

to

indi-

this

specified

sector

correspond

interrupt

in

are

is

48

Command SOH

Write

Pre

camp Sector Sector Cylinder Cylinder

Count Number

Low High

7

6 5

0 1 0

Sector Don't Number Don't Cylinder Cylinder

Size,

Care

of

Care

Address Address

Drive

Sectors

4

1

and

per

3 2

0 0

Head

Track

1

0

0 0

LSB MSB

Western Digital Corporation

HOST

INTERFACE AND

AT

COMMAND

SET

5.3.6

Read Verify

The

Read

Verify

requested

With

monitored partitioning data. begins.

for

Register

Command SOH

Write

Sector Sector Cylinder Cylinder

sectors

CacheFlow.

to

perform

changes

If

the

physical

If

the

data

before

Precomp

Count Number

Low High

physical

(40B)

Command

are

not

the

requested

segment are cylinder

cylinder

the

seeking

is

the

transferred

sector

partitioning

not

required.

is

valid.

is

invalid.

operation

7

6 5

1

0

Sector Don't 1-256 Starting Starting Starting

Size, Care Sectors

same

as a Read

to

the

address

and

the

currently

but

no

other

host.

data

active

Command

and

sector

sequential/repetitive

active

is

present. a read

cache

begins.

Binary

Opcode

3 2 1

4

0 0 0 0 0

Drive

and

Head

to

Verify Sector Cylinder Cylinder

Number

LSB MSB

except

count

parameters

segment

is disk

segments

that

the

are

switching.

checked

for

operation

are

checked

0

R

If

Western Digital Corporation

----=-

.-~----

R=

Retry

Bit

49

Caviar

AC160lAC2120

Technical Reference Manual

5.3.7

Execute

The

Execute

and

to

The

following

•

• A

If

the diagnostics) performed

Diagnostics

report a result

01

=No

Error 02 = Not 03 = Buffer 04 = WD42C22C 05:::

Microprocessor

ax

=

Slave

ROM

checksum

RAM

test.

RAM. RAM

and

register

Caviar

line. A slave

its

Command

code

Applicable

RAM

error register

Internal

drive

failed

tests

are

performed:

test

Tests 2 KBytes

An

incremental

then

read

test

of

the

is

configured

diagnostics.

(90H)

causes

in

the

Error

Register

error

RAM

of

the

pattern

back.

WD42C22C

as a master

drive

pulls

is

this

the

Caviarto

as

erroro(ROM

microprocessor written

to

is

performed.

drive,

line

active

execute

follows:

checksum

and

both

internal

it

monitors

low

the

once

its

self-diagnostics

error

64-KByte

and

it

has

buffer

external

PDIAG

(passed

successfully

50

If

the

Execute

drives

execute

drive.

The

the

slave

is

always Register

Command SOH

Write

Sector Sector Cylinder Cylinder

Diagnostics

the

master

drive's

drive

to

assert

returned

Precomp

Count Number

Low High

Command

command

as

task

PDIAG.

zero

to

just

the

7

1

Drive Don't Don't Don't Don't Don't

as

file

The

host

is

issued

if

the

drives

the

Drive

following

6 5

0 0

Care Care Care Care Care

with

the

slave

drive

selected,

command

bus

Designation

Binary

has

and

it

the

Execute

Opcode

4

3

1

been

waits

Bit

(bit

Diagnostics

2 1

0

issued

up

to

4

of

the

0

to

the

five

seconds

SDH

Register)

Command.

0 0

Western Digital Corporation

both

master

for

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.8

Set

Drive

The

Set

Drive

logical

Sectors

and

the

SOH

values

for 17-SPT Caviar

and

AC2120

Register

Command SOH

Write

Sector Sector Cylinder Cylinder

Parameters

Per

Register

SPT

and

seven

are

Precomp

Count Number

Low High

(91H)

Command

Track

(Spn

and

determine

heads,

heads

for

recommended.

SPT

the

Caviar

the

Caviar

7

6 5

1

0 0

Drive

and Oon'tCare 1-255

Sectors Oon'tCare Don't

Care Oon'tCare

configures

heads.

The

and

heads,

is

always

AC160,

Binary

Heads

per

the

Caviar

values

in

the

respectively.

in

translation

and

35-SPT

Opcode

4

3

1

0

Track

for a specific

Sector

Count

Regardless

mode. A value

and

eight

heads

2 1 0

0 0

number

Register

of

for

1

of

the

of

the

Western Digital Corporation

51

Caviar AC160lAC2120 Technical Reference Manual

5.3.9

Write

For a Write drive, seek

An media. and

DRO segment. segments

referenced

DMA (CAB)

starting

occurs

interrupt

The

the

data

must

be

The remain

by

Register

Command SOH

Write

Precomp Sector Sector Cylinder Cylinder

Count Number

DMA

Command,

at

the

if

the

drive

is

generated

first

data

request

received

base

the

disk

Low High

logical

is

not

when

buffer

bit

is

before

segment

valid.

write

the

host

address

contents

·on·.

Caching

operation

7

1 1 Sector

Don't

1-256 Starting Starting Starting

specified

positioned

all

the

are

the

host

is

reserved

6 5

Size, Care Sectors

transfers a number

by

the

task

at

the

specified

data

has

been

transferred

sent

after

the

host

write

buffers

for

segments

become

Binary

write

that

invalid

Opcode

4

begin

operations.

contain

before

3

0 0 1 0

Drive

and

Head

to

be

Written Sector Cylinder Cylinder

Number

LSB MSB

of

sectors

file

registers.

address.

and

has

issued

transferring

sectors

the

write

2 1

1 R

(1-256)

written

Other

to

An

implied

to

the

command

to

the

caching

that

is

completed.

0

the

base

were

52

R=

Retry

Bit

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.10

Read

For a Read

location 256 positioned up has

For

DMA

of

the

sectors. A sector

at

to

11

bits

are

been

transferred

this

command,

(20H).

Register

Command SOH

Write

Precomp Sector Sector

Cylinder Cylinder

Count Number

Low High

(e8B)

Command,

sectors

the

specified

corrected

the

transferred

count

of

cylinder,

if

retries

to

the

host

caching

operation

7

1 1

Sector Don't 1-256 Starting Starting Starting

task

to

the

zero

specifies

an

are

and

status

6

Size,

Care

Sectors

Sector Cylinder Cylinder

file's

registers

host.

The

implied

enabled.

is

available.

is

the

Binary

5

seek

same

4

0 0

Drive

and

to

be

Number

lSB MSB

determine

host

can

256

sectors.

occurs.

An

interrupt

as

in

Opcode

3

1

Head

Read

the

number

request a maximum

If

the

drive

Single

burst

occurs

when

Read-Sector

2 1

0 0

and

is

errors

all

data

.command

0

R

of

not

of

R=

Retry

Bit

Western Digital Corporation 53

Caviar AC160lAC2120 Technical Reference Manual

5.3.11

Read Multiple (C4H)

The

Read

Multiple

except

for

the

•

Data

•

long

•

Retries

Interrupts per Command transferred block. for correctly.

Register

Command

and

block

is

Partial

transfer.

Otherwise,

transfers

bit

(not

Command

following

is

invalid

are

always

DROs

occur

set

using

issued,

the

blocks

block

transfers

The

Caviar

conditions:

occur

performed.

once

the

Sector

or

block

must

the

command

operates

in

multiple

per

Set

Multiple

Count

count).

are

completed

be

7 6

1 1 0

sector

block

value

Sector

in

multiple

aborts.

similarly

of

Binary

5

to

the

blocks

mu

Itiple

sectors.

Command.

sets

the

total

count

need

when

the

remaining

mode

for

Opcode

4

3

0

Read

The

When

number

only

this

command

2

1

Sectors

number

the

Read

of

sectors

be

a

multiple

sectors

1

0 0

Command

of

sectors

Multiple

to

be

of

the

are

ready

to

operate

0

54

SOH

Write

Precomp Sector Sector Cylinder Cylinder

Long Retries

Count Number

Mode

Low High

Bit

always

invalid allowed.

for

Sector Don't

Care

1 -

256

Sectors Starting Starting Starting

this

command.

Size,

Drive

Sector Cylinder Cylinder

and

Head

to

be

Read

Number

LSB MSB

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.12

Write Multiple (CSH)

The

Write

Multiple

except

for

the

•

Data

transfers

•

Long

bit

•

Retries

Interrupts Sectors-per-Block Multiple

to

be

the

ready correctly.

DRQ segment. segments referenced

and

Command

transferred

block.

Partial

for

transfer.

Otherwise.

must

be

The remain

by

Command

following

occur

in

invalid.

are

always

DROs

occur

value

is

issued,

(not

blocks

block

The

Caviar

the

received

base

segment

valid.

the

disk

write

conditions:

performed.

is

transfers

command

before

operates

in

multiple

once

per

set

using

the

Sector

or

block

are

must

be

aborts.

the

host

is

reserved

Caching

operation

similarly

sector

blocks.

block

of

the

Set

Multiple

Count

value

count).

Sector

completed

in

multiple

write

buffers

for

segments

become

inva

to

the

multiple

Command. sets count

when

mode

for

begin

write

operations.

that

contain

lid

before

Write

Sectors

sectors.

the

total

number

need

not

the

remaining

this

command

transferring

sectors

the

write

Command

The

Number

When

the

be a mu

sectors

to

Other

that

is

completed.

Write

of

sectors

Itiple operate

the

base

caching

were

of

are

Register

Command SOH

Write

Precomp Sector Sector Cylinder Cylinder

Long Retries

Count Number

Low High

Mode

always

Western Digital Corporation

Bit

invalid

allowed.

7 6 5

1 1

Sector Don't 1 Starting Starting Starting

for

Size,

Care

256

Sectors

Sector Cylinder Cylinder

this

command.

Binary

4

0 0

Drive

to

be

Number

LSB MSB

Opcode

3 2

0 1 0 1

and

Head

Written

1

0

55

Caviar AC160lAC2120 Technical Reference Manual

5.3.13

Set

Multiple (C6H)

The

Set

Multiple

between Number maximum buffer considered

the

of

Sectors-per-Block

number

it

is

eight. A value

valid. A value

Register

Command SOH Write

Precomp Sector Sector Cylinder Cylinder

o =

X =

Count Number

Low High

Drive

DeSignation

Don't

Care

host

Command

and

of

sets

the

Caviar

sectors

beyond

of

zero

7

1 X X X 0 X X X Don't

1 Don't Don't Don't

Bit

the for

value

per

block

the

disables

6 5

1

Care

16

Sectors Care Care Care

number

the

Read

is

loaded

for a 64

limit

multiple

Binary

0

of

sectors and into

KByte

causes

Opcode

4

0 0

Per

Block

per

block

to

be

Write

Mu

Itiple

Commands.

the

Sector

Count

Register.

buffer

is

16,

for a 32

termination. A value

mode.

2 1 0

3

1 1 0

transferred

The The

KByte

of

one

is

X

56

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.14

Standby

The

Standby

Power

Mode,

and

is

capable

may

take

the

media

Ready

(DRDy)

interface

even

Register

Command SOH Write

Precomp Sector Sector Cylinder Cylinder

o =

Drive

X =

Don't

Immediate

then

clear

of

accepting

as

long

as

is

not

immediately signal though

Count Number

Low

High

Designation

Care

(EOH)

Command

BSY

10

seconds

is

not a power

the

media

7 6 1

X X X D X X Don't

Don't Don't Don't Don't

Bit

causes

and

generate

all

the

supported

to

respond

accessible

condition.

is

not

1

Care Care Care Care Care

the

drive

an

interrupt.

AT

to a media

due

to a spindown

accessible

..

Binary

4 3

5 1

0

to

set

BSY,

The

drive

commands.

access

The

drive

will

.

Opcode

2 1

0

enter

the

interface

However,

command

condition.

post

Ready

0 0

X

Standby is

active

the

drive

because

The

Drive

at

0

X

the

Western Digital Corporation

57

Caviar AC16 0 IAC212 0 Technical Reference Manual

5.3.15

Idle Immediate

The

Idle

Immediate Mode. electronics any

clear

are

media

access

Register

Command SOH

Write

Precomp Sector Sector Cylinder Cylinder

o =

X =

Count Number

low High

Drive

Don't

Designation

Care

BSY

and

turned

commands.

(EIH)

Command

generate

off.

causes

In

the

7

1

X X X 0 X X Don't

Don't Don't Don't Don't

Bit

the

an

interrupt.

Idle

Mode

6 1

Care Care Care Care Care

drive

the

Binary

5

1

to

set During drive

Opcode

4

3

0 0

BSY,

enter

Idle

Mode.

will

respond

2 1 0

0 0

the

Idle

Power

non-essential

immediately

1

X X

to

58

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.16

Standby With

The

Standby clear supporting as

10 immediately is

not a power

media

The

drive

prescribed

specified

If

the

a

timer

the

drive down unit

of

interval; is

1000 Register

Command

BSY

and

generate

all

the

seconds

is

register

will

sequence

time

to

accessible

condition.

not

accessible.

will

automatically

time

using

the

is

begin

in

the

specified

the

minimum

seconds

following non-zero

Idle

is

(16.6

Tuner

supported

respond

Sector

counting

Power

disabled

(E2H)

causes

an

interrupt.

to a media

due

to a spindown

The

the

Count

then

down

Mode.

and

in

the

timer

period

minutes).

7

the

drive

The

AT

commands.

access

drive

will

re-enter

execution

the

Sector

this

Register

automatic

upon

If

the

drive

Count

applicable

6 5

to

set

BSY,

enter

drive

interface

However,

command,

condition.

post

Ready

at

Power

Mode

of

the

last

command.

when

issuing

power

completion

register

will

Binary

of

is

remain

Register

is

60

seconds

Opcode

4

the

Standby

is

active

the

drive

because

The

Drive

Ready

the

interface

upon

the

This

the

Standby

down

sequence

the

last

command

zero

then

the

in

the

Idle

Power

corresponds

and

the

2 1

3

Power

and

is

capable

may

take

the

media

(DRDY)

even

though

expiration time

interval

Command

is

enabled

which

automatic

Mode.

to a five

maximum

0

Mode,

of

as

long

is

not

signal

the

of

a

is

(E2).

and

left

power

Each

second

period

Command SOH

Write

Precomp Sector Sector Cylinder

Cylinder

o =

X =

Count Count Number

low

High

Drive

Designation

Don't

Care

Western Digital Corporation

1 1 1

X X X 0 X X X X Don't

Care of

five

second,

Don't

Care

Don't

Care

Don't

Care

Bit

0

units

0

1

0

59

Caviar AC16 0 IAC212 0 Technical Reference Manual

5.3.17

Idle

With

Timer

The

Idle

Command

clear

BSY

and

immediately

The

drive of a prescribed command.

Idle

(E3) sequence last

command then

the

in

the timer minutes).

Register

Command SOH

to

will

automatically

This

Command.

is

enabled

which

automatic

Sector

Count

applicable

(E3H)

causes

generate

any

media

time

following

time

interval If

the

and a timer

left

power

Register

is

60

seconds

the

drive

an

interrupt.

access

commands.

transition

the

execution

is

specified

register

will

the

drive

down

sequence

corresponds

and

7

6 5

1 1

X X D X X X X

X

to

set

to

is

non-zero

begin

in

the

BSY,

enter

In

the

Idle

the

Standby

of

the

using

the

then

counting

Idle

Power

is

disabled.

to a five

maximum

Binary

Opcode

4

1

0

the

mode

Power

Idle

(E3)

Sector

the

down

Mode.

Each

second

period

3

0

Idle

Power

the

drive

Mode

upon

command

Count

Register

automatic

upon

completion

If

the

register

unit

of

time

interval;

is

1000

seconds

2 1

1

0

Mode,

will

respond

expiration

or

any

and

power

specified

the

minimum

0

1

then

other

the

down

of

the

is

zero

(16.6

60

Write

Precomp

Sector Sector Cylinder Cylinder

D =

X

Drive

=

Don't

Count Number

Low High

Designation

Care

Don't

Count Don't Don't Don't

Bit

Care

of

five Care Care Care

second,

units

Western Digital Corporation

HOST INTERFACE

AND

AT

COMMAND

SET

5.3.18

Read ButTer (E4H)

The

Read

Buffer

Command

RAM

cache,

for

example,

segment.

Register

Command SOH

Write

Precomp Sector Sector Cylinder

Cylinder

o =

X =

Count Number

Low

High

Drive

Don't

Designation

Care

allows

the

host

the

512

bytes

7

6 5

1 1

X X X

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Bit

to

of

the

Binary

1

read

Buffer

first

sector

Opcode

4

3

0

X X X X

0

of

the

buffer

2

1

Caviar

in

the

1

0 0

64-KByte

base

cache

0

Western Digital Corporation

61

Caviar AC160lAC2120 Technical Reference Manual

5.3.19

Check

The mode,

If set

If

to In

is

Power

Check

Power

and

programmed

the

drive

is

in

the

Sector

Count

the

drive

is

in

FFH,

then

clear

the

Cylinder

returned. A value

low

Register

Command SOH

Write

Precomp Sector Sector

Cylinder Cylinder

Count Number

Low High

Mode

Command a lIows

va

or

transitioning

Register

the

Idle

Power

BSY

and

Register,

of

DOH

(E5B)

the

host

to

lue

for

the

spin

to

the

Standby

to

DOH,

then

Mode,

it

will

generate

the means

7

1 1 1

an

interrupt.

currently

that

the

6 5

determine

down

timer.

Power

Mode,

clear

BSY

and

set

BSY.

set

programmed

timer

Binary

va

is

disabled.

Opcode

4

3 2

0 0

the

lue

the

drive

generate

Sector

for

the

spin

1

0

current

will

an

interrupt.

Count

down

0

1

X X X 0 X X X X

Don't

Care

Don't

Care

Don't

Care

Don't

Care

Don't

Care

power

set

BSY.

Register

timer

62

o =

X =

Drive

Don't

Care

Designation

Bit

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.20

Sleep (E6H)

The

Sleep

Command

only

vehicle active or a Power reset A

cycling Sleep generated

Register

Command SOH Write

Sector Sector Cylinder Cylinder

and

is

On

or

AT

bus

of

Power

and

Precomp

Count Number

Low High

to

cause

capable

Reset

reset

power

Mode

the

causes the

drive

of

accepting

are

the

when

in

returns

interface

the

drive

7 6

1 1 1

X X X 0 X Don't

Don't Don't Don't Don't

the

drive

to

enter

only a Soft

only

means

the

Sleep

drive

to

motor

becomes

inactive.

Care Care

Care Care Care

to

enter

this

power

for

recovery

Mode

its

default

is

stopped,

Binary

5

the

Sleep

mode.

Reset. A Soft

from

returns

the

drive

ready

BSY

is

Opcode

4 3 2

0 0

Power

Mode

The

drive

interface

Reset,

an

this

power

to

the

Sta

mode.

Upon

cleared,

an

1

1 1 0

X X X

and

is

the

is

in

AT

Bus

Reset

mode. A soft

ndby

Mode.

entry

to

the

interrupt

is

0

o =

Drive

Designation

X =

Don't

Care

Western Digital Corporation

Bit

63

Caviar AC160lAC2120 Technical Reference Manual

5.3.21

Write Buffer

The

Write

Buffer

that

512

bytes

of

Note:

The

Read

bytes

of

Register

Command SOH Write

Precomp Sector Sector Cylinder Cylinder

o =

X =

Count Number

Drive Don't

Low High

Care

Designation

(E8B)

Command

data

and

the

functions

are

transferred

Write

Caviar

7

1 1 1

X X

Don't Don't Don't Don't

Don't

Bit

Buffer

RAM

identica

from

the

Commands

cache.

Binary

6 5

X

Care Care Care Care Care

Ilyto

the

Read

Buffer

Command

host

to

the

Caviar

RAM

only

affect

the

first

Opcode

4

0

0 X X X X

2 1 0

3

1

0 0 0

except

cache.

512

64

Western Digital Corporation

HOST INTERFACE

AND

AT

COMMAND

SET

5.3.22

Identify Drive (ECH)

The

Identify parameters. when

Register

Command SOH

Write

Sector Sector Cylinder Cylinder

o =

X =

the

Caviar

Precomp

Count Number

low High

Drive

Don't

Care

Drive

Command

The

host

is

required

sets

ORO

Designation

and

Bit

transfers

IRO.

7

1 1

X X X 0 X

Don't

Don't Don't Don't Don't

to

read

Table

6

Care Care Care Care Care

512

bytes

the

5-4

Binary

5

1

lists

of

data

parameters

the

parameters

Opcode

4

3

1 1

0

that

specify

out

of

2 1

X

the

sector

read

by

0

o .

0

X X

drive's

buffer

the

host.

Western Digital Corporation

65

Caviar AC160lAC2120 Technical Reference Manual

Word

0 1 2 3 4 5 6 7 8 9

10-19

20 21

22 23-26 27-46

47

48

49

50

51

52

53-255

Description

General Number Number Number Unformatted Unformatted Sectors Minimum

Reserved Minimum Serial Controller Controller Number Firmware Controller Number Double DMA Reserved PIO DMA Reserved

configuration affixed of

removable

of

heads

per

track

size

PLO

number

type

buffer

ECC

Rev.

model

of

Sectors/interrupt

word

capabilities

data

transfer

data

transfer

•

cylinders

(AC160 = 7,

bytes

per

bytes

per

(ACl60 = 17,

of

ISG

bytes

(ASCII

(3)

size

bytes

transferred

(ASCII

number

110

(0)

(0100H) cycle

cycle

(427A)

(ACl60 = 1024,

cylinders

AC2120 = 8)

track

(Zl = 27,264,

sector

in

(14)

characters,

in

characters,

bytes

512

byte

(ASCII

(568)

(7)

R/W

timing

(0)

timing

AC2120 = 872)

(00)

Z2 = 22,720)

AC2120 = 35)

WOnnnnnn)

increments

on

long

operations

XX'>O(JO()

characters,

multiples

(0)

WOC

AC2120)

(8010H)

66

*

Note:

The

512

data

bytes

structure

of

information.

Table

5-4.

for

the

Indentify

Identify

Drive

Command

contains

Western Digital Corporation

HOST

INTERFACE

AND

AT

COMMAND

SET

5.3.23

Set

ButTer Mode (EFH)

The

Set

Buffer Precompensation Precompensation default to

number

enable

caching

Register

Command SOH Write

Precomp Sector Sector Cylinder Cylinder

o =

X =

Count Number

Drive

Don't

Mode

Register

of

cache

with

Low High

Designation

Care

Command

is

set

segments,

one

to

7

1 1 1

X X X 0 X AAH

Don't Don't Don't Don't

Bit

set

to

55H,

the

five

segments.

6 5

or

55H, Care Care Care Care

enables

AAH,

then

CacheFlow

Precompensation

Binary

A 1

H-ASH

or

disables

CacheFlow

is

disabled.

Register

Opcode

4

3 2 1 0

1 1 1

0

X

CacheFlow.

is

enabled.

To

modify

is

setto

A 1

0

X

If

the

If

the the

H-A5H

Western Digital Corporation

67

Caviar AC160lAC2120 Technical Reference Manual

5.4

HOST INTERFACE READ TIMING

ADDRESS VALID TIME (HA0-2)

---1~r----

o 0

:

tASU1

, :

i'

"1

o 0 0

:

tCS01

I I • I

'. • •

lOR

: tMRIRA

o 0

: tRCY : :

it

--I---1j

:

o 0

:

tDV1

0 :

I:

(Data Port Only)

HOST DATA 0-15 :HOST DATA BUS VALID

--------~~~---

tClCSV

o tAlCSV

o 0

'.

IOCS16:

---

:

I

tAH1

tRDR

tDH1

(HDO-HD15)

:

':

o

:

tAlCSI

: tClCSI

: :

:.--

o 0

or-

.....---.1

!

I

::··--!'""""""·i

:.

L

68

SYMBOL DESCRIPTION MIN

tASUI tCS01 tMRIRA

tAH1 tOV1

tDH1 tRDR tClCSV tAlCSV tClCSI tAlCSI tRCY

Note:

All

Figure

units of All

values

5-2.

Address Chip

I/O I/O

Chip Data Data Data

Chip

IOCS16

iOCS'i6

IOCS16 IOCS16 Read Read

measurement

Host

setup

select setup

read

active -

read

active -other ports

select/Address

valid valid hold

selectJRead

valid valid inactive inactive

cycle time -

cycle

based

on a maximum

Interface

time

are

time

from from

in

time

Port

0

hold

- Port 0

- other ports

form form

- other ports

nanoseconds,

time

rect:N~

CSO

HAO

eso

HAO

Port

0

load

capacilBnce

Read

Timing

time

unless

of

Western Digital Corporation

30 22 75

100

10

5

20

330

150

otherwise

50

pf.

MAX

60

100

50 20

20 20

20

noted.

HOST

INTERFACE

AND

AT

COMMAND

SET

5.5

HOST

(Data Port Only)

INTERFACE

-~~"----

I I

CSO/

: tASUI I :

CSi

II

I I I

I : .

: : '

: tCS02 : tlWA : tASU2:

.

HOST DATA 0-15

---------~~~

tClCSV : tAlCSI

I tAlCSV : tCICSI

I I : :

i5CS16

H H

WRITE

ADDRESS VALID TIME (HA0-2)

':

.1.

: :.

~I

___________________________

TIMING

tWCY I

tDV2 tDH4

I

'I

:HOST DATA

.:...---..'

:~ER

'.1'

BUS

VAliD

tAH2

tCHW :

(H'DO-HD15)

:

I I

~r-

.:

I'

L

Western Digital Corporation

SYMBOL DESCRIPTION MIN

tASU2 tCS02 tlWA

tAH2 tDV2

tDH4 tCHW tClCSV tAlCSV tClCSI tAlCSI fWCY

fWER

Note:

All

Figure

Address Chip 110 110 Address Data Data

Data hold

Chip IOCS16

iOCSi6

IOCS16 IOCS16 Write Write Write

unils of

All values based on a maximum load capacitence of

5-3.

Host

setup

select

read

active -Port

read

active -other hold

setup

- Port 0

setup

- other ports

time

select

valid

valid inactive inactive

cycle cycle

recovery

measurement

Interface

time

setup

time

hold

til!!!L

from

CSO

from

HAO

form form

time -Port time -other

time

are

in

nanoseconds.

Write

0

ports

CSO

HAO

0

ports

Timing

100

330

150

unless

30

22

75

20

50 50 15 10

20

otherwise

50

pf.

MAX

20 20 20 20

noted.

69

Caviar

AC160lAC2120

Technical Reference Manual

5.6

ERROR REPORTING

Table

5-5

lists

all

the

valid

error

The

Caviar

drive determine command point

Command Recalibrate

Seek Read/DMARead Write/DMA Write Format Read Execute Set Parameters Read

Write

Set Read Write

Identify Set

Invalid

BBD • Bad UNC

IDNF • 10 AC • Abort DRDY • Drive

if

is

where

Long-

long

Track

Verify

Diag

Drive

Multiple-

Multiple

Buffer

Drive

Buffer

Command

•

Uncorrectable

•

Also

-

Also

checks

any

condition

then

attempted.

it

is

encountered.

•

-

Mode

Block

Not

Found

Command

Not

sets sets

the

exists

Any

BBD

UNC

V V V V V V V V V V V V

V V V V V

V

V V V V V V V

V

Detected

Data

Error

Ready

Error

TKO

in

Error

DAMNF

in

conditions

Command

which

subsequent

IDNF

Register

Error

Register

which

Register

could

result

error

Error

Message

DRDY

AC

V V V V

V V V V V V

V

V V

V V V V V

DWF

•

Drive DSC · Drive CORR· ERR · Error V

if

no

·

track

if

data

Data

Valid

zero

address

can

occur

for a given

at

the

start

of a command

in a terminated

terminates

DWF

V V

V

V V V V

V V V

Write

Seek

was

Bit

Error

is

found.

the

DSC

V V

V V V

Fault

Complete

Corrected

in

Status

Register

for

Command

mark

not

command.

command

CORR

Error

found.

ERR

V V V

V

to

The

atthe

70

Table

5-5.

Error

Reporting

Western Digital Corporation

INSTALLATION AND SETUP PROCEDURES

6.0

INSTALLATION AND SETUP PROCEDURES

6.1

UNPACKING

6.1.1

6.1.2

6.1.3

Handling

Western unpacking mechanical Caviar installed prevent

Inspection

Carefully

signs

representative

container

Removal

Precautions

Digital

and

shock

and

void

in

its

proper

damage,

examine

of

crushing, in

the

From

products

installing

or

the

warranty.

host

do

not

of

Shipping

the

or

if

you

upright

Shipping

are

designed

the

drive.

electrostatic

When

enclosure,

unpack

your

Container

container

stains.

observe

position

for

Notify

any

indicated

Container

to

Care

discharge

the

Caviar

it

must

Caviar

until

obvious

the

shipment

by

withstand

must

be

that

can

is

not

be

placed

you

are

shipping

carrier

damage.

the

arrows

normal

taken

to

permanently

in

its

shipping

on

an

antistatic

ready

to

damage,

and

Always

on

your

the

for

move container.

handling

avoid

excessive

damage

container

surface.

install

it.

example:

Western

the

shipping

when

the

or

To

holes,

Digital

Remove Carefully When the

its

stand

the

open

removing

bezel

(if

antistatic

the

Caviar

the

Caution:

Handle not compartment.

the

touch

Caviar

circuit

Western Digital Corporation

from

the

box.

the

Caviar

bag

on a clean,

on

Never

from

severely circuit

only

board

Failure

the

The

Caviar

has

edge.

drop

the

by

board

to

observe

shipping

Caviar

from

the

been

shipped

level,

the

shipping

damage

board.

holding

the

components.

these

container

is

always

foam

grounded

shipped

insert,

grasp

with a bezel).

work

CBViarfrom

contJIiner.

the

head

metal

cover

Do

restrictions

only

for

the

station.

any

height

Dropping

disk

assembly

of

the

not

attempt

will

void

inspection

in a foam-insert

drive

Gently

Do

head

at

the place not

when

the

Dr

disk

to

the

warranty.

or

installation.

sides,

the

stack

removing

Caviar

printed

assembly.

open

its

package.

behind

Caviar

in

drives

or

it

can

Do

sealed

71

Caviar AC16 0 IAC212 0 Technical Reference Manual

6.1.4

6.1.5

6.2

Removal

Before

•

After

Handle circuit downward

Moving

If

it

becomes automatically zone

where

from

accidental

From

removing

Make Wear a properly

Avoid

attaching

the

board

the

sure

contact

your

Caviar

or

the

during

that

wrist

only

bezel.

installation.

Precautions

necessary

park

the

they

are

locked

damage

Antistatic

Caviar

from

your

work

grounded

with

any

component

strap,

by

the

base

Handle

to

move

heads.

into

due

Parking

place.

to

vibration,

Bag

its

antistatic

station

wrist

gently

casting

the

your

moves

is

strap

remove

Caviar

computer

This

moving

MOUNTING RESTRICTIONS

bag:

properly

with

on

the

areas.

Never

with

the

helps

grounded.

good

skin

printed

circuit

Caviar

lift

the

printed

system,

heads

to

protect

or

shipping.

contact.

from

the

Cavia

turn

a

safe,

the

media

board.

the

antistatic

r

by

circuit

off

the

non-data

and

the

printed

board

power

landing

the

bag.

facing

to

heads

6.2.1

6.2.2

Orientation

The

Caviar

can

be

design

of

your

dimensions

and

mounted

system.

location

in

Figure

of

the

Screw Size Limitations

The

Caviar

is

mounted

CAUTION:

to

the

Screws ponents. threads

which are

(3/16

many

2-1

screw

chassis

The

screw

inch).

different

shows

the

holes.

using

four

too

long

must

ways

depending

Caviar

6-32

screws.

will

engage

upon

AC160/AC2120

damage

no

board

more

than

the

physical

mounting

com-

six

72 Western Digital Corporation

INSTALLATION AND SETUP PROCEDURES

6.3

6.3.1

6.3.2

INSTALLATION CONFIGURATION

Determining Your ComJgUration

You

can

configure

•

The

•

The slots

Both

configurations

If

you

are

using

installation).

a

40-pin

host

to

the

motherboard

Dual

Installations

Dual

installations designated secondary other is

not

(slave)

intelligent

compatible

the

Caviar

drive

is

cabled

directly

drive

is

cabled

to

in

the

computer.

use a 4O-pin

the

Caviar

drive

you

may

use

either

interface

as

cable

or

adapter

require a master/slave

the

primary

drive.

The

drives

that

support a master/slave

with

ST-506

in

one

of

two

to a 4O-pin

an

adapter

host

interface

as

one

of

configuration.

with

three

card.

(master)

Caviar

drives.

drive

ways:

connector

card

mounted

cable.

two

hard

disk

In

dual

connectors

drive

configuration,

and

the

is

compatible

configuration.

on

the

in

one

drives

installations,

and

daisy-chain

other

is

in

dual

motherboard.

of

the

expansion

in

the

computer

you

must

the

two

where

one

designated

installations

The

Caviar

(dual

use

drives

drive

as

the

with

drive

is

If

your

6.3.3

installation

may

also

be

Jumper

The

Caviar

drive.

If

you

do

not

single

drive

Note:

Even

ACTNE/SLAVE

intelligent

If

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Western Digital Corporation 73

Caviar AC160lAC2120 Technical Reference Manual

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INSTALLATION

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6.4.1

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Caviar AC160lAC2120 Technical Reference Manual

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INSTALLATION AND SETUP PROCEDURES

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Western Digital Corporation

77

Caviar AC160lAC2120 Technical Reference Manual

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Western Digital Corporation

INSTALLATION

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6.5

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6.6.1

INSTALUNG THE ADAPTER CARD

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Western Digital Corporation

79

Caviar AC160lAC2120 Technical Reference Manual

6.6.2

Selecting

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INSTALLATION AND SETUP PROCEDURES

6.6.3

Partitioning

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81

Caviar AC160lAC2120 Technical Reference Manual

6.6.5

6.6.6

Booting

After intelligent

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Western Digital Corporation

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Western Digital Corporation

83

Caviar AC160lAC2120 Technical Reference Manual

84 Western Digital Corporation

WESTERN

DIGITAL DRIVE

UTILITY

8.0

WESTERN DIGITAL DRIVE UTILITY

All

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intelligent factory. you the data does

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85

Caviar AC160lAC2120 Technical Reference Manual

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Western Digital Corporation

TROUBLESHOOTING

9.0

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Western Digital Corporation 87

Caviar AC160lAC2120 Technical

R~ference

Manual

88

Western Digital Corporation

GLOSSARY

10.0

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91

Caviar AC16 0 IAC212 0 Technical Reference Manual

92

Western Digital Corporation

Western Digital AC160l, AC2120 Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual