Westcode Semiconductors H0500KC25# Data Sheet

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Date:- 4 Aug, 2004

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IXYS

Company

Data Sheet Issue:- 2

Fast Symmetrical Gate Turn-Off Thyristor

Type H0500KC25#

Absolute Maximum Ratings

MAXIMUM

VOLTAGE RATINGS

DRM

RSM

RRM

RSM

Repetitive peak off-state voltage, (note 1) 2500 V Non-repetitive peak off-state voltage, (note 1) 2600 V Repetitive peak reverse voltage 100-2000 V Non-repetitive peak reverse voltage 100-2000 V

RATINGS

TGQM

T(AV)M

T(RMS)

TSM

TSM2

I2tI di/dt P

FGM

RGM

FGM

RGM

off

jop

stg

Maximum peak turn-off current, (note 2) 500 A Snubber loop inductance, ITM=I Mean on-state current, T Nominal RMS on-state current, 25°C (note 3) 280 A Peak non-repetitive surge current tp=10ms 3.0 kA Peak non-repetitive surge current, (Note 4) 5.4 kA

t capacity for fusing tp=10ms 45 kA2s

Critical rate of rise of on-state current, (note 5) 1000 A/µs

Peak forward gate power 160 W Peak reverse gate power 5 kW Peak forward gate current 100 A Peak reverse gate voltage (note 6) 18 V Minimum permissible off-time, ITM=I Minimum permissible on-time 10 µs Operating temperature range -40 to +125 °C Storage temperature range -40 to +150 °C

LIMITS

MAXIMUM

LIMITS

, (note 2) 0.3 µH

TGQM

=55°C (note 3) 540 A

sink

, (note 2) 60 µs

TGQM

UNITS

Notes:-

=-2Volts.

1) V

=125°C, VD=80%VDM, VDM<V

2) T

3) Double-side cooled, single phas e; 50Hz, 180° half-sinewave.

4) Half-sinewave, t

5) For di/dt>1000A/µs, consult factory.

6) May exceed this value during turn-off avalanche period.

Data Sheet. Type H0500KC25# Issue 2 Page 1 of 15 August, 2004

=2ms

, diGQ/dt=20A/µs, CS=3µF.

DRM

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Characteristics

Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Parameter MIN TYP MAX TEST CONDITIONS

dv/dtcrCritical rate of rise of off-state voltage 800 - - VD=80%V I

GKM

Maximum peak on-state voltage - 2.8 3.2 IG=2A, IT=500A V Latching current - 5 - Tj=25°C A Holding current - 5 - Tj=25°C A

Peak off state current - - 30 Rated V Peak reverse current - - 60 Rated V Peak negative gate leakage current - - 200 VGR=-16V mA

Gate trigger voltage

Gate trigger current

-0.9-T

-0.8-T

-0.7-T

-1.76.0T

-0.62T

-0.10.5T

=-40°C V

=25°C

=125°C V

=-40°C A

=25°C

=125°C A

VD=50%V

Delay time - 0.5 -

=25°C, di/dt=300A/µs, (10%IGM to 90%VD)

Turn-on time - 2.0 3.0 Conditions as for td, (10%IGM to 10%VD)µs

, VGR=-2V V/µs

DRM

, VGR=-2V mA

DRM

RRM

=25V, RL=25m

VD=25V, RL=25m

, I

DRM

=500A, IGM=30A, diG/dt=15A/µs µs

TGQ

Ω

UNITS

Q t

tail

Fall time - 0.5 -

/dt=40A/µs, VGR=-16V, (90%I

Turn-off time - 5.0 6.0 Conditions as for tf, (10%IGQ to 10%I Turn-off gate current - 180 - Conditions as for t Turn-off gate charge - 500 600 Conditions as for t

Tail time - 35 50 Conditions as for tf, (10%I Gate off-time (see note 3) 80 - - Conditions as for t

VD=80%V

DRM

, I

=500A, CS=1µF,

TGQ

to 10%IVD)

TGQ

)µs

TGQ

to I

<1A) µs

TGQ

µs

µC

µs

- - 0.065 Double side cooled K/W

thJK

Thermal resistance junction to sink

- - 0.24 Cathode side cooled K/W

- - 0.09 Anode side cooled K/W F Mounting force 4.5 - 9.0 (see note 2) kN W

Weight - 120 - g

Notes:-

1) Unless otherwise indic at ed T

2) For other clamping f orces, consult factory.

3) The gate off-tim e i s the period during which the gate circuit i s required to remain low impedance to al l ow for t he passage

of tail current.

=125oC.

Data Sheet. Type H0500KC25# Issue 2 Page 2 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Notes on ratings and characteristics.

1. Maximum Ratings.

1.1 Off-state voltage ratings. Unless otherwise indicated, all off-state voltage ratings are given for gate conditions as diagram 1. For other gate conditions see the curves of figure 5. It should be noted that V

is the repeatable peak

DRM

voltage which may be applied to the device and does not relate to a DC operating condition. W hile not given in the ratings, V

should ideally be limited to 60% V

in this product.

DRM

Diagram 1.

1.2 Reverse voltage rating. All devices in this series have a m inim um V 80%V

is available.

DRM

of 100 Volts. If specified at the tim e of order , a V

RRM

up to

1.3 Peak turn-off current. The figure given in maximum ratings is the highest value for normal operation of the device under conditions given in note 2 of ratings. For other com binations of I

, VD and Cs see the curves of figures

TGQ

15 & 16. The curves are eff ective over the normal operating range of the device and as sume a snubber circuit equivalent to that given in diagram 2. If a m ore com plex snubber, s uch as an Under land circuit, is employed then the equivalent C

should be used and Ls<0.3µH must be ensured for the curves to be

applied.

Diagram 2.

1.4 R.M.S and average current. Measured as for standard thyristor conditions, double side cooled, single phase, 50Hz, 180° halfsinewave. These are included as a guide to com pare the alternative types of G TO thyristors available, values can not be applied to practical applications, as they do not include switching losses.

1.5 Surge rating and I

Ratings are for half-sinewave, peak value against duration is given in the curve of figure 4.

1.6 Snubber loop inductance. Use of GTO thyristors with snubber loop inductance, L

<0.3µH implies no dangerous Vs voltages (see

diagrams 2 & 3) can be applied, provided the other conditions given in note 1.3 are enforced. Alternatively

should be limited to 700 Volts to avoid possible device failure.

Data Sheet. Type H0500KC25# Issue 2 Page 3 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

1.7 Critical rate of rise of on-state current The value given is the maxim um r epetitive rating, but does not im ply any specific operating condition. T he high turn-on losses associated with limit di/dt would not allow for practical duty cycle at this maxim um condition. For special pulse applications, s uch as crowbars and puls e power supplies , a m uch higher di/dt is possible. Where the device is required to operate with infrequent high current pulses, with natural commutation (i.e. not gate turn-off), then di/dt>5kA/µs is possible. For this type of operation individual specific evaluation is required.

1.8 Gate ratings The absolute conditions above which the gate may be damaged. It is permitted to allow V off (see diagram 10) to exceed V

which is the implied DC condition.

RGM

GK(AV)

during turn-

1.9 Minimum permissible off time. This time relates specif ically to re-firing of device (see also note on gate-off time 2.7). T he value given in the ratings applies only to operating conditions of ratings note 2. For other operating conditions see the curves of figure 18.

1.10 Minimum permissible on-time. Figure is given for minim um tim e to allow complete conduction of all the GT O thyristor islands. W here a simple snubber, of the form given in diagram 1. (or any other non-energy recovery type which discharges through the GTO at turn-on) the ac tual minimum on-time will usually be fixed by the snubber circuit time constant, which must be allowed to fully discharge before the GTO thyristor is turned off. If the anode circuit has di/dt<10A/µs then the minimum on-tim e s hould be incr eas ed, the actual value will depend upon the di/dt and operating conditions (each case needs to be assessed on an individual basis).

Data Sheet. Type H0500KC25# Issue 2 Page 4 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

2 Characteristics

2.1 Instantaneous on-state voltage Measured using a 500µs square pulse, see also the curves of figure 2 for other values of I

2.2 Latching and holding current These are considered to be approximately equal and only the latching current is measured, type test only as outlined below. The test circuit and wave diagrams are given in diagram 4. The anode current is monitored on an oscilloscope while V period between the end of I

and the application of reverse gate voltage. Test fr equency is 100Hz with I

is increased, until the current is s een to flow during the un-gated

& IG as for td of characteristic data.

Gate-drive

DUT

100µs

Unlatched

Latched

Gate current

15V

Anode current

unlatched condition

Anode current

Latched condition

Diagram 4, Latching test circuit and waveforms.

2.3 Critical dv/dt The gate conditions are the sam e as for 1.1, this c haracteristic is for off -state only and does not relate to dv/dt at turn-off. The measurem ent, type test only, is conducted using the exponential ramp method as shown in diagram 5. It should be noted that GTO thyristors have a poor static dv/dt c apability if the gate is open circuit or R

is high impedance. Typical values: - dv/dt<30V/µs for RGK>10Ω.

Diagram 5, Definition of dV/dt.

2.4 Off-state leakage. For I

DRM

& I

see notes 1.1 & 1.2 for gate leakage IGK, the off-state gate circuit is required to sink this

RRM

leakage and still maintain minimum of –2 Volts. See diagram 6.

Diagram 6.

Data Sheet. Type H0500KC25# Issue 2 Page 5 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

2.5 Gate trigger characteristics. These are measured by slowly ramping up the gate current and monitoring the transition of anode cur rent and voltage (see diagram 7). Maximum and typical data of gate trigger current, for the full junction temperature range, is given in the cur ves of figure 6. Only typical figures are given for gate trigger voltage, however, the curves of figure 1 give the range of gate forward characteristics, for the full allowable junction temperature range. The curves of f igures 1 & 6 should be used in conj unction, when considering forward gate drive circuit requirement. The gate drive requirem ents s hould always be calculated for lowest junction temperature start-up condition.

Anode current

Gate current

Anode-Cathode

Voltage

Current-

sence

Gate-drive

Feedback

DUT

0.9V

Not to scale

0.1I

Diagram 7, Gate trigger circuit and waveforms.

2.6 Turn-on characteristics The basic circuit used for turn-on tests is given in diagram 8. The test is initiated by establishing a circulating current in T

, resulting in VD appearing across Cc/Lc. When the test device is fired Cc/L

discharges through DUT and c omm utates Tx off, as pulse from Cc/Lc decays the constant current source continues to supply a fixed current to DUT. Changing value of C respectively, V

and i are also adjustable.

Gate-drive

& Lc allows adjustment of ITM and di/dt

DUT

Diagram 8, Turn-on test circuit of FT40.

The definitions of turn-on parameters used in the characteristic data are given in diagram 9. The gate circuit conditions I

& IG are fully adjustable, IGM duration 10µs.

diG/dt

di/dt

VD=V

Eon integral

period

Diagram 9, Turn-on wave-diagrams.

Data Sheet. Type H0500KC25# Issue 2 Page 6 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

In addition to the turn-on time figures given in the characteristics data, the curves of figure 9 give the relationship of t

to di/dt and IGM. The data in the curves of figures 7 & 8, gives the turn-on losses both with

and without snubber discharge, a snubber of the f orm given in diagram 2 is as sumed. Only typical losses are given due to the large number of variables which effect E

. It is unlikely that all negative aspects

would appear in any one application, so typical figures can be considered as worst case. W her e the turnon loss is higher than the figure given it will in mos t cas es be compensated by reduced turn-of f loss es, as variations in processing inversely effect many parameters. For a worst case device, which would also have the lowest turn-off losses, E

would be 1.5x values given in the curves of figures 7 & 8. Turn-on

losses are measured over the integral period specified below:-

µs

dtivEon

∫

The turn-on loss can be sub- divided into two com ponent parts, firs tly that assoc iated with t the contribution of the voltage tail. For this series of devices t

contributes 50% and the voltage tail 50%

(These figures are approxim ate and are influenced by several second order ef fects ). The los s during t greatly affected by gate current and as with turn-on time (figur e 9), it can be reduced by increasing I

and secondly

The turn-on loss assoc iated with the voltage tail is not effected by the gate conditions and can only be reduced by limiting di/dt, where appropriate a turn-on snubber should be used. In applications where the snubber is discharged through the GT O thyristor at turn-on, selection of discharge resistor will eff ect E

The curves of figure 8 are given for a snubber as shown in diagram 2, with R=5Ω, this is the lowest recommended value giving the highest E

, higher values will reduce Eon.

2.7 Turn-off characteristics The basic circuit used for the turn-off test is given in diagr am 10. Prior to the negative gate pulse being applied constant current, equivalent to I

, is established in the DUT. The switch Sx is opened just before

TGQ

DUT is gated off with a reverse gate puls e as specified in the charac teristic/data curves. Af ter the period

voltage rises across the DUT , dv/dt being limited by the snubber circuit. Voltage will continue to rise

across DUT until D until energy stored in L required V

Over the full tail time period. The overshoot voltage VDM is derived from Lc and forward voltage

characteristic of D

turns-on at a voltage set by the active clam p Cc, the voltage will be held at this value

is depleted, after which it will fall to VDC .The value of Lx is selected to give

, typically VDM=1.2VD to 1.5VD depending on test settings. The gate is held reverse

biased through a low impedance circuit until the tail current is fully extinguished.

Gatedrive

DUT

RCD snubber

Diagram 10, Turn-off test circuit.

The definitions of turn-off parameters used in the characteristic data are given in diagram 11.

Data Sheet. Type H0500KC25# Issue 2 Page 7 of 15 August, 2004

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TGQ

Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

0.9

0.1

G(AV)

Diagram 11, Turn-off parameter definitions.

In addition to the turn-off figures given in character istic data, the curves of figures 10, 11 & 12 give the relationship of I

GQ QGQ

and tgq to turn-off current (I

) and diGQ/dt. Only typical values of IGQ are given due

TGQ

to a great dependence upon the gate circuit impedance, which is a f unction of gate drive design not the device. The t

is also, to a lesser extent, aff ected by circuit im pedance and as such the m ax im um figures

given in data assume a good low impedance circuit design. The curves of figures 17 & 18 give the tail time and minimum of f time to re-fire device as a f unc tion of turn- of f c ur rent. The minimum off tim e to r e- f ire the device is distinct from t

, the gate off time given in char acteristics. T he GTO thyristor m ay be safely re-

triggered when a small amount of tail c urrent is still flowing. In contrast, the gate c ircuit must rem ain low impedance until the tail current has fallen to zero or below a level which the higher impedance V

circuit

can sink without being pulled down below –2 Volts. If the gate circuit is to be switched to a higher impedance before the tail current has reached zero then the requirements of diagram 12 must be applied.

tail

(V - i R)>2V

tail

Diagram 12.

The figure t

, as given in the characteristic data, is the maximum time required for the tail current to

decay to zero. The figure is applicable under all normal operating conditions for the device; provided suitable gate drive is employed. At lower turn-off current, or with special gate drive consider ations, this time may be reduced (each cas e needs to be considered individually).Typical turn-off losses are given in the curves of figures 13 & 14, the integration per iod f or the los ses is nominally taken to the end of the tail time (I

<1A) i.e. :-

tail

ttailtgt

dtivEoff

∫

Data Sheet. Type H0500KC25# Issue 2 Page 8 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

The curves of figure 13 give the turn-of f energy for a fixed VD with a VDM=120%VD, whereas the curves of figure 14 give the turn-off energy with a fixed value of V

and VD=50%V

. The curves are for energy

DRM

against turn-off current/snubber capacitance with a correction for voltage inset as an additional graph (snubber equivalent to diagram 2 is assumed). From these curves a typical value of turn-off energy for any combination of I off with on-state voltage (V losses in an application, the use of a maximum V frequencies) give a more realistic value. The lowest V

and VD or VDM can be derived. Only typical data is included, to allow for the trade-

TGQ/Cs

) which is a feature of these devices, see diagram 13. When calculating

and typical E

device of this type would have a maximum tur n-

will (under normal operating

off

off energy of 1.5x the figure given in the curves of figures 13 & 14.

Trade-off between V & E

off

Diagram 13.

2.8 Safe turn-off periphery The necessity to control dv/dt at tun-off for the GT O thyristor im plies a tr ade-of f between I

TGQ/VDM/Cs

. This information is given in the curves of figures 15 & 16. The information in these curves should be considered as maxim um limits and not implied operating c onditions, some margin of 'saf ety' is advised with the conditions of the curves reserved for occasional excursions. It should be noted that these cur ves are derived at maximum junction temperature, however, they may be applied across the full operating temperature range of the device provided additional precautions are taken. At very low temperature, (below –10°C) the fall-time of device becomes very rapid and can give rise to very high turn-off voltage spikes, as such it is advisable to reduce snubber loop inductance to <0.2µH to minimise this effect.

Data Sheet. Type H0500KC25# Issue 2 Page 9 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Curves

Figure 1 –Forward gate characteristics Figure 2 - On-state characteristics of Limit device

1000

H0500KC25#

Issue 2

For Tj=-40°C to +125°C

10000

H0500KC25#

Issue 2

(A)

100

Instantaneous Forward Gate Current, I

00.511.52

Instantaneous Forward Gate Voltage, V

Minimum Maximum

Figure 3 - Maximum surge and I2t Ratings

10000

25°C 125°C

(A)

1000

100

Instantaneous On-State Current, I

(V)

0123456

Instantaneous On-State Voltage, V

(V)

1.00E+06

≤

RRM

: 60% V

10V

≤

10V

RRM

1.00E+05

s) t (A

1000

I2t: V

I2t: 60% V

: V

TSM

Maximum I

Total peak half sine surge current (A)

Tj (initial) = 125°C

H0500KC25#

Issue 2

100

135101 5 10 50 100 Duration of surge (ms)

Data Sheet. Type H0500KC25# Issue 2 Page 10 of 15 August, 2004

Duration of surge (cycles @ 50H z)

1.00E+04

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Figure 4 – Transient thermal impedance

H0500KC25#

Issue 2

Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Figure 5 – Typical forward blocking voltage Vs. external gate-cathode resistance

H0500KC25#

Issue 2

, (°C/W)

0.1

thJK

0.01

Thermal Impedance Junction To Sink Z

0.001

0.001 0.01 0.1 1 10 100

Time, (s)

Figure 6 – Gate trigger current

H0500KC25#

Issue 2

Cathode

Anode

Double-side

0.2

DRM

0.4

0.6

0.8

Forward Blocking As A Ratio Of V

1.2 1 10 100 1000

External Gate-Cathode Resistance, R

Tj=125oC

Tj=100oC

Tj=25oC

ΩΩΩΩ

(

)

Figure 7 – Typical turn-on energy per pulse (excluding snubber discharge)

H0500KC25#

Issue 2

IGM=30A, diG/dt=15A/µs VD=50%V

Tj=25oC

DRM

di/dt=500A/µs

(A)

(J).

di/dt=300A/µs

Maximum

D.C. Gate Trigger Current, I

0.1

0.01

-50 -25 0 25 50 75 100 125 150

Junction Temperature, T

Data Sheet. Type H0500KC25# Issue 2 Page 11 of 15 August, 2004

(°C)

Typical

Turn-On Energy Per Pulse, E

0 300 600 900 1200

Turn-On Current, I

di/dt=100A/µs

(A)

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Figure 8 – Typical turn-on energy per pulse (including snubber discharge) Figure 9 – Maximum turn-on time

250

H0500KC25#

Issue 2

IGM=30A, diG/dt=15A/µs Cs=1µF, Rs=5

VD=0.5V

200

Tj=25oC

DRM

di/dt=500A/µs

Ω

di/dt=300A/µs

3.5

H0500KC25#

Issue 2

VD=50%V

≤

tr of I

2µs

Tj=25oC

DRM

, I

=500A

TGQ

IGM=30A

IGM=40A

(A)

di/dt=100A/µs

2.5

(µs)

Turn-On Time, t

1.5

0.5

10 100 1000

Rate Of Rise Of On-State Current, di/dt (A/ µs)

(mJ).

150

100

Turn-On Energy Per Pulse, E

0 300 600 900 1200

Turn-On Current, I

Figure 10 – Typical peak turn-off gate current Figure 11 – Maximum gate turn-off charge

(A)

250

200

H0500KC25#

Issue 2

VD=80%V Tj=125oC

diGQ/dt=40A/µs

DRM

diGQ/dt=30A/µs

diGQ/dt=20A/µs

1200

1000

(µC).

800

H0500KC25#

Issue 2

VD=80%V

DRM

Tj=125oC

20A/µs

30A/µs

40A/µs 50A/µs

IGM=50A

150

Peak Turn-Off Gate Current, I

100

0 200 400 600 800 1000

Turn-Off Current, I

Data Sheet. Type H0500KC25# Issue 2 Page 12 of 15 August, 2004

TGQ

(A)

600

400

Typical Gate Turn-Off Charge, Q

200

0 250 500 750 1000

Turn-Off Current, I

TGQ

(A)

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Figure 12 – Maximum turn-off time Figure 13 – Turn-off energy per pulse

H0500KC25#

Issue 2

VD=80%V Tj=125oC

(µs)

Turn-Off Time, t

DRM

20A/µs

30A/µs

40A/µs

50A/µs

0.5

H0500KC25#

Issue 2

VD=1200V, VDM=120%V

0.45 diGQ/dt=40A/µs

≤

0.4

0.3µH

Tj=125oC

CS=0.5µF

0.35

(J)

off

0.3

0.25

0.2

Turn-Off Energy Per Pulse, E

0.15

CS=1µF

CS=1.5µF

CS=2µF

CS=3µF

0 200 400 600 800 1000

Turn-Off Current, I

TGQ

(A)

For other values of V

0.1

scale E

0.05

1000 2000 3000

0 200 400 600 800 1000

Turn-Off Current, I

TGQ

(A)

. Note:V

off

≤

DRM

1.5

0.5

Figure 14 – Typical turn-off energy per pulse Figure 15 – Maximum permissible turn-off current

0.8

H0500KC25#

Issue 2

VDM=2000V, VD=50%V diGQ/dt=40A/µs

≤

Tj=125oC

0.6

(J)

off

0.3µH

DRM

Cs=1µF Cs=1.5µF

Cs=0.5µF

0.4

Turn-Off Energy Per Pulse, E

Note: V

0.2

For other val ues of VDM scal e E

1500 3000 4500

0 200 400 600 800 1000

Turn-Off Current, I

TGQ

(A)

Cs=2µF

Cs=3µF

≤

DRM

off

1. 5

0. 5

H0500KC25#

Issue 2

diGQ/dt=40A/µs

≤

0.3µH

2.5 Tj=125oC

120% V

≤

(µF)

1.5

VD=80%V VD=65%V

≤

Snubber Capacitance, C

0.5

0 200 400 600 800 1000

Turn-Off Current, I

TGQ

(A)

50%V

DRM DRM

DRM

Data Sheet. Type H0500KC25# Issue 2 Page 13 of 15 August, 2004

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Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

Figure 16 – Maximum turn-off current Figure 17 – Maximum tail time

1000

900

Cs=3µF

120% V

≤

H0500KC25#

Issue 2

VD=80%V

DRM

Tj=125oC

800

700

(A)

600

TGQ

500

400

Turn-Off Current, I

300

200

Tj=125oC

≤

0.3µH

diGQ/dt=40A/µs

100

H0500KC25#

Issue 2

0 0.2 0.4 0.6 0.8 1

Cs=2µF

Cs=1.4µF

Cs=1µF

Cs=0.5µF

Turn-Off Voltage A s The Ratio V

D/VDRM

Figure 18 – Minimum off-time to re-fire device

H0500KC25#

Issue 2

VD=80%V

DRM

Tj=125°C

(µs)

off

(µs)

tail

<1A), t

TGQ

Tail Time (I

0 200 400 600 800

Turn-Off Current, I

TGQ

(A)

diGQ/dt=30A/µs diGQ/dt=40A/µs

diGQ/dt=50A/µs

Minimum Off-Time To Re-Fire Device, t

0 500 1000

Turn-Off Current, I

Data Sheet. Type H0500KC25# Issue 2 Page 14 of 15 August, 2004

TGQ

(A)

WESTCODE

WESTCODEWESTCODE

An IXYS Company

Outline Drawing & Ordering Information

Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

ORDERING INFORMATION

H0500 KC

Fixed

Type Code

Typical order code: H0500KC25G – 2500V V

IXYS Semiconductor GmbH

Edisonstraße 15 D-68623 Lampertheim Tel: +49 6206 503-0 Fax: +49 6206 503-627 E-mail: marcom@ixys.de

IXYS Corporation

3540 Bassett Street Santa Clara CA 95054 USA Tel: +1 (408) 982 0700 Fax: +1 (408) 496 0670 E-mail: sales@ixys.net

The information contained herein is confidential and is protected by Copyright. The information may not be used or disclosed except with the written permission of and in the manner permitted by the proprietors Westcode Semiconductors Ltd.

In the interest of product improvement, Westcode reserves the right to change specifications at any time without prior notice. Devices with a suffix code (2-letter, 3-letter or letter/digit/letter combination) added to their generic code are not necessarily subject

to the conditions and limits contained in this report.

Fixed

Outline Code

, V

DRM

RRM

WESTCODE

IXYS

Company

www.westcode.com

www.ixys.com

♦ ♦

♦ ♦ ####

♦ ♦♦ ♦

Fixed Voltage Code

DRM

=65%V

(Please quote 10 digit code as bel ow)

Code as % of V

/100

(1625V), 37.7mm c l amp height capsule.

DRM

D=80, E=75, F=70, G=65,H=60, J=55, K =50,

L=45, M=40, N=35, P=30, R=25, S=20, T=15,

RRM

Westcode Semiconductors Ltd

Langley Park Way, Langl ey Park,

Chippenham, Wi l tshire, SN15 1GE.

E-mail: WSL.sales@westcode.com

Westcode Semiconductors Inc

E-mail: WSI.sales@westcode.com

DRM

V=10, W=5

Tel: +44 (0)1249 444524

Fax: +44 (0)1249 659448

3270 Cherry Avenue

Long Beach CA 90807 USA

Tel: +1 (562) 595 6971

Fax: +1 (562) 595 8182

Data Sheet. Type H0500KC25# Issue 2 Page 15 of 15 August, 2004

Westcode Semiconductors H0500KC25# Data Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Absolute Maximum Ratings

Characteristics

Notes on ratings and characteristics.

1. Maximum Ratings.

1.1 Off-state voltage ratings. Unless otherwise indicated, all off-state voltage ratings are given for gate conditions as diagram 1. For other gate conditions see the curves of figure 5. It should be noted that V

1.2 Reverse voltage rating. All devices in this series have a m inim um V 80%V

1.3 Peak turn-off current. The figure given in maximum ratings is the highest value for normal operation of the device under conditions given in note 2 of ratings. For other com binations of I

1.6 Snubber loop inductance. Use of GTO thyristors with snubber loop inductance, L

1.8 Gate ratings The absolute conditions above which the gate may be damaged. It is permitted to allow V off (see diagram 10) to exceed V

1.9 Minimum permissible off time. This time relates specif ically to re-firing of device (see also note on gate-off time 2.7). T he value given in the ratings applies only to operating conditions of ratings note 2. For other operating conditions see the curves of figure 18.

2 Characteristics

2.1 Instantaneous on-state voltage Measured using a 500µs square pulse, see also the curves of figure 2 for other values of I

2.4 Off-state leakage. For I

2.6 Turn-on characteristics The basic circuit used for turn-on tests is given in diagram 8. The test is initiated by establishing a circulating current in T

2.7 Turn-off characteristics The basic circuit used for the turn-off test is given in diagr am 10. Prior to the negative gate pulse being applied constant current, equivalent to I

2.8 Safe turn-off periphery The necessity to control dv/dt at tun-off for the GT O thyristor im plies a tr ade-of f between I

Curves

Figure 1 –Forward gate characteristics Figure 2 - On-state characteristics of Limit device

Figure 3 - Maximum surge and I2t Ratings

Figure 4 – Transient thermal impedance

Figure 5 – Typical forward blocking voltage Vs. external gate-cathode resistance

Figure 6 – Gate trigger current

Figure 7 – Typical turn-on energy per pulse (excluding snubber discharge)

Figure 8 – Typical turn-on energy per pulse (including snubber discharge) Figure 9 – Maximum turn-on time

Figure 10 – Typical peak turn-off gate current Figure 11 – Maximum gate turn-off charge

Figure 12 – Maximum turn-off time Figure 13 – Turn-off energy per pulse

Figure 14 – Typical turn-off energy per pulse Figure 15 – Maximum permissible turn-off current

Figure 16 – Maximum turn-off current Figure 17 – Maximum tail time

Figure 18 – Minimum off-time to re-fire device

Outline Drawing & Ordering Information