Wadia 121Decoding Computer Overview
A Definition
What is a 121Decoding Computer?
The Wadia 121Decoding Computer is a small form factor digital-to-analog converter with
digital pre-amplifier capabilities. It is designed to function as the control center for playback
of digital audio sources.
At Wadia we refer to our digital-to-analog converters (DAC’s) as Decoding Computers. This
is because in function our DAC’s work in much the same way as a personal computer (PC).
We write software programs for our DAC’s that run on powerful multi-purpose processors to
accomplish a task (in this case decoding and perfecting digital audio waveforms). Digital audio
data received from a source, is buffered in memory, and then processed via our software and
circuit designs, much in much the same way as a conventional computer.
The 121Decoding Computer
Although diminutive in form, the 121 Decoding Computer was developed using the same
design principles and philosophy that has shaped our reference level products. Remarkably
for its size and cost, the 121 features several core Wadia technologies including: DigiMaster
upsampling algorithm, SwiftCurrent current to voltage conversion, ClockLink and ClockLock
jitter reduction, and DirectConnect with 32-bit Digital Volume Control.
The 121 is comprised of 8 main sections – Digital Input’s, Clocking, Digital Processing,
Digital-to-Analog conversion, Current-to-Voltage conversion, Variable Output stages, Power
supply, and User Interface. The following document will provide you with a brief overview of
how each of these sections works and integrates together to create a true Wadia DAC.
Digital Inputs
The 121Decoding Computer has five digital inputs each capable of receiving and decoding
data rates of up to 24-bits and 192 kHz sample rate in AES/EBU, S/PDIF, and USB formats.
Inputs include:
• AES/EBU (XLR)
• S/PDIF Coax (BNC and RCA)
• Toslink
• USB (B)
Clocking
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The 121 inputs employ one of two Wadia jitter-reduction technologies: ClockLink for USB
and ClockLock.
ClockLink for USB
The Wadia 121 features a new implementation of Wadia’s traditional jitter reduction technology
in the form of a USB input featuring dedicated internal ClockLink.
As in previous versions, the function of ClockLink is to position a master oscillator as near as
possible to the D>A converter chip to reduce transmission-induced jitter. All upstream sources
are then synchronized to the DAC’s oscillator clock signal. With USB Internal ClockLink, instead
of using a clock embedded in the incoming data stream (isochronous audio), a high performance
fixed frequency oscillator located at the point of conversion to analog is used. In the case
of the 121 USB input, the receiver is Asynchronous in function. This means that the 121 is
controlling requests for audio data from your computer. The 121 is managing a buffer and
requesting data from the connected PC as needed to keep the buffer at an optimal level. Our
fixed oscillator located at the DAC is controlling the rate that data is depleted from this buffer
and in effect initiating the requests for additional audio data from the PC. The net result is
that the jitter laden source clock can be ignored and the high performance 121 DAC oscillator
is the only clock used in the conversion to analog process eliminating time related distortions.
DACUSB Receiver
Data to DacData from Computer
USB Receiver
with Buffer
Request for AudioData Clock to USB Receiver
▼
▼
Digital
Filter
DAC
Master
Clock
Output
ClockLock
ClockLock is a Wadia proprietary circuit implemented in a Field Programmable Gate Array that
virtually eliminates jitter from any standard digital source. ClockLock is utilized on all inputs
on the 121 other than USB. It works by monitoring the incoming clock frequency and then
adjusting its DAC oscillator clock to match the incoming rate. Once the two clocks are aligned
the DAC clock is locked into a fixed jitter free mode. The incoming clocking information is then
monitored but not used. A large buffer prior to the DAC oscillator ensures that no data is lost
due to small changes in the incoming rate. The benefit again is that the jitter laden source
clock can be bypassed and the high performance 121 DAC oscillator can be locked into a fixed
position and be the only clock used in the conversion to analog process.
W a d i a D i g i t a l
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Digital Processing
Field Programmable Gate Array (FPGA)
All inputs and outputs in the 121 Decoding Computer are routed to a large field-programmable
gate array (FPGA) on the main control board. With 8256 logic cells, or gates, this gate array
provides tremendous flexibility for digital signal processing and routing. The gate array performs
several operations on the data, including DSP functions.
Some of the functional blocks programed into the FPGA include:
• Input source signal selection and multiplexing
• USB master clock provisioning (logic, dividers and distribution)
• Digital Audio Receiver (DAR) I2S connection
• Clocking Control
• DAC I2S connection, DAC clocking
DSP Capability
The FPGA is configured so that a dedicated DSP block is created that performs all data
processing including execution of the DigiMaster interpolation upsampling algorithm.
DigiMaster 4 Interpolation Filter
The Wadia 121 features a new generation of Wadia’s proprietary interpolating digital filtering
system known as DigiMaster. The DigiMaster 4 Waveform Algorithm for the 121 has been
optimized for a wide range of performance parameters. Incoming data samples are reconstructed
with special emphasis placed on time and phase accuracy so that it is able to recreate the
subtle musical presence and details.
W a d i a D i g i t a l
The DigiMaster 4 interpolator uses a curve fitting spline interpolation algorithm to precisely
reconstruct the original analog waveform. Using digital signal processing (DSP), a curve is
fitted that conforms to the current sample plus future and prior samples.
DigiMaster 4 operates at the rate of 4-times re-sampling of 44.1 kHz, that is, 4 interpolated
values are calculated for each original sample from the source. Although DigiMaster 4 calculates
the interpolated samples using 64-bit calculations to 32-bit precision, the original data samples
from the source are not altered in any way (as shown in the illustration below).
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