VXI Technology VM1548C User Manual

VM1548C

TTL I/O MODULE

USER’S MANUAL

P/N: 82-0045-000

Released July 31, 2007

VXI Technology, Inc.

2031 Main Street

Irvine, CA 92614-6509

[phone]

bus

2

www.vxitech.com

TABLE OF CONTENTS

INTRODUCTION

Certification..........................................................................................................................................................6

Warranty ...............................................................................................................................................................6

Limitation of Warranty.........................................................................................................................................6

Restricted Rights Legend......................................................................................................................................6

Declaration of Conformity....................................................................................................................................7

Terms and Symbols .............................................................................................................................................. 8

Warnings ..............................................................................................................................................................8

SECTION 1..................................................................................................................................................................11

INTRODUCTION .......................................................................................................................................................11

Introduction ........................................................................................................................................................11

Features...............................................................................................................................................................12

Description .........................................................................................................................................................13

Programming and Data Access...........................................................................................................................13

VM1548 Specifications ......................................................................................................................................15

SECTION 2..................................................................................................................................................................17

PREPARATION FOR USE...........................................................................................................................................17

Installation .......................................................................................................................................................... 17

Calculating System Power and Cooling Requirements ......................................................................................17

Setting the Chassis Backplane Jumpers..............................................................................................................17

Setting the Logical Address................................................................................................................................18

Front Panel Interface Wiring .............................................................................................................................. 19

SECTION 3..................................................................................................................................................................20

PROGRAMMING....................................................................................................................................................... 20

Introduction ........................................................................................................................................................20

Notation ..............................................................................................................................................................22

EXAMPLES OF SCPI COMMANDS ............................................................................................................................23

TTLTRIG Circuit ...............................................................................................................................................23

Interrupt Circuit ..................................................................................................................................................24

Output Register Circuit.......................................................................................................................................25

Input Register Circuit .........................................................................................................................................26

Bi-directional Clock Circuit ...............................................................................................................................27

APPLICATION EXAMPLES ........................................................................................................................................28

Write Mode.........................................................................................................................................................28

Read Mode..........................................................................................................................................................30

Write/Read Mode ...............................................................................................................................................33

REGISTER ACCESS EXAMPLES ................................................................................................................................37

VXIPLUG&PLAY EXAMPLES ...................................................................................................................................39

SECTION 4..................................................................................................................................................................45

COMMAND DICTIONARY......................................................................................................................................... 45

Introduction ........................................................................................................................................................45

Alphabetical Command Listing..........................................................................................................................45

Terminology ....................................................................................................................................................... 46

Command Dictionary..........................................................................................................................................50

IEEE 488.2 COMMON COMMANDS .........................................................................................................................51

*CLS................................................................................................................................................................... 51

*ESE...................................................................................................................................................................52

*ESR?.................................................................................................................................................................53

*IDN? ................................................................................................................................................................. 54

VM1548C Preface 3

VXI Technology, Inc.

*OPC ..................................................................................................................................................................55

*RST................................................................................................................................................................... 56

*STB?.................................................................................................................................................................57

*TRG ..................................................................................................................................................................58

*TST...................................................................................................................................................................59

*WAI ..................................................................................................................................................................60

INSTRUMENT SPECIFIC SCPI COMMANDS...............................................................................................................61

FORMat..............................................................................................................................................................61

INPut:REGister:POLarity................................................................................................................................... 62

INPut:REGister:SOURce ...................................................................................................................................63

INPut:TTLTrig ...................................................................................................................................................64

INPut:TTLTrig:STATE......................................................................................................................................65

OUTPut:CLOCk:ENABle ..................................................................................................................................66

OUTPut:CLOCk:POLarity.................................................................................................................................67

OUTPut:CLOCk:SOURce..................................................................................................................................68

OUTPut:REGister:POLarity............................................................................................................................... 69

OUTPut:REGister:SOURce ...............................................................................................................................70

OUTPut:TTLTrig ...............................................................................................................................................71

OUTPut:TTLTrig:POLarity ...............................................................................................................................72

OUTPut:TTLTrig:SOURce ................................................................................................................................73

OUTPut:TTLTrig:STATE..................................................................................................................................74

READ? ...............................................................................................................................................................75

READ? CLOCks ................................................................................................................................................76

READ? CONTrol ...............................................................................................................................................77

READ? ISENse ..................................................................................................................................................78

RESet:ISENse.....................................................................................................................................................79

SOURce:DATA.................................................................................................................................................. 80

SOURce:DATA:ENABle...................................................................................................................................81

SOURce:DATA:POLarity..................................................................................................................................82

STATus:INTerrupt:ENABle ..............................................................................................................................83

STATus:INTerrupt:NTRansition........................................................................................................................84

STATus:INTerrupt:PTRansition ........................................................................................................................85

TRIGger:SEQuence:IMMediate......................................................................................................................... 86

SCPI REQUIRED COMMANDS..................................................................................................................................87

STATus:OPERation? .........................................................................................................................................87

STATus:OPERation:CONDition?......................................................................................................................88

STATus:OPERation:ENABle.............................................................................................................................89

STATus:PRESet .................................................................................................................................................90

STATus:QUEStionable:CONDition?................................................................................................................. 91

STATus:QUEStionable:ENABle .......................................................................................................................92

STATus:QUEStionable:EVENt?........................................................................................................................93

SYSTem:ERRor? ...............................................................................................................................................94

SYSTem:VERSion? ...........................................................................................................................................95

SECTION 5..................................................................................................................................................................97

THEORY OF OPERATION.......................................................................................................................................... 97

Introduction ........................................................................................................................................................97

VXI INTERFACE......................................................................................................................................................98

Device Transfers (Write Mode).......................................................................................................................... 98

Direction .............................................................................................................................................................98

Clock Enable ......................................................................................................................................................98

Data Load ...........................................................................................................................................................99

Device Triggering (TTL Input Trigger) ...........................................................................................................100

Trigger Decode.................................................................................................................................................100

Trigger Select ...................................................................................................................................................100

Device Transfers (Read Mode).........................................................................................................................102

Direction ...........................................................................................................................................................102

4 VM1548C Preface

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Clock Enable ....................................................................................................................................................102

Latch Data ........................................................................................................................................................103

Read Data .........................................................................................................................................................104

INDEX.......................................................................................................................................................................105

VM1548C Preface 5

VXI Technology, Inc.

CERTIFICATION

VXI Technology, Inc. (VTI) certifies that this product met its published specifications at the time of shipment from
the factory. VTI further certifies that its calibration measurements are traceable to the United States National
Institute of Standards and Technology (formerly National Bureau of Standards), to the extent allowed by that
organization’s calibration facility, and to the calibration facilities of other International Standards Organization
members.

WARRANTY

The product referred to herein is warranted against defects in material and workmanship for a period of three years
from the receipt date of the product at customer’s facility. The sole and exclusive remedy for breach of any warranty
concerning these goods shall be repair or replacement of defective parts, or a refund of the purchase price, to be
determined at the option of VTI.

For warranty service or repair, this product must be returned to a VXI Technology authorized service center. The
product shall be shipped prepaid to VTI and VTI shall prepay all returns of the product to the buyer. However, the
buyer shall pay all shipping charges, duties, and taxes for products returned to VTI from another country.

VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming
when properly installed on that product. VTI does not however warrant that the operation of the product, or
software, or firmware will be uninterrupted or error free.

LIMITATION OF WARRANTY

The warranty shall not apply to defects resulting from improper or inadequate maintenance by the buyer, buyer­supplied products or interfacing, unauthorized modification or misuse, operation outside the environmental
specifications for the product, or improper site preparation or maintenance.

VXI Technology, Inc. shall not be liable for injury to property other than the goods themselves. Other than the
limited warranty stated above, VXI Technology, Inc. makes no other warranties, express or implied, with respect to
the quality of product beyond the description of the goods on the face of the contract. VTI specifically disclaims the
implied warranties of merchantability and fitness for a particular purpose.

RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subdivision (b)(3)(ii) of
the Rights in Technical Data and Computer Software clause in DFARS 252.227-7013.

VXI Technology, Inc.
2031 Main Street
Irvine, CA 92614-6509 U.S.A.

6 VM1548C Preface

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D ECLARATION OF C ONFORMITY

Declaration of Conformity According to ISO/IEC Guide 22 and EN 45014

ANUFACTURER’S NAME VXI Technology, Inc.

M

ANUFACTURER’S ADDRESS 2031 Main Street

M

Irvine, California 92614-6509

RODUCT NAME TTL I/O Module

P

ODEL NUMBER(S) VM1548C

M

RODUCT OPTIONS All

P

RODUCT CONFIGURATIONS All

P

VXI Technology, Inc. declares that the aforementioned product conforms to the requirements of
the Low Voltage Directive 73/23/EEC and the EMC Directive 89/366/EEC (inclusive 93/68/EEC)
and carries the “CE” mark accordingly. The product has been designed and manufactured
according to the following specifications:

AFETY EN61010 (2001)

S

EMC EN61326 (1997 w/A1:98) Class A

CISPR 22 (1997) Class A
VCCI (April 2000) Class A
ICES-003 Class A (ANSI C63.4 1992)
AS/NZS 3548 (w/A1 & A2:97) Class A
FCC Part 15 Subpart B Class A
EN 61010-1:2001

The product was installed into a C-size VXI mainframe chassis and tested in a typical configuration.

I hereby declare that the aforementioned product has been designed to be in compliance with the relevant sections
of the specifications listed above as well as complying with all essential requirements of the Low Voltage Directive.

July 2007

VM1548C Preface 7

Steve Mauga, QA Manager

Review the following safety precautions to avoid bodily injury and/or damage to the product.
These precautions must be observed during all phases of operation or service of this product.
Failure to comply with these precautions, or with specific warnings elsewhere in this manual,
violates safety standards of design, manufacture, and intended use of the product.

Service should only be performed by qualified personnel.

TERMS AND SYMBOLS

These terms may appear in this manual:

WARNING

CAUTION

These symbols may appear on the product:

VXI Technology, Inc.

GENERAL SAFETY INSTRUCTIONS

Indicates that a procedure or condition may cause bodily injury or death.

Indicates that a procedure or condition could possibly cause damage to
equipment or loss of data.

ATTENTION - Important safety instructions

WARNINGS

Frame or chassis ground

Indicates that the product was manufactured after August 13, 2005. This mark is
placed in accordance with EN 50419, Marking of electrical and electronic
equipment in accordance with Article 11(2) of Directive 2002/96/EC (WEEE).
End-of-life product can be returned to VTI by obtaining an RMA number. Fees
for take-back and recycling will apply if not prohibited by national law.

Follow these precautions to avoid injury or damage to the product:

Use Proper Power Cord

Use Proper Power Source

Use Proper Fuse

To avoid hazard, only use the power cord specified for this product.

To avoid electrical overload, electric shock, or fire hazard, do not
use a power source that applies other than the specified voltage.

To avoid fire hazard, only use the type and rating fuse specified for
this product.

8 VM1548C Preface

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WARNINGS (CONT.)

Avoid Electric Shock

Ground the Product

Operating Conditions

Improper Use

To avoid electric shock or fire hazard, do not operate this product
with the covers removed. Do not connect or disconnect any cable,
probes, test leads, etc. while they are connected to a voltage source.
Remove all power and unplug unit before performing any service.

Service should only be performed by qualified personnel.

This product is grounded through the grounding conductor of the
power cord. To avoid electric shock, the grounding conductor must
be connected to earth ground.

To avoid injury, electric shock or fire hazard:

- Do not operate in wet or damp conditions.

- Do not operate in an explosive atmosphere.

- Operate or store only in specified temperature range.

- Provide proper clearance for product ventilation to prevent
overheating.

- DO NOT operate if any damage to this product is suspected.

Product should be inspected or serviced only by qualified
personnel.

The operator of this instrument is advised that if the equipment is
used in a manner not specified in this manual, the protection
provided by the equipment may be impaired.
Conformity is checked by inspection.

VM1548C Preface 9

VXI Technology, Inc.

SUPPORT RESOURCES

Support resources for this product are available on the Internet and at VXI Technology customer
support centers.

VXI Technology
World Headquarters

VXI Technology, Inc.
2031 Main Street
Irvine, CA 92614-6509

Phone: [phone]
Fax: [phone]

VXI Technology
Cleveland Instrument Division

5425 Warner Road
Suite 13
Valley View, OH 44125

Phone: [phone]
Fax: [phone]

VXI Technology
Lake Stevens Instrument Division

VXI Technology, Inc.
1924 - 203 Bickford
Snohomish, WA 98290

Phone: [phone]
Fax: [phone]

Technical Support

Phone: [phone]
Fax: [phone]
E-mail:

Visit

[e-mail]

http://www.vxitech.com for worldwide support sites and service plan information.

10 VM1548C Preface

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A

V

V

V

SECTION 1

INTRODUCTION

INTRODUCTION

The VM1548C is a high-performance I/O module that has been designed for high data throughput
and flexibility of configuration. The instrument uses the message-based word serial interface for
programming and data movement as well as allowing direct register access for very high-speed
data input and retrieval. The VM1548C command set conforms to the SCPI standard for
consistency and ease of programming.

The VM1548C is a member of the VXI Technology VMIP™ (VXI Modular Instrumentation
Platform) family and is available as a 48-, 96-, or 144-channel, singlewide VXIbus instrument.

Figure 1-1 and Figure 1-2 show the 144-channel version of the VM1548C. The 96-channel
version would not have J200 and its associated LED’s and nomenclature while the 48-channel
version would eliminate J202 as well. In addition to these three standard configurations, the
VM1548C may be combined with any of the other members of the VMIP family to form a
customized and highly integrated instrument (see
system size and cost by combining the VM1548C with two other instrument functions in a single
wide, C-size VXIbus module.

Figure 1-1). This allows the user to reduce

V
X

I
B
U
S

MIP

INTERFACE

IGURE 1-1: VMIP™ PLATFORM

F

N
T
E
R
N

L

M
P
B

U
S

MIP

INSTRUMENT

MODULE #1

I

MIP

INSTRUMENT

V
I

MODULE #2

VMIP

INSTRUMENT

MODULE #3

VM1548C Introduction 11

ACC/

ERR

J200

ERR

J201

ERR

J202

bus

FAIL

FAILACC/

FAILACC/

VXI Technology, Inc.

Regardless of whether the VM1548C is configured with other VM1548C modules or
with other VMIP modules, each group of 48 channels is treated as an independent
instrument in the VXIbus chassis and as such, each group has its own FAIL/POWER
and ACCESS/ERROR indicators.

FEATURES

• 48 channels, 6 groups of 8 bits. Up to 144 channels in a single C-size card.

• Group-wise programmable, as an input or an output, through user TTL input or VXI

A16 registers.

• Group-wise programmable polarity through VXI A16 registers as an active high or

low.

• Input: 0 V to 60 V, V

IN(high)

≥ 2.0 V, V

• Output: Open collector (N-DMOS), 0 V to 60 V, up to 300 mA continuous with

over-voltage and over-current protection.

• Data throughput: 5 µs typical system speeds, 200 kilobytes (kB) per second using

D8 access, 400 kB per second using D16 access.

• Data Input/Output Clock Sources: For each group, from Front Panel clock input,

VXI TTL Trigger lines, or word serial event (command).

• Capture clock edge programmable as rising edge or falling edge.

• ASCII, Hex, Octal, and Binary data output types.

• Message or Register based data access.

• SCPI compatible.

≤ 1.5 V, input impedance ≥ 65 kΩ.

IN(low)

IGURE 1-2: FRONT PANEL LAYOUT

F

12 VM1548C Introduction

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DESCRIPTION

The VM1548C Open Collector Digital I/O module is a high performance I/O module that has
been designed for high voltage, current, and data throughput. The instrument uses the message­based word serial interface for programming and data movement as well as allowing direct
register access for very high-speed.

The VM1548C provide 48 open-collector digital I/O line that are configurable as input or output
in six groups of eight channels each. The module can drive up to 60 V with sink current of up to
300 mA per channel. Each group of 8 bits can be configured as an input or an output under
program control. The VM1548C has the flexibility to source the input and output clocks from
either the front panel (one input per group of 8 bits), the backplane TTL Trigger bus or via a word
serial command. By using the appropriate clocking sources, very large numbers of channels may
by synchronized to collect or present data to a UUT (unit under test).

Each clock input is internally pulled to a logic high level and has a RC termination network to
reduce multiple clocking due to line ringing. The RC network consists of a 120 Ω resistor in series
with a 100 pF capacitor, giving a time constant of 12 ns.

The VM1548C can be combined with any member of the VMIP family to form a customized and
highly integrated instrument.

PROGRAMMING AND DATA ACCESS

The data may be read or loaded by one of two different methods:

Word Serial Message-based Data Access: In this mode, the input or output data and all other

functions are accessed via the VXI message-based
interface. Commands are sent to set the I/O ports
as well as to initiate functions such as triggering an
update or to query a port’s input state. This data
access method is very clean from a programming
perspective, but it is also the slowest of the data
access modes.

Register-Based Data Access: This mode offers the fastest throughput. The I/O

ports are directly mapped into the VXI user
definable registers. Data access occurs in
approximately 500 ns, depending on the controller
and software used.

VM1548C Introduction

13

VXI Technology, Inc.

FRONT
PANEL

22

DATA I/O

WRITE
DATA

A

DQDQ

CLKOUTENA

ISENSE

B

DAMPING

RESISTOR

VMIP BUSVXI BACKPLANE

TTL TIGGER 0-7

8:1

SELECT

READ
DATA

8:1

SELECT

A
B

TTL
TRIGGER
SELECT

1:3

SELECT

TTL TRIG
OUT SEL

F

IGURE 1-3: VM1548C MODULE BLOCK DIAGRAM

A
B

3:1

MUX

3:1

MUX

3:1

MUX

CLKINENA

CLK OUT

SEL

CLK IN

SEL

CLKOUTENA

QD

OUTENA

47K

I/O*

47K

CLOCK

120

100pF

14 VM1548C Introduction

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VM1548 SPECIFICATIONS

GENERAL SPECIFICATIONS

NUMBER OF CHANNELS
VM1548C-1
VM1548C-2
VM1548C-3
DIRECTION

DATA THROUGHPUT

48, 6 groups of 8 bits
96, 12 groups of 8 bits
144, 18 groups of 8 bits

bi-directional

5 µs typical system (500 µs register cycle time)
200 kB/s using D8 access
400 kB/s using D16 access

PHYSICAL INTERFACE

N channel DMOS transistor (TPIC2601KTC) with a current protection circuit on
the output side, and a voltage divider and voltage comparator on the input side

CHANNEL INPUT CHARACTERISTICS
V
V
V
Input Impedance

IN(high)
IN(low)
IN(max)

≥ 2.0 V
≤ 1.5 V
≤ 60 V
≥ 65 kΩ

CHANEL OUTPUT CHARACTERISTICS
V

OUT(max)

Current Sink (Max.)
Switch On Time

≤ 60 V
≤ 300 mA
≤ 1 µs

CLOCK AND CONTROL INPUT CHARACTERISTICS
V
V

IN(high)
IN(low)

Current In (VIN = 5.0 V)

> 2.0 V
< 0.8 V
< 10 µA

DATA INPUT CLOCK SOURCES

6 front panel
TTL trigger bus (0 - 7)
word serial command

TTL TRIGGER OUTPUT SOURCES

CLOCKED INPUT DATA SETUP

Front Panel Clock inputs (0 - 5)

≥ 2 µs

CLOCKED INPUT DATA HOLD

≥ 0

CLOCKED DATA OUTPUT SKEW

POWER REQUIREMENTS

≤ 2 µs

+5 V @ 864 mA, +12 V @ 60 mA

COOLING REQUIREMENTS
VM1548C-1
VM1548C-2
VM1548C-3

0.4 L/s

0.8 L/s

1.2 L/s

VM1548C Introduction

15

VXI Technology, Inc.

16 VM1548C Introduction

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SECTION 2

PREPARATION FOR USE

INSTALLATION

When the VM1548C is unpacked from its shipping carton, the contents should include the
following items:

(1) VM1548C VXIbus module
(1) VM1548C Open Collector Digital I/O Module User’s Manual (this manual)

All components should be immediately inspected for damage upon receipt of the unit.

Once the VM1548C is assessed to be in good condition, it may be installed into an appropriate
C-size or D-size VXIbus chassis in any slot other than slot 0. The chassis should be checked to
ensure that it is capable of providing adequate power and cooling for the VM1548C. Once the
chassis is found to be adequate, the VM1548C’s logical address and the chassis’ backplane
jumpers should be configured prior to the VM1548C’s installation.

CALCULATING SYSTEM POWER AND COOLING REQUIREMENTS

The power and cooling requirements of the VM4018 are given in the Specifications section of
Section 1 in this manual. It is imperative that the chassis provide adequate power and cooling for
this module. Referring to the chassis User’s Manual, confirm that the power budget for the system
(the chassis and all modules installed therein) is not exceeded and that the cooling system can
provide adequate airflow at the specified backpressure.

It should be noted that if the chassis cannot provide adequate power to the module, the instrument
might not perform to specification or possibly not operate at all. In addition, if adequate cooling is
not provided, the reliability of the instrument will be jeopardized and permanent damage may
occur. Damage found to have occurred due to inadequate cooling will void the warranty on the
instrument in question.

SETTING THE CHASSIS BACKPLANE JUMPERS

Please refer to the chassis User’s Manual for further details on setting the backplane jumpers.

VM1548C Preparation for Use 17

SETTING THE LOGICAL ADDRESS

The logical address of the VM1548C is set by a single 8-position DIP switch located near the
module’s backplane connectors (this is the only switch on the module). The switch is labeled with
positions 1 through 8 and with an ON position. A switch pushed toward the ON legend will signify
a logic 1; switches pushed away from the ON legend will signify a logic 0. The switch located at
position 1 is the least significant bit while the switch located at position 8 is the most significant
bit. See

Figure 2-1 for examples of setting the logical address switch.

VXI Technology, Inc.

ON ON

1ON2345678

SET TO 4

ON ON

12345678

SET TO 168

F

IGURE 2-1: LOGICAL ADDRESS SWITCH SETTING EXAMPLES

1ON2345678

SET TO 8

1

2345678

SET TO 255

(Dynamic)

Switch

Position

1
2
3
4
5
6
7
8

Switch

Value

1
2
4
8

16
32
64

128

The VMIP may contain three separate instruments and will allocate logical addresses as required
by the VXIbus specification (revisions 1.3 and 1.4). The logical address of the instrument is set on

the VMIP carrier. The VMIP logical addresses must be set to an even multiple of 4 unless dynamic
addressing is used. Switch positions 1 and 2 must always be set to the OFF position. Therefore,

only addresses of 4, 8, 12, 16, ...252 are allowed. The address switch should be set for one of these
legal addresses and the address for the second instrument (the instrument in the center position)
will automatically be set to the switch set address plus one; while the third instrument (the
instrument in the lowest position) will automatically be set to the switch set address plus two. If
dynamic address configuration is desired, the address switch should be set for a value of 255 (All
switches set to ON). Upon power-up, the slot 0 resource manager will assign the first available
logical addresses to each instrument in the VMIP module.

If dynamic address configuration is desired, the address switch should be set for a value of 255.
Upon power-up, the slot 0 resource manager will assign logical addresses to each instrument in the
VMIP module.

18 VM1548C Preparation for Use

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FRONT PANEL INTERFACE WIRING

The VM1548C’s module interface is made available on the front panel of the instrument. The
48-channel version (VM1548C-1) will have J201, which contains all signals for this instrument.
The 96-channel version (VM1548C-2) will have J201 and J202 provided, while the 144-channel
version (VM1548C-3) will have J200, J201 and J202. The wiring for each of these connectors is
identical and since each group of 48 channels is treated as a separate instrument, the module will
have three Channel 1s, three Channel 2s, three Channel 3s, etc.

The connector used in the VM1548C is a readily available 68-pin high-density type commonly
known as a 68-pin version of the SCSI 2 connector. The mating connector is an IDC (Insulation
Displacement Connector) component and is available from a variety of sources. The connector
attaches to two 34-conductor 0.050 centers ribbon cable, and the pin out has been selected to allow
for using the twisted pair type of ribbon cable. Some manufacturers also allow the use of discrete
30 gauge stranded wires.

ABLE 2-1: J200, J201 AND J202 PIN OUTS

T

PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL

1 GND 18 DATA1.5 35 GND 52 DATA4.5
2 DATA0.0 19 DATA1.6 36 DATA3.0 53 DATA4.6
3 DATA0.1 20 DATA1.7 37 DATA3.1 54 DATA4.7
4 DATA0.2 21 I/O*1 38 DATA3.2 55 I/O*4
5 DATA0.3 22 CLK1 39 DATA3.3 56 CLK4
6 DATA0.4 23 GND 40 DATA3.4 57 GND
7 DATA0.5 24 DATA2.0 41 DATA3.5 58 DATA5.0
8 DATA0.6 25 DATA2.1 42 DATA3.6 59 DATA5.1

9 DATA0.7 26 DATA2.2 43 DATA3.7 60 DATA5.2
10 I/O*0 27 DATA2.3 44 I/O*3 61 DATA5.3
11 CLK0 28 DATA2.4 45 CLK3 62 DATA5.4
12 GND 29 DATA2.5 46 GND 63 DATA5.5
13 DATA1.0 30 DATA2.6 47 DATA4.0 64 DATA5.6
14 DATA1.1 31 DATA2.7 48 DATA4.1 65 DATA5.7
15 DATA1.2 32 I/O*2 49 DATA4.2 66 I/O*5
16 DATA1.3 33 CLK2 50 DATA4.3 67 CLK5
17 DATA1.4 34 GND 51 DATA4.4 68 GND

VM1548C Preparation for Use 19

VXI Technology, Inc.

The mating connector to J200, J201 or J202 is available from the following companies:

AMP Inc.

P/N 749111-6 Connector
P/N 749204-2 Back Shell
P/N 82208 Catalog covering this series of connectors

Circuit Assembly

P/N CA-68NDP-12GT Connector
P/N CA-68NDBS-1M Back Shell
P/N DG01 Catalog covering this series of connectors

The pin locations for J200, J201, and J202 are shown in

PIN 1 PIN 35

Figure 2-2.

PIN 34

F

IGURE 2-2: J200, J201, AND J202 PIN LOCATIONS

PIN 68

SECTION 3

PROGRAMMING

INTRODUCTION

The VM1548C is a VXIbus message-based device whose command set is compliant with the
Standard Command for Programmable Instruments (SCPI) programming language.

20 VM1548C Preparation for Use

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All module commands are sent over the VXIbus backplane to the module. Commands may be in
upper, lower, or mixed case. All numbers are sent in ASCII decimal unless otherwise noted.

The module recognizes SCPI commands. SCPI is a tree-structured language based on IEEE-STD-

488.2 Specifications. It utilizes the IEEE-STD-488.2 Standard command, and the device
dependent commands are structured to allow multiple branches off the same trunk to be used
without repeating the trunk. To use this facility, terminate each branch with a semicolon.

See the Standard Command for Programmable Instruments (SCPI) Manual, Volume 1: Syntax &

Style, Section 6, for more information.

The SCPI commands are listed in upper and lower case. Character case is used to indicate
different forms of the same command. Keywords can have both a short form and a long form
(some commands only have one form). The short form uses just the keyword characters in
uppercase. The long form uses the keyword characters in uppercase plus the keyword characters
in lowercase. Either form is acceptable. Note that there are no intermediate forms. All characters
of the short form or all characters of the long form must be used. Short forms and long forms may
be freely intermixed. The actual commands sent can be in upper case, lower case, or mixed case
(case is only used to distinguish short and long form for the user). As an example, these
commands are all correct and all have the same effect:

TRIGger:SEQuence:IMMediate
trigger:sequence:immediate
TRIGGER:SEQUENCE:IMMEDIATE
TRIG:SEQuence:IMMediate
TRIG:SEQ:IMMediate
TRIG:SEQ:IMM
trig:seq:IMM
trig:seq:imm

VM1548C Programming 21

NOTATION

VXI Technology, Inc.

The following command is not correct because it uses part of the long form of TRIGger, but not

all the characters of the long form:

trigg:seq:imm (incorrect syntax - extra "g"- only trig or trigger is correct)

All of the SCPI commands also have a query form unless otherwise noted. Query forms contain a
question mark (?). The query form allows the system to ask what the current setting of a
parameter is. The query form of the command generally replaces the parameter with a question
mark (?). Query responses do not include the command header. This means only the parameter is
returned: no part of the command or "question" is returned.

Keywords or parameters enclosed in square brackets ([ ]) are optional. If the optional part is a
keyword, the keyword can be included or left out. Omitting an optional parameter will cause its
default to be used.

Parameters are enclosed by angle brackets (< >). Braces ({ }), or curly brackets, are used to
enclose one or more parameters that may be included zero or more times. A vertical bar (|), read
as "or", is used to separate parameter alternatives.

22 VM1548C Programming

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EXAMPLES OF SCPI COMMANDS

TTLTRIG CIRCUIT

A multiplexer is used to select 1 of 8 different sources as TTLTRIG. The signal is selected using
the following SCPI command:

OUTPut:TTLTrig:SOURce <source> Where <source> refers to one of

The selected signal is called GLOBAL (TRIGOUT) and after a polarity control, it is called
TTLTRIGGER, which is presented on the VXIbus as the selected TTLTRIG0-7. The specific

TTLTRIG line is selected using the following SCPI command:

OUTPut:TTLTrig <n> Where <n> refers to one of the 8

The TTLTRIGGER is enabled or disabled using the following SCPI command:

OUTPut:TTLTrig:STATe ON Enables the Trigger
OUTPut:TTLTrig:STATe OFF Disables the Trigger

The following is an example of how to produce CLK2 as TTLTRIG4 to the backplane:

OUTPut:TTLTrig:STATe ON
OUTPut:TTLTrig:POLarity NORMal
OUTPut:TTLTrig 4
OUTPut:TTLTrig:SOURce EXTERNAL2

If CLK2 is a logic low level, then the following SCPI command would allow a logic high level on
the backplane.

OUTPut:TTLTrig:POLarity INVERT TTLTRIG 4 will not pull the line

Likewise, continuing with this example, the following command would produce a logic low level
on the backplane.

OUTPut:TTLTrig:POLarity NORMal TTLTRIG 4 will pull the line low

the EXTERNAL CLK lines (CLK0-

5), IMMEDIATE or NONE.

TTLTRIG lines.

low

VM1548C Programming 23

INTERRUPT CIRCUIT

This section deals with the interrupt circuit. The VM1548C has the capability to interrupt the slot
0 controller via the VMIP with either a high going edge or with a low going edge of the IRQ*
signal. The timing and control circuitry can select one of the six EXTERNAL clocks, GLOBAL
(TRIGOUT) or NONE as the interrupt trigger. The interrupt is selected and enabled using the
following SCPI command:

STATus:INTerrupt:ENABle <source> Where <source> is EXTERNAL0-

The following SCPI command will trigger the status interrupt on a positive edge:

STATus:INTerrupt:PTRansition ON

The following SCPI command will trigger the status interrupt on a negative edge:

STATus:INTerrupt:NTRansition ON

EXAMPLES

To use GLOBAL (TRIGOUT) out as the status interrupt trigger, the following SCPI command
would be issued:

STATus:INTerrupt:ENABle GLOBAL

To trigger the status interrupt from a negative going edge external clock source from port 3, the
following SCPI commands would be issued:

STATus:INTerrupt:ENABle EXTERNAL3
STATus:INTerrupt:NTRansition ON

To trigger the status interrupt from a negative edge going external clock source from port 1, the
following SCPI commands would be issued:

STATus:INTerrupt:ENABle EXTERNAL1
STATus:INTerrupt:NTRansition ON

VXI Technology, Inc.

5, GLOBAL or NONE

24 VM1548C Programming

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OUTPUT REGISTER CIRCUIT

This section refers to the bi-directional port when configured as an output. The SCPI command
used to configure a port as an output is:

SOURce:DATA:ENABle <port #> ON

The port is programmable to allow the data to be transparent or clocked. If the port is clocked,
there are several choices for the clock source. The method for selecting clocked mode and the
source of the clock is done with one SCPI command.

OUTPut:REGister:SOURce <port #> <source> Where <port> is 1 of 6 data

The method for selecting transparent mode is:

OUTPut:REGister:SOURce <port #> NONE Where <port> is 1 of 6 data

EXAMPLES

The following SCPI commands will clock the number 205 out of port #5 using the IMMEDIATE
pulse.

SOURce:DATA:ENABle 5 ON
OUTPut:REGister:SOURce 5 IMMEDIATE
SOURce:DATA 5 205

TRIGger:SEQuence:IMMediate This provides a rising edge clock

The following is an example of writing to a port operating in transparent mode. This method
requires no clock edge for the data to be presented on the external connector.

SOURce:DATA:ENABle 5 ON
OUTPut:REGister:SOURce 5 NONE

SOURce:DATA 5 205 205 Immediately appears on the

The following example selects the external CLK5 line to clock the data port. In this example, it is
assumed the external CLK5 signal is a steady logic low and the clock edge is produced by
toggling the clock polarity.

SOURce:DATA:ENABle 5 ON
OUTPut:REGister:SOURce 5 EXTERNAL
OUTPut:REGister:POLarity 5 NORMAL
SOURce:DATA 5 205

OUTPut:REGister:POLarity 5 INVERT This provides a rising edge clock

registers and <source> is
EXTERNAL, TTLTRIG, GLOBAL
(TRIGOUT) or IMMEDIATE

registers and NONE means this
data register is transparent

External Connector

VM1548C Programming 25

INPUT REGISTER CIRCUIT

This section refers to the bi-directional port when configured as an input. The SCPI command
used to configure a port as an input is:

SOURce:DATA:ENABle <port #> OFF

The port is programmable to allow the data to be transparent or clocked. If the port is clocked,
there are several choices for the clock source. The method for selecting clocked mode and the
source of the clock is done with one SCPI command.

INPut:REGister:SOURce <port #> <source> Where <port> is 1 of 6 data

Regardless of the port’s input mode, note that data inputs to the module do not contain pull-up or
down-biasing resistors. As such, if the user does not provide either active or passive biasing of the
data inputs, a read of the port may result in either a “1” or a “0” being read from the data inputs.

The method for selecting transparent mode is:

INPut:REGister:SOURce <port #> NONE Where <port> is 1 of 6 data

EXAMPLES
The following SCPI commands will clock the data in on port #3 using the IMMEDIATE pulse.

SOURce:DATA:ENABle 3 OFF
INPut:REGister:SOURce 3 IMMEDIATE

TRIGger:SEQuence:IMMediate This provides a rising edge clock
FORMat ASCII

READ? 3 Example of read value is 255

The following is an example of reading from a port operating in transparent mode. This method
requires no clock edge for the data to be available.

SOURce:DATA:ENABle 5 OFF
INPut:REGister:SOURce 5 NONE

FORMat BINARY

READ? 5 The data presented on the external

The following example selects the external CLK3 line to clock the data port. In this example, it is
assumed the external CLK3 signal is a steady logic low and the clock edge is produced by
toggling the clock polarity.

SOURce:DATA:ENABle 3 OFF
INPut:REGister:SOURce 3 EXTERNAL
INPut:REGister:POLarity 3 NORMAL

INPut:REGister:POLarity 3 INVERT This provides a rising edge clock
FORMat HEX

READ? 3

Example of read value is #HFF

VXI Technology, Inc.

registers and <source> is
EXTERNAL, TTLTRIG, GLOBAL
(TRIGOUT) or IMMEDIATE

registers and NONE means this
data register is transparent

Example of read value is

#B11111111

connector is what will be read

26 VM1548C Programming

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BI-DIRECTIONAL CLOCK CIRCUIT

There are six independent bi-directional clock circuits connected to the 68-pin external connector.
Each clock is associated with one of the 6 ports previously described. Therefore, <port #>
terminology is used to refer to a specific clock. When the circuit is configured as an output, the
clock signal will be sourced by the module. When the circuit is configured as an input, the clock
signal is sourced by the UUT. This clock (CLK0-5) may be used for many different purposes: a
trigger source; selections for the interrupt trigger; a port’s input clock; a port’s output clock.

The following SCPI command configures the clock line as an output:

OUTPut:CLOCk:ENABle ON

The following SCPI command configures the clock line as an input:

OUTPut:CLOCk:ENABle OFF

When the circuit is operating as an output, the clock source is selectable using the following SCPI
command.

OUTPut:CLOCk:SOURce <port #> <source> Where <source> is TTLTRIG,

The polarity of the output clock signal is controlled with the following SCPI command.

OUTPut:CLOCk:POLarity <edge> Where <edge> is NORMAL or

EXAMPLES

To drive TRIGIN out as CLK1 on the external connector, the following SCPI commands would
be issued.

OUTPut:CLOCk:ENABle 1 ON
OUTPut:CLOCk:SOURce TTLTRIG

To drive TRIGOUT out as CLK3 on the external connector, the following SCPI commands would
be issued:

OUTPut:CLOCk:ENABle 3 ON
OUTPut:CLOCk:SOURce GLOBAL

To drive IMMEDIATE out as CLK5 on the external connector, the following SCPI commands
would be issued:

OUTPut:CLOCk:ENABle 5 ON
OUTPut:CLOCk:SOURce IMMEDIATE

To select no clock, the NONE parameter is used. This will always be a logic level low.

OUTPut:CLOCk:ENABle 5 ON
OUTPut:CLOCk:SOURce NONE

IMMEDIATE, GLOBAL
(TRIGOUT) or NONE

INVERT

VM1548C Programming 27

APPLICATION EXAMPLES

This section contains examples of using SCPI command strings for programming the VM1548C
module. The code is functional and will contain a brief description and block diagram of the
operation.

WRITE MODE

In this example the VM1548C will be set up prior to receiving the UUT generated clock edge.
The VM1548C will output one (1) 16-bit binary word to the UUT from ports 0 and 1.

COMMANDS

OUTP:CLOC:ENAB 0 0 Disables port 0 clock from driving front panel

OUTP:CLOC:ENAB 1 0 Same as previous command except for port 1.
OUTP:REG:SOUR 0 EXT Selects port 0 input clock (CLK0) as method of

OUTP:REG:SOUR 1 EXT Same as previous command except for port 1.
SOUR:DATA:ENAB 0 1 Selects and enables port 0 to write data to the UUT.
STAT:INT:ENAB EXT0 Set the interrupt trigger source as the port 0 clock.
STAT:INT:PTR ON Set the interrupt trigger source to the positive edge.
SOUR:DATA 0 48 Writes “48” data to port 0 for subsequent transfer to

SOUR:DATA:ENAB 1 1 Selects and enables port 1 to write data to the UUT.
SOUR:DATA 1 15 Writes “15” data to port 1 for subsequent transfer to

Figure 3-1 and the description that follows illustrates the function of each of the commands above.

DESCRIPTION

VXI Technology, Inc.

connector and enables this line as the clock input to
port 0.

triggering.

the UUT.

the UUT.

28 VM1548C Programming

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VCC

47K

120

22

100pF

CLK from
front panel

VMIP

Bus

Control Lines

Address 0,1,2

Data Bus

Read /

Write

Data

Buffer

WRITE*
DOE*
D8-D15

Timing

and

Control

Port

Decoder

F

WRITE

CLKOUT <port>

PORTENA*

Write

Clock

Data Bus

OUTENA

PORT2*

D8-D15

PORT1*

Direction

Control

Enable

IGURE 3-1: OUTPUT BLOCK DIAGRAM

OR

WRITE

CLKOUT <port>

IN*/OUT <port>
CLKOUTENA

I/O
Word
Buffer

200K

33K

Data Bus

I/O from

front panel

Output

Data

Buffer

22

ISENSE

OUTP:CLOC:ENAB 0 0 and OUTP:CLOC:ENAB 1 0 commands inform the timing and

control circuitry that the front panel clock lines are used as inputs. This allows the UUT to furnish
the clock source when ready to receive data.

The OUTP:REG:SOUR 0 EXT and the OUTP:REG:SOUR 1 EXT commands select the

external clock input as the trigger method to output data to the UUT. When these commands are
received the VM1548C timing and control circuitry will generate the PORTENA* signal to the
port decoder. The port decoder then clocks the write clock enable latch selecting the
CLKOUTENA. The CLKOUTENA signals are applied to the I/O data and word buffers enabling

the output clock line. The SOUR:DATA:ENAB 0 1 and SOUR:DATA 0 48 command enables

port 0 for a write and latches the data into the I/O word buffer respectively.

VM1548C Programming 29

READ MODE

VXI Technology, Inc.

The VM1548C timing and control circuitry generates the PORTENA* signal to the port decoder.
This decoder in turn clocks the direction latch selecting the OUTENA. This signal is OR’ed with
the external I/O direction signal from the UUT. The result is referred to as IN*/OUT and is
applied to the I/O data and word buffers configuring them as outputs. The timing and control
circuitry will generate a write pulse latching the data from the read/write data buffer into the I/O
word buffer. Port 0 is now ready to transmit the data byte “48” to the UUT. The steps are repeated

for the SOUR:DATA:ENAB 1 1 and SOUR:DATA 1 15 commands with port 1 being enabled

and loaded with the data byte “15”.

The VM1548C is now ready to transmit the data word “1548C” to the UUT. When the CLK
signals are received from the UUT, the I/O data buffers latch the data word from the I/O word
buffer. The data on the I/O data buffer’s outputs are now available to the UUT. The

STAT:INT:ENAB EXT 0 and STAT:INT:PTR ON commands enable the interrupt to occur

when the CLK 0 signal is received and sets the polarity of this interrupt to the positive edge. The
VM1548C module sends an Interrupt Request (IRQ*) informing the slot 0 controller that the
transfer has occurred.

In this example the VM1548C will be configured to clock the UUT and read 24 bits of data, when
the TTL Trigger line 1 is activated. The TTL Trigger is assumed to be pulled by another
instrument used during this test. The UUT will output data on the rising edge of the received clock
that is generated from the VM1548C. The VM1548C will capture or read data on the falling edge
of this same clock. When the VM1548C detects a TTL Trigger 1, the front panel clock lines to the
UUT are activated. The clock is sent, the UUT transmits data on the rising edge, and the data will
be latched into the VM1548C on the falling edge. An Interrupt Request is generated informing the
slot 0 controller via the VMIP that data is ready to be read.

COMMANDS

OUTP:CLOC:ENAB 3 ON Enables port 3 clock to drive the front panel

DESCRIPTION

connector

OUTP:CLOC:ENAB 4 ON Same as previous command except for port 4
OUTP:CLOC:ENAB 5 ON Same as previous command except for port 5
SOUR:DATA:ENAB 3 OFF Selects and enables port 3 to read data from the UUT
SOUR:DATA:ENAB 4 OFF Selects and enables port 4 to read data from the UUT
SOUR:DATA:ENAB 5 OFF Selects and enables port 5 to read data from the UUT
INP:REG:POL 3 INV Selects the falling edge for clocking port 3
INP:REG:POL 4 INV Selects the falling edge for clocking port 4
INP:REG:POL 4 INV Selects the falling edge for clocking port 5
INP:REG:SOUR 3 TTLT Selects VXI bus TRIGIN as the clock source for

port 3

INP:REG:SOUR 4 TTLT Same as previous command except for port 4
INP:REG:SOUR 5 TTLT Same as previous command except for port 5
INP:TTLT:STATE ON Enables the TTL trigger selection mux
INP:TTLT 1 Selects VXI bus TTL trigger line 1 to be used as

TRIGIN

STAT:INT:ENAB Set the interrupt trigger source as the default value
STAT:INT:NTR ON Set the interrupt trigger source to the negative edge

The controller waits for the interrupt and then

proceeds

READ? 3 Data is transferred from port 3 to the VMIP bus
READ? 4 Data is transferred from port 4 to the VMIP bus
READ? 5 Data is transferred from port 5 to the VMIP bus

30 VM1548C Programming