VML P2V28S20ATP-7, P2V28S20ATP-75, P2V28S30ATP-8, P2V28S40ATP-8, P2V28S40ATP-75 Datasheet

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

128Mb SDRAM Specification

P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8

MIRA TECHNOLOGY INC.

8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C.
TEL: [phone].25170066
FAX: [phone]

JULY.2000 Rev.2.2

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)

128Mb Synchronous DRAM

P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

P2V28S20ATP-7,-75,-8
P2V28S30ATP-7,-75,-8
P2V28S40ATP-7,-75,-8

PRELIMINARY

Some of contents are described for general products and

(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)

are subject to change without notice.

DESCRIPTION

P2V28S20ATP is organized as 4-bank x 8,388,608-word x
4-bit Synchronous DRAM with LVTTL interface and
P2V28S30ATP is organized as 4-bank x 4,194,304-word x
8-bit and P2V28S40ATP is organized as 4-bank x 2,097,
152-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK.

FEATURES

ITEM

tCLK

tRAS
tRCD

tAC

tRC

Icc1

Icc6

Clock Cycle Time

Active to Precharge Command Period (Min.)

Row to Column Delay

Access Time from CLK

Ref /Active Command Period

Operation Current (Single Bank)

Self Refresh Current

(Min.)

(Min.)

(Max.)

(Min.)

(Max.)

(Max.)

P2V28S20ATP,P2V28S30ATP and P2V28S40ATP
achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in com­puter systems.

P2V28S20/30/40ATP

CL=2
CL=3

CL=2
CL=3

V28S20D
V28S30D

V28S40D

-7,-75,-8

-7

­7ns

45ns
20ns

-

5.4ns
63ns

85mA
85mA
85mA

1mA

-75

10ns

7.5ns
45ns
20ns

6ns

5.4ns

67.5ns
85mA
85mA
85mA

1mA

-8

10ns

8ns

48ns

20ns

6ns
6ns

70ns
85mA
85mA
85mA

1mA

- Single 3.3V ±0.3V power supply

- Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Byte Control- DQML and DQMU (P2V28S40ATP)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 4096 refresh cycles /64ms

- LVTTL Interface

- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

JULY.2000 Rev.2.2

Page-1

PIN CONFIGURATION (TOP VIEW)

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

P2V28S20ATP

P2V28S30ATP

P2V28S40ATP

PIN CONFIGURATION

(TOP VIEW)

Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC

VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS

BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd

Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2

VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS

BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd

Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4

VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS

BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22

23 32
24 31

25 30
26 29
27 28

400mil 54pin TSOP(II)

54
53
52
51
50
49
48
47

46
45
44
43
42
41
40
39
38
37
36

35
34
33

Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11

VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC

A11
A9
A8
A7
A6
A5
A4
Vss

Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5

VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC

A11
A9
A8
A7
A6
A5
A4
Vss

Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC

VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC

A11
A9
A8
A7
A6
A5
A4
Vss

CLK
CKE

/CS
/RAS
/CAS
/WE

DQ0-15

JULY.2000 Rev.2.2

: Master Clock
: Clock Enable
: Chip Select

: Row Address Strobe

: Column Address Strobe
: Write Enable
: Data I/O

DQM
A0-11 : Address Input

BA0,1
Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output

Page-2

: Output Disable / Write Mask

: Bank Address

BLOCK DIAGRAM

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

DQ0-7

I/O Buffer

Memory Array

4096 x1024 x8

Cell Array

Bank #0

Mode

Register

Address Buffer

A0-11

Note:This figure shows the P2V28S30ATP
The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3
The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15

BA0,1

Type Designation Code

P2 V 28 S 3 0 TP -8

A

Memory Array

4096 x1024 x8

Cell Array

Bank #1

Clock Buffer

CLK CKE

Memory Array

4096 x1024 x8

Cell Array

Control Circuitry

/CS /RAS

Bank #2

Control Signal Buffer

/CAS

Memory Array

4096 x1024 x8

Cell Array

Bank #3

/WE

DQM

Access Item

-7 : 7 ns (143MHz/3-3-3)

-75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3)

-8 : 8 ns (100MHz/2-2-2 o r 125MH z/3-3-3)

Package Type TP : TSOP(II)
Process Generation
Function 0 : Random Column
Organization 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 128 :128Mbit
Interface V :LVTTL
PSC DRAM

JULY.2000 Rev.2.2

Page-3

A : 2nd generation

PIN FUNCTION

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

CLK Input

CKE Input

/CS Input

/RAS, /CAS, /WE Input

A0-11 Input

BA0,1 Input

Master Clock:

All other inputs are referenced to the rising edge of CLK

Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.

Chip Select:

When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.

A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.

Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.

DQ0-3(x4),
DQ0-7(x8),

Input / Output

DQ0-15(x16)

DQM(x4,x8),
DQMU/L(x16)

Input

Vdd, Vs s Power Supply

VddQ, VssQ Power Supply

Data In and Data out are referenced to the rising edge of CLK.

Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.

Power Supply for the memory array and peripheral circuitry.

VddQ and VssQ are supplied to the Output Buffers only.

JULY.2000 Rev.2.2

Page-4

BASIC FUNCTIONS

The P2V28S20 , 30 and 40ATP provides basic functions,
bank (row) activate, burst read / write, bank (row) precharge,
and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and

CLK

/CS Chip Select : L=select, H=deselect
/RAS Command
/CAS

/WE Command

Command

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

A10 are used as chip select, refresh opt ion, and precharge
option, respectively .
To know the detailed definition of commands, please see the com­mand truth table.

define basic command

CKE Refresh Option @ refresh command

A10 Precharge Option @ precharge or read/write command

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output
data appears after /CAS latency. When A10 =H at this command, the bank is deac­tivated after the burst read (auto-precharge, READA).

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write (auto-precharge, WRITEA).

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, all banks
are deactivated (precharge all, PREA ).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally . After this command, the banks are precharged automatically.

JULY.2000 Rev.2.2

Page-5

COMMAND TRUTH T ABLE

COMMAND

MNEMONIC

CKE

n-1

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

CKE

/CS /RAS /CAS /WE BA0,1 A11 A10 A0-9

n

Deselect

No Operation
Row Address Entry &

Bank Active

Single Bank Precharge

Precharge All Banks
Column Address Entry

Column Address Entry &

Write with Auto-Precharge

Column Address Entry

Column Address Entry &

Read with Auto-Precharge

Auto-Refresh

Self-Refresh Entry

Self-Refresh Exit

&Write

& Read

DESEL HXHXXXX XXX

NOP HXLHHHX XXX

ACT

PRE

PREA

WRITE

WRITE A

READ

READA

REFA

REFS

REFSX

HX LL HHV VVV

HXLLHLVXLX

HXLLHL XHX

HXLHLLVVLV

HXLHLL VVHV

HXLHLHVVLV

HXLHLHVVHV

HHL L LHX XXX

H LL L LHX XXX

L HHXXX XXXX

L HLHHH XXXX

X

Burst Terminate

Mode Register Set

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE: 1. A7-A9 =0, A0-A6 =Mode Address

JULY.2000 Rev.2.2

TBST HX L HHL XX XX

MRS

H X L L L L L L L V*1

Page-6

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH T ABLE

Current State /CS /RAS /CAS /WE Address Command Action

IDLE

ROW

ACTIVE

HXXXX DESEL NOP

L H H H X NOP NOP

L H H L TBST ILLEGAL*2

L H L X BA, CA, A10

L L H H BA, RA ACT Bank Active, Latch RA

L L H L BA, A10

L L L H X REFA Auto-Refresh*5

LLLL

HXXXX DESEL NOP

L H H H X NOP NOP

L H H L TBST NOP

BA

Op-Code,
Mode-Add

BA

READ /
WRITE

PRE /
PREA

MRS Mode Register Set*5

ILLEGAL*2

NOP*4

L H L H BA, CA, A10

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

Op-Code,
Mode-Add

READ /

READA
WRITE /
WRITEA

PRE /
PREA

MRS ILLEGAL

Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge

Precharge / Precharge All

JULY.2000 Rev.2.2

Page-7

FUNCTION TRUTH T ABLE (continued)

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

Current State /CS /RAS /CAS /WE Address

READ

WRITE

H X X X X DESEL

LHHHX NOP

L H H L TBST

L H L H BA, CA, A10

L H L L BA, CA, A10

L L H H BA, RA ACT

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

H X X X X DESEL

L H H H X NOP NOP (Continue Burst to END)

BA

Op-Code,
Mode-Add

Command

READ

/READA

WRITE /
WRITEA

PRE /
PREA

MRS ILLEGAL

Action

NOP (Continue Burst to END)

NOP (Continue Burst to END)

Terminate Burst

Terminate Burst, Latch CA,Begin

Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin

Write, Determine Auto-Precharge*3

Bank Active / ILLEGAL*2

Terminate Burst, Precharge

NOP (Continue Burst to END)

L H H L TBST

L H L H BA, CA, A10

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2

L L H L BA, A10

L L L H X REFA ILLEGAL

L L L L MRS ILLEGAL

BA

READ /

READA
WRITE /
WRITEA

PRE /
PREA

Op-Code,
Mode-Add

Terminate Burst, Latch CA,Begin
Terminate Burst, Latch CA,Begin

Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3

Terminate Burst, Precharge

JULY.2000 Rev.2.2

Page-8

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH T ABLE (continued)

Current State /C S /R AS /CAS /WE Address Command Action

READ with

AUTO

PRECHARGE

WRITE with

AUTO

PRECHARGE

H X X X X DESEL

LHHHX NOP

L H H L TBST ILLEGAL

L H L H BA, CA, A10

L H L L BA, CA, A10

L L H H BA, RA ACT

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

H X X X X DESEL

L H H H X NOP NOP (Continue Burst to END)

BA

Op-Code,
Mode-Add

READ /

READA

WRITE /

WRITE A

PRE /
PREA

MRS ILLEGAL

NOP (Continue Burst to END)

NOP (Continue Burst to END)

ILLEGAL

ILLEGAL

Bank Active / ILLEGAL*2

ILLEGAL*2

NOP (Continue Burst to END)

L H H L TBST ILLEGAL

L H L H BA, CA, A10

L H L L BA, CA, A10

L L H H BA, RA ACT

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

BA

Op-Code,
Mode-Add

READ /

READA

WRITE /

WRITEA

PRE /
PREA

MRS

ILLEGAL

ILLEGAL

Bank Active / ILLEGAL*2

ILLEGAL*2

ILLEGAL

JULY.2000 Rev.2.2

Page-9

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH T ABLE (continued)

Current State /C S /R AS /CAS /WE Address Command Action

PRE -

CHARGING

ROW

ACTIVATING

H X X X X DESEL NOP (Idle after tRP)

L H H H X NOP NOP (Idle after tRP)

L H H L TBST ILLEGAL*2

L H L X BA, CA, A10

L L H H BA, RA ACT ILLEGAL*2

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

H X X X X DESEL NOP (Row Active after tRCD)

L H H H X NOP NOP (Row Active after tRCD)

L H H L TBST ILLEGAL*2

BA

Op-Code,
Mode-Add

BA

READ /
WRITE

PRE /

PREA

MR S ILLEGAL

ILLEGAL*2

NOP*4 (Idle after tRP)

L H L X BA, CA, A10

L L H H BA, RA ACT

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

Op-Code,
Mode-Add

READ /
WRITE

PRE /
PREA

MR S ILLEGAL

ILLEGAL*2

ILLEGAL*2

ILLEGAL*2

JULY.2000 Rev.2.2

Page-10

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH T ABLE (continued)

Current State /C S /R AS /CAS /WE Address Command Action

WRITE

RECOVERING

REFRESHING

HXXX

LHHH

LHHL

LHLX

LLHH

LLHL

L L L H X REFA ILLEGAL

LLLL

H X X X X DESEL NOP (Idle after tRC)

L H H H X NO P NOP (Idle after tRC)

L H H L TBST ILLEGAL

X

X NOP NOP

BA

BA, CA, A10

BA, RA ACT

BA, A10

Op-Code,
Mode-Add

BA

DESEL

TBST

READ /
WRITE

PRE /

PREA

MRS

NOP

ILLEGAL*2

ILLEGAL*2

ILLEGAL*2

ILLEGAL*2

ILLEGAL

L H L X BA, CA, A10

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

Op-Code,
Mode-Add

READ /
WRITE

PRE /
PREA

MRS ILLEGAL

ILLEGAL

ILLEGAL

JULY.2000 Rev.2.2

Page-11

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH T ABLE (continued)

Current State /CS /RAS /C AS /WE Address Command Action

MODE

REGISTER

SETTING

H X X X X DESEL NOP (Idle after tRSC)

L H H H X NOP NOP (Idle after tRSC)

L H H L TBST ILLEGAL

L H L X BA, CA, A10

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10

L L L H X REFA ILLEGAL

LLLL

BA

Op-Code,
Mode-Add

READ /
WRITE

PRE /
PREA

MRS ILLEGAL

ILLEGAL

ILLEGAL

JULY.2000 Rev.2.2

Page-12

FUNCTION TRUTH T ABLE for CKE

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

Current State

SELF-

REFRESH*1

POWER

DOWN

ALL BANKS

IDLE*2

CKE

n-1

CKE

n

/CS /RAS /CAS /WE Add Action

H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
LHLHHHX

Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
HXXXXXX

INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Power Down)

H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State =Power Down

ANY STATE

other than

H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Susspend at Next Cycle*3

listed above

LHXXXXX

Exit CLK Susspend at Next Cycle*3

L L X X X X X Maintain CLK Suspend

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

JULY.2000 Rev.2.2

Page-13

SIMPLIFIED STATE DIAGRAM

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

SELF

REFRESH

REFS

REFSX

WRITE

SUSPEND

MODE

REGISTER

SET

CLK

SUSPEND

CKEL

WRITE

CKEH

WRITEA

MRS

CKEL

CKEH

TERM

WRITE

WRITEA

WRITE

WRITEA READA

IDLE

ACT

ROW

ACTIVE

READA

READ

CKEH

REFA

CKEL

READ

TERM

READ

AUTO

REFRESH

POWER

DOWN

READA

CKEL

CKEH

READ

SUSPEND

WRITEA

SUSPEND

POWER
APPLIED

CKEL

CKEH

POWER

ON

WRITEA

PRE

PRE

PRE PRE

PRE

CHARGE

READA

CKEL

CKEH

READA

SUSPEND

Automatic Sequence
Command Sequence

JULY.2000 Rev.2.2

Page-14

128Mb Synchronous DRAM

P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)

POWER ON SEQUENCE

Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.

1. Apply power and star t clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.

2. Maintain stable power, stable clock, and NOP input con­ditions for a minimum of 200µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.

5. Issue a mode register set command to initialize the mode
register.

After these sequence, the SDRAM is idle state and ready
for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be pro­grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.

CLK
/CS
/RAS
/CAS
/WE

BA0,1 A11-A0

V

LATENCY

MODE

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0

0 0 0 0 0 LTMODE BT BL00

CL

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

/CAS LATENCY

R: Reserved for Future Use

FP: Full Page

BL

0 0 0
0 0 1

R
R

2

3
R
R
R
R

BURST

LENGTH

BURST

TYPE

0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

0
1

BT= 0 BT= 1

1
2
4
8
R

R
R

FP

SEQUENTIAL
INTERLEAVED

1
2
4
8
R

R
R
R

JULY.2000 Rev.2.2

Page-15