Datasheet P2V28S20ATP-7, P2V28S20ATP-75, P2V28S30ATP-8, P2V28S40ATP-8, P2V28S40ATP-75 Datasheet (VML)
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128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
MIRA TECHNOLOGY INC.
8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C.
TEL: 886-2-25170055.25170066
FAX: 886-2-25174575
JULY.2000 Rev.2.2
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
128Mb Synchronous DRAM
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
P2V28S20ATP-7,-75,-8
P2V28S30ATP-7,-75,-8
P2V28S40ATP-7,-75,-8
PRELIMINARY
Some of contents are described for general products and
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
are subject to change without notice.
DESCRIPTION
P2V28S20ATP is organized as 4-bank x 8,388,608-word x
4-bit Synchronous DRAM with LVTTL interface and
P2V28S30ATP is organized as 4-bank x 4,194,304-word x
8-bit and P2V28S40ATP is organized as 4-bank x 2,097,
152-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
Active to Precharge Command Period (Min.)
Row to Column Delay
Access Time from CLK
Ref /Active Command Period
Operation Current (Single Bank)
Self Refresh Current
(Min.)
(Min.)
(Max.)
(Min.)
(Max.)
(Max.)
P2V28S20ATP,P2V28S30ATP and P2V28S40ATP
achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in computer systems.
P2V28S20/30/40ATP
CL=2
CL=3
CL=2
CL=3
V28S20D
V28S30D
V28S40D
-7,-75,-8
-7
7ns
45ns
20ns
-
5.4ns
63ns
85mA
85mA
85mA
1mA
-75
10ns
7.5ns
45ns
20ns
6ns
5.4ns
67.5ns
85mA
85mA
85mA
1mA
-8
10ns
8ns
48ns
20ns
6ns
6ns
70ns
85mA
85mA
85mA
1mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
JULY.2000 Rev.2.2
Page-1
PIN CONFIGURATION (TOP VIEW)
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
P2V28S20ATP
P2V28S30ATP
P2V28S40ATP
PIN CONFIGURATION
(TOP VIEW)
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 32
24 31
25 30
26 29
27 28
400mil 54pin TSOP(II)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
JULY.2000 Rev.2.2
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM
A0-11 : Address Input
BA0,1
Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output
Page-2
: Output Disable / Write Mask
: Bank Address
BLOCK DIAGRAM
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Mode
Register
Address Buffer
A0-11
Note:This figure shows the P2V28S30ATP
The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3
The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15
BA0,1
Type Designation Code
P2 V 28 S 3 0 TP -8
A
Memory Array
4096 x1024 x8
Cell Array
Bank #1
Clock Buffer
CLK CKE
Memory Array
4096 x1024 x8
Cell Array
Control Circuitry
/CS /RAS
Bank #2
Control Signal Buffer
/CAS
Memory Array
4096 x1024 x8
Cell Array
Bank #3
/WE
DQM
Access Item
-7 : 7 ns (143MHz/3-3-3)
-75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3)
-8 : 8 ns (100MHz/2-2-2 o r 125MH z/3-3-3)
Package Type TP : TSOP(II)
Process Generation
Function 0 : Random Column
Organization 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 128 :128Mbit
Interface V :LVTTL
PSC DRAM
JULY.2000 Rev.2.2
Page-3
A : 2nd generation
PIN FUNCTION
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
CLK Input
CKE Input
/CS Input
/RAS, /CAS, /WE Input
A0-11 Input
BA0,1 Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
Input / Output
DQ0-15(x16)
DQM(x4,x8),
DQMU/L(x16)
Input
Vdd, Vs s Power Supply
VddQ, VssQ Power Supply
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
JULY.2000 Rev.2.2
Page-4
BASIC FUNCTIONS
The P2V28S20 , 30 and 40ATP provides basic functions,
bank (row) activate, burst read / write, bank (row) precharge,
and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and
CLK
/CS Chip Select : L=select, H=deselect
/RAS Command
/CAS
/WE Command
Command
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
A10 are used as chip select, refresh opt ion, and precharge
option, respectively .
To know the detailed definition of commands, please see the command truth table.
define basic command
CKE Refresh Option @ refresh command
A10 Precharge Option @ precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output
data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, all banks
are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally . After this command, the banks are precharged automatically.
JULY.2000 Rev.2.2
Page-5
COMMAND TRUTH T ABLE
COMMAND
MNEMONIC
CKE
n-1
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
CKE
/CS /RAS /CAS /WE BA0,1 A11 A10 A0-9
n
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
&Write
& Read
DESEL HXHXXXX XXX
NOP HXLHHHX XXX
ACT
PRE
PREA
WRITE
WRITE A
READ
READA
REFA
REFS
REFSX
HX LL HHV VVV
HXLLHLVXLX
HXLLHL XHX
HXLHLLVVLV
HXLHLL VVHV
HXLHLHVVLV
HXLHLHVVHV
HHL L LHX XXX
H LL L LHX XXX
L HHXXX XXXX
L HLHHH XXXX
X
Burst Terminate
Mode Register Set
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
JULY.2000 Rev.2.2
TBST HX L HHL XX XX
MRS
H X L L L L L L L V*1
Page-6
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH T ABLE
Current State /CS /RAS /CAS /WE Address Command Action
IDLE
ROW
ACTIVE
HXXXX DESEL NOP
L H H H X NOP NOP
L H H L TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10
L L L H X REFA Auto-Refresh*5
LLLL
HXXXX DESEL NOP
L H H H X NOP NOP
L H H L TBST NOP
BA
Op-Code,
Mode-Add
BA
READ /
WRITE
PRE /
PREA
MRS Mode Register Set*5
ILLEGAL*2
NOP*4
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Precharge / Precharge All
JULY.2000 Rev.2.2
Page-7
FUNCTION TRUTH T ABLE (continued)
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Current State /CS /RAS /CAS /WE Address
READ
WRITE
H X X X X DESEL
LHHHX NOP
L H H L TBST
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL
L H H H X NOP NOP (Continue Burst to END)
BA
Op-Code,
Mode-Add
Command
READ
/READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Action
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
NOP (Continue Burst to END)
L H H L TBST
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L MRS ILLEGAL
BA
READ /
READA
WRITE /
WRITEA
PRE /
PREA
Op-Code,
Mode-Add
Terminate Burst, Latch CA,Begin
Terminate Burst, Latch CA,Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
JULY.2000 Rev.2.2
Page-8
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH T ABLE (continued)
Current State /C S /R AS /CAS /WE Address Command Action
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
H X X X X DESEL
LHHHX NOP
L H H L TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL
L H H H X NOP NOP (Continue Burst to END)
BA
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITE A
PRE /
PREA
MRS ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
NOP (Continue Burst to END)
L H H L TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
BA
Op-Code,
Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
ILLEGAL
JULY.2000 Rev.2.2
Page-9
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH T ABLE (continued)
Current State /C S /R AS /CAS /WE Address Command Action
PRE -
CHARGING
ROW
ACTIVATING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD)
L H H L TBST ILLEGAL*2
BA
Op-Code,
Mode-Add
BA
READ /
WRITE
PRE /
PREA
MR S ILLEGAL
ILLEGAL*2
NOP*4 (Idle after tRP)
L H L X BA, CA, A10
L L H H BA, RA ACT
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MR S ILLEGAL
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
JULY.2000 Rev.2.2
Page-10
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH T ABLE (continued)
Current State /C S /R AS /CAS /WE Address Command Action
WRITE
RECOVERING
REFRESHING
HXXX
LHHH
LHHL
LHLX
LLHH
LLHL
L L L H X REFA ILLEGAL
LLLL
H X X X X DESEL NOP (Idle after tRC)
L H H H X NO P NOP (Idle after tRC)
L H H L TBST ILLEGAL
X
X NOP NOP
BA
BA, CA, A10
BA, RA ACT
BA, A10
Op-Code,
Mode-Add
BA
DESEL
TBST
READ /
WRITE
PRE /
PREA
MRS
NOP
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
JULY.2000 Rev.2.2
Page-11
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH T ABLE (continued)
Current State /CS /RAS /C AS /WE Address Command Action
MODE
REGISTER
SETTING
H X X X X DESEL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC)
L H H L TBST ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
LLLL
BA
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
JULY.2000 Rev.2.2
Page-12
FUNCTION TRUTH T ABLE for CKE
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CKE
n-1
CKE
n
/CS /RAS /CAS /WE Add Action
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
LHLHHHX
Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
HXXXXXX
INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State =Power Down
ANY STATE
other than
H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Susspend at Next Cycle*3
listed above
LHXXXXX
Exit CLK Susspend at Next Cycle*3
L L X X X X X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
JULY.2000 Rev.2.2
Page-13
SIMPLIFIED STATE DIAGRAM
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEA
MRS
CKEL
CKEH
TERM
WRITE
WRITEA
WRITE
WRITEA READA
IDLE
ACT
ROW
ACTIVE
READA
READ
CKEH
REFA
CKEL
READ
TERM
READ
AUTO
REFRESH
POWER
DOWN
READA
CKEL
CKEH
READ
SUSPEND
WRITEA
SUSPEND
POWER
APPLIED
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
JULY.2000 Rev.2.2
Page-14
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
POWER ON SEQUENCE
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and star t clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
After these sequence, the SDRAM is idle state and ready
for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
V
LATENCY
MODE
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 0 0 0 LTMODE BT BL00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
/CAS LATENCY
R: Reserved for Future Use
FP: Full Page
BL
0 0 0
0 0 1
R
R
2
3
R
R
R
R
BURST
LENGTH
BURST
TYPE
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
1
2
4
8
R
R
R
R
JULY.2000 Rev.2.2
Page-15
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Command
Address
DQ
Initial Address
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0123456701234567
1234567010325476
2345670123016745
3456701232107654
4567012345670123
Write
Y
D0 D1 D2 D3
10 1
11 0
11 1
-00
-01
-10
-11
--0
--1
5670123454761032
6701234567452301
7012
0123
1230
4
2301
30
01
2
10
3456 3210
12
7654
0123
1032
2301
32
01
10
10
JULY.2000 Rev.2.2
Page-16
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by
the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval
between one bank and the other bank is tRRD. Maximum 2 ACT
commands are allowed within tRC , although the number of banks
which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When
multiple banks are active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank
can be issued.
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
READ
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the /CAS Latency from the
READ, followed by (BL -1) consecutive data when the Burst Length
is BL. The start address is specified by A0-A9(x4), A0-8(X8), A0-7
(X16) , and the address sequence of burst data is defined by the
Burst Type. A READ command may be applied to any active bank,
so the row precharge time (tRP) can be hidden behind continuous
output data by interleaving the multiple banks. When A10 is high at
a READ command, the auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, TBST, ACT) to the same bank is
inhibited till the internal precharge is complete. The internal precharge
starts at BL after READA. (Need to keep tRAS min.) The next ACT
command can be issued after (BL + tRP) from the previous READA.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin
Command
A0-9
A10
ACT
Xa
Xa
tRRD
tRCD
ACT
Xb
Xb
READ
Y
0
A11 Xa Xb Xb
BA0,1
00
01
00
DQ
tRCmin
tRAS
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
ACT
Xb
Xb
01
JULY.2000 Rev.2.2
Page-17
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Command
A0-9
A10
A11
BA0,1
ACT
tRCD
Xa
Xa
Xa Xb
00
READ
Y
0
00
ACT
Xb
Xb
10
DQ
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
A0-9
A10
ACT
Xa
Xa
READ
tRCD
Y
1
READ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
BL + tRP
BL
10
PRE
Y
0
0
00
ACT
tRP
Xa
Xa
A11 Xa Xa
BA0,1
DQ
00
00
Qa0 Qa1 Qa2 Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK
Command AC T READ
BL
CL=3
CL=2
DQ
DQ
Internal Precharge Start Timing
Qa1 Qa2 Qa3Qa0
Qa1 Qa2 Qa3Qa0
00
JULY.2000 Rev.2.2
Page-18
WRITE
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9(x4), A0-8(X8), A0-7(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE
command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input
WRITE with Auto-Precharge (BL=4)
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the
autoprecharge (WRITEA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at
tWR after the last input data cycle. (Need to keep tRAS min.) The
next ACT command can be issued after tRP from the internal
precharge timing.
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
A0-9
A10
ACT
Xa
Xa
Xa
Xa
00
ACT
Xa
Xa
10
PRE
Y
0
0
00
Write
tRCD tRCD
ACT
Y
Xb
00
Xb
Xb 0Xa
00
10
Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0
Write
Multi Bank Interleaving WRITE (BL=4)
Write
tRCD
Y
1
PRE
0
10
ACT
tRP
Xa
Xa
A11
BA0,1
DQ
JULY.2000 Rev.2.2
Xa Xa
00
00
tWR
Da0 Da1 Da2 Da3
Internal precharge starts
Page-19
00
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval
is minimum 1 CLK..
Read Interrupted by Read (BL=4, CL=3)
CLK
READ
Command
A0-9
READ
Yi
Yj Yk Yl
READ
READ
A10
0000
A11
BA0,1
DQ
00 1000 01
Qai0 Qaj1 Qbk0 Qbk1Qaj0 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1
cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-9
A10
READ
Yi
0
Write
Yj
0
A11
BA0,1
00
00
DQM
Q
D
JULY.2000 Rev.2.2
Qai0
Daj0 Daj1 Daj2 Daj3
DQM control Write control
Page-20
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the
same bank . READ to PRE interval is minimum 1 CLK. A PRE
command to output disable latency is equivalent to the /CAS
Read Interrupted by Precharge (BL=4)
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Latency. As a result, READ to PRE interval determines valid
data length to be output. The figure below shows examples of
BL=4.
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
READ
READ
READ
READ
READ PRE
READ PRE
PRE
PRE
Q0 Q1 Q2
Q0
PRE
Q0 Q1 Q2
Q0
Q1
Q0
PRE
Q1
DQ
JULY.2000 Rev.2.2
Q0
Page-21
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
[Read Interrupted by Burst Terminate]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The
terminated bank remains active.
Read Interrupted by Terminate (BL=4)
CLK
CL=3
Command
DQ
Command
DQ
READ
READ
TBST
READ to TBST interval is minimum 1 CLK. A TBST command to
output disable latency is equivalent to the /CAS Latency.
TBST
Q0 Q1 Q2
Q0
Q1
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ
READ
READ
READ
TBST
TBST
Q0
TBST
Q0 Q1 Q2
TBST
Q0
Q1
Q0
JULY.2000 Rev.2.2
Page-22
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE
interval is minimum 1 CLK.
Write Interrupted by Write (CL=3,BL=4)
CLK
Command
A0-9
A10
Write
Yi
0
Write
Yj
0
Write
Yk
0
Write
Yl
0
A11
BA0,1
DQ
00
00
Dai0 Daj0 Daj1 Dbk0
10
Dbk1 Dbk2
00
Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE
to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (CL=3,BL=4)
CLK
Command
A0-9
A10
Write
Yi
0
READ
Yj
0
Write
Yk
0
READ
Yl
0
A11
BA0,1
00
00
10
00
DQM
Qaj0
DQ
JULY.2000 Rev.2.2
Qaj1Dai0 Dbk0 Dbk1
Page-23
Qal0
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data
to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQM
DQ
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da 1
tWR
PRE
0
00
ACT
tRP
Xa
0
00
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the
bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
JULY.2000 Rev.2.2
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da 1
TBST Write
Yb
0
00
Db0 Db 1 Db2 Db3
Page-24
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after
tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Write Interrupted by WRITE to another bank (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
CLK
Command
Write
Ya
1
00
Da0 Da1
Write
BL
Yb
tWR
0
10
Db0 Db1 Db2 Db3
interruptedauto-precharge activate
ACT
tRP
Xa
Xa
00
Write Interrupted by READ to another bank (CL=2,BL=4)
Write
Read
BL
ACT
tRP
A0-9,11
A10
BA0-1
DQ
JULY.2000 Rev.2.2
Ya
1
00
Da0 Da1
Yb
tWR
0
10
Qb0 Qb1 Qb2 Qb3
interruptedauto-precharge activate
Page-25
Xa
Xa
00
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after
tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Read Interrupted by Read to another bank (CL=2,BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
Read
Ya
1
00
Read
BL tRP
Yb
0
10
Qa0 Qa1
interruptedauto-precharge activate
Qb0 Qb1 Qb2 Qb3
ACT
Xa
Xa
00
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge
or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
JULY.2000 Rev.2.2
Page-26
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /
CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit
memory cells. The auto-refresh is performed on 4 banks
concurrently. Before performing an auto-refresh, all banks must
Auto-Refresh
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command.
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto Refresh on All Banks
NOP or DESELECT
minimum tRFC
Auto Refresh on All Banks
JULY.2000 Rev.2.2
Page-27
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command
(/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the selfrefresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and
the only enabled input ,all other inputs including CLK are
disabled and ignored, so that power consumption due to
Self-Refresh
CLK
/CS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
synchronous inputs is saved. To exit the self-refresh, supplying
stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE=H. After tRC from the 1st CLK egde following
CKE=H, all banks are in the idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Stable CLK
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
new command
X
00
minimum tRFC
for recovery
JULY.2000 Rev.2.2
Page-28
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure
below shows how CKE works. By negating CKE, the next
internal CLK is suspended. The purpose of CLK suspend is
power down, output suspend or input suspend. CKE is a
ext.CLK
tIH tIS tIH tIS
CKE
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active
or idle. A command at the suspended cycle is ignored.
CLK
CKE
Command
CKE
Command
int.CLK
Power Down by CKE
PRE NOP NOP NOP
NOP NOP NOPACT
DQ Suspend by CKE (CL=2)
Standby Power Down
Active Power Down
CLK
CKE
Command
DQ
JULY.2000 Rev.2.2
Write Read
D0 D1 D2 D3
Page-29
Q0 Q1 Q2 Q3
DQM CONTROL
DQM is a dual function signal defined as the data mask for
writes and the output disable for reads. During writes, DQM(U,L)
masks input data word by word. DQM(U,L) to write mask latency
DQM Function(CL=3)
CLK
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
is 0. During reads, DQM(U,L) forces output to Hi-Z word by word.
DQM(U,L) to output Hi-Z latency is 2.
Command
DQM
DQ
Write
D0 D2 D3
masked by DQM(U,L)=H
READ
Q0 Q1 Q3
disabled by DQM(U,L)=H
JULY.2000 Rev.2.2
Page-30
ABSOLUTE MAXIMUM RATINGS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Symbol Parameter
Vdd
VddQ
VI
VO
IO
Pd
Topr
Tstg
Supply Voltage
Supply Voltage for Output
Input Voltage
Output Voltage -0.5 - 4.6
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Conditions Ratings Unit
with respect to Vss
with respect to VssQ
with respect to Vss
with respect to VssQ
Ta = 25˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Symbol
Vdd
Vss 0
VddQ Supply Voltage for output 3.0
VssQ
VIH*1
VIL*2
Supply Voltage
Supply Voltage
Supply Voltage for output
High-Level Input Voltage all inputs
Low-level Input Voltage all inputs
Parameter
Min.
3.0
0
2.0
-0.3
-0.5 - 4.6
-0.5 - 4.6
-0.5 - 4.6
50
1000
0 - 70
-65 - 150
Limits
Typ. Max.
3.3
0
3.3
0
3.6 V
3.6 V
VddQ +0.3
0.8 V
V
V
V
V
mA
mW
˚C
˚C
Unit
V
0
V
V
NOTES:
1. VIH(max)=5.5V for pulse width less than 10ns.
2. VIL(min)=-1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 -70˚C,Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O Input Capacitance, I/O pin
Parameter
Input Capacitance, address pin
Input Capacitance, contorl pin
Input Capacitance, CLK pin
JULY.2000 Rev.2.2
Test Condition
@ 1MHz
1.4V bias
200mV swing
Vcc=3.3V
Page-31
Limits (min.)
2.5
2.5
2.5
4.0
Limits (max.)
-7 -75/-8
3.8
3.8
3.5
6.5
5.0
5.0
4.0
6.5
Unit
pF
pF
pF
pF
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
ITEM
Operating current
Precharge Standby
current in Non-Power
down mode
Precharge Standby
current in Power down
mode
Active Standby current
Burst current
Auto-refresh current
-7
100
20
15
1
30
25
130
2
Limits (max.)
-75
95
20
15
2
1
30
25
130
130
-8
85
20
15
120
130
Unit
mA
mA
mAIcc2P x4/x8/x16
2
1
30
mA
25
mA
mA
Symbol
Icc1
Icc2N
Icc2NS x4/x8/x16 mA
Icc2PS
Icc3N x4/x8/x16
Icc3NS x4/x8/x16
Icc4
Icc5
tRC=min, tCLK=min
BL=1,IOL=0mA
CKE=VILmax
tCLK=15ns
CKE=VIHmin
CLK=VILmax(fixed)
CKE=VIHmin
tCLK=15ns(Note)
CKE=VIHmin
tCLK=VILmax(fixed)
CKE=/CS=VIHmin
tCLK=15ns(Note)
CKE=VIHmin
tCLK=VILmax(fixed)
All Bank Active
tCLK = min
BL=4, CL=3, IOL=0mA
tRC=min, tCLK=min
Organization
x4/x8/x16
x4/x8/x16
x4/x8/x16 mA
x4/x8/x16
x4/x8/x16
140
Self-refresh current
Icc6
CKE < 0.2V
x4/x8/x16
7,7.5,8
NOTE:
1. Icc(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Symbol
VOH (DC)
VOL (DC)
IOZ
I
I
High-Level Output Voltage (DC)
Low-level Output Voltage (DC)
Off-state Output Current
Input Current
Parameter Test Conditions
IOH=-2mA
IOL= 2mA
Q floating VO=0 -- VddQ
VIH = 0 -- VddQ +0.3V
1
Limits
Min.
2.4
-5
-5 5
mA
Max.
0.4
5
1
unit
V
V
µA
µA
1
JULY.2000 Rev.2.2
Page-32
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Min.
-
-7
Max.
Symbol
tCLK
Parameter
CLK cycle time
CL=2 ns
Min.
10
Limits
-75
Max.
Min.
10
-8
Unit
Max.
2.5
2.5
1.5
0.8
63
7
1
70
20
45
20
14
14
14
10
100K
64
7.5
2.5
2.5
1.3
0.8
67.5
75
20
45
20
15
15
15
1
10
100K
64
0.8
8
3
3
10
1
2
7
0
80
20
100K
48
20
20
20
20
64
CL=3 ns
tCH CLK High pulse width ns
tCL CLK Low pulse width ns
tT
Transition time of CLK
tIS
Input Setup time
(all inputs)
tIH Input Hold time (all inputs) ns
tRC Row Cycle time
tRFC Refresh Cycle Time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD
tRSC
Act to Act Delay time
Mode Register Set Cycle time
tREF Refresh Interval time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CLK
DQ
1.4V
1.4V
Any AC timing is referenced
to the input signal passing
through 1.4V.
JULY.2000 Rev.2.2
Page-33
128Mb Synchronous DRAM
V
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits
Symbol Parameter
tAC
Access time from CLK
Output Hold time
tOH
from CLK
tOLZ
Delay time , output lowimpedance from CLK
CL=2
CL=3
CL=2
CL=3
-7 -7.5
Min.
2.7
0
Max.
5.4
Min.
3
3
0
Max.
6
5.4
Min.
3
3
0
-8
Max.
Unit
Note
6
ns
6
ns
ns
*1
ns
ns
tOHZ
NOTE:
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Delay time , output highimpedance from CLK
2.7
5.4
3
Output Load Condition
OUT
50pF
CLK
tOLZ
CLK
DQ
Output Timing Measurement
Reference Point
5.4
1.4V
6
3
1.4V
1.4V
ns
DQ
tAC
tOH
JULY.2000 Rev.2.2
tOHZ
Page-34
1.4V
Burst Write (single bank) @BL=4
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRC
tRAS
tRP
RAS
tRCD
tRCD
CAS
tWR
tWR
WE
CKE
DQM
A0-8
X
Y
X Y
A10
X
X
A9,11
BA 0,1
DQ
X
0
ACT#0 PRE#0 ACT#0 WRITE#0 PRE#0
0
D0 D0 D0 D0
WRITE#0
0
X
0 0
0
D0 D0 D0 D0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-3 5
Burst Write (multi bank) @BL=4
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
tRAS
tRRD
RAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRC
tRC
tRP
tRCD
tRCD
tRCD
CAS
tWR
tWR
WE
CKE
DQM
A0-8
X
Y
X
Y
X Y
X
A10
A9,11
BA0,1
X
X
0
X
X
0
1
0
1
X
X
0 0
X
X
1
0
DQ
D0 D0 D0 D0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0 PRE#0
ACT#1
D1 D1 D1 D1
WRITEA#1
(Auto-Precharge)
D0 D0 D0 D0
ACT#1
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-36
Burst Read (single bank) @BL=4 CL=2
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
CS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRAS tRP
tRAS
RAS
tRCD
tRCD
CAS
WE
CKE
DQM
A0-8
X
Y
X Y
A10
X
X
A9,11
BA 0,1
DQ
X
0
ACT#0 READ# 0 PRE#0 ACT#0 READ#0 PRE#0
0
Q0 Q0 Q0 Q0
0
X
0 0
0
Q0 Q0 Q0 Q0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-37
Burst Read (multiple bank) @BL=4 CL=2
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
CS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRC
tRRD
tRAS
RAS
tRCD tRCD
tRCD
CAS
WE
CKE
DQM
A0-8
X
Y
X
Y
X Y
X
A10
X
X
X
X
A9,11
BA 0,1
DQ
X
0
ACT#0 READA#0
0
ACT#1
X
1
Q0 Q0 Q0 Q0
READA#1
1
X
0 0
Q1 Q1 Q1 Q1
ACT#0 READ#0 PRE#0
X
1
Q0 Q0 Q0 Q0
ACT#1
0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-38
Write Interrupted by Write @BL=4
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
tRRD
RAS
tRCD
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tWR
WE
CKE
DQM
A0-8
X
Y
X
Y
Y
Y
X
A10
A9,11
BA0,1
DQ
X
X
0
X
X
0
1
D0 D0 D0 D0
0
1
D0 D1 D1 D1
0
D0 D0 D0 D0
X
X
0
1
ACT#0 WRITE#0 WRITE#0 PRE#0
ACT#1
WRITE#0 WRITEA#1
interrupt
same
bank
interrupt
other
bank
interrupt
other
bank
ACT#1
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-39
Read Interrupted by Read @BL=4,CL=2
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
tRRD
RAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRCD
tRCD
CAS
WE
CKE
DQM
A0-8
X
Y
X
Y
Y
Y
X
A10
A9,11
BA0,1
X
X
0
X
X
0
1
1
1
0
X
X
1
DQ
Q0 Q0
ACT#0 READ#0 READ#0
ACT#1
READ#1 READA#1
interrupt
other
bank
Q0 Q1 Q1 Q1
interrupt
same bank
Q1 Q1 Q0 Q0
interrupt
other
bank
Q0 Q0
ACT#1
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-40
128Mb Synchronous DRAM
/
/
/
/
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
tRRD
RAS
tRCD
tRCD
CAS
tWR
WE
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
X
X
X
1
Y
0
D0 D0
Y
1
Q1 Q1
Y
1
D1 D1 D1 D1
1
ACT#0 WRITE#0 WRITE#1 PRE#1
ACT#1
READ#1
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-41
128Mb Synchronous DRAM
/
/
/
/
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Write/Read Terminated by Precharge @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
tRC
tRP
tRAS
tRP
RAS
tRCD
tRCD
CAS
tWR
WE
CKE
DQM
A0-8
A10
A9,11
X
X
X
Y
X
X
X
Y
X
X
X
BA 0,1
DQ
0
ACT#0 WRITE#0 READ#0 PRE#0
0
D0 D0
0
PRE#0
Terminate Terminate
0
ACT#0
0
0
Q0 Q0
0
ACT#0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-42
128Mb Synchronous DRAM
/
/
/
/
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
RAS
tRCD
CAS
tWR
WE
CKE
DQM
A0-8
X
Y
Y
Y
A10
A9,11
BA 0,1
X
X
0
0
0
0
0
DQ
D0 D0
ACT#0 WRITE#0 READ#0
TERM
Q0 Q0
TERM
D0 D0 D0 D0
WRITE#0
PRE#0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-43
Single Write Burst Read @BL=4,CL=2
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
RAS
tRCD
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
WE
CKE
DQM
A0-8
X
Y
Y
A10
A9,11
BA 0,1
DQ
X
X
0
0
D0 Q0 Q0
0
Q0 Q0
ACT#0 WRITE#0 READ#0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-44
Power-Up Sequesce and Intialize
/
/
/
/
CLK
200µs
CS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
tRP tRFC
tRFC tRSC
RAS
CAS
WE
CKE
DQM
A0-8
A10
A9,11
MA
0
0
X
X
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL REFA ACT#0MRSREFA
Minimum 8 REFA cycles
REFA
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-45
Auto Refresh
/
/
/
/
CLK
CS
RAS
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tRFC
tRP
tRCD
WE
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
Y
0
D0 D0 D0 D0
PRE ALL REFA
All banks must be idle before REFA is issued.
ACT#0
WRITE#0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-46
Self Refresh
/
/
/
/
CLK
CS
RAS
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tRFC
tRP
WE
CKE
DQM
A0-8,
A10
A9,11
BA0,1
X
X
X
0
DQ
PRE ALL Self Refresh Entry Self Refresh Exit
All banks must be idle before REFS is issued.
ACT#0
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-47
CLK Suspension @BL=4,CL=2
/
/
/
/
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
CS
RAS
tRCD
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
WE
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
Y
0
D0 Q0 Q0
D0 D0 D0
Y
0
Q0
Q0
ACT#0 WRITE#0 READ#0
internal
CLK
suspended
internal
CLK
suspended
Italic parameter indicates minimum case
JULY.2000 Rev.2.2
Page-48
Power Down
/
/
/
/
CLK
CS
RAS
CAS
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WE
Standby Power Down Active Power Down
CKE
DQM
A0-8
X
A10
A9,11
BA 0,1
X
X
0
DQ
PRE ALL ACT#0
JULY.2000 Rev.2.2
Page-49
DQM Write Mask @BL=4
128Mb Synchronous DRAM
P2V28S20A TP-7,-75,-8 (4-B ANK x 8,388,608-WORD x 4-BIT)
P2V28S30A TP-7,-75,-8 (4-B ANK x 4,194,304-WORD x 8-BIT)
P2V28S40A TP-7,-75,-8 (4-B ANK x 2,097,152-WORD x 16-BIT)
JULY.2000 Rev.2.2
Page-50
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