VITESSE VSC851FX Datasheet

VITESSE SEMICONDUCTOR CORPORATION
Page 1
10/21/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
SC851
1.6 Gb/s 32 X 32
Crosspoint Switc
h
G52167-0 Rev. 4.1
Features
General Description
This VSC851 is a 32 x 32 crosspoint switch intended for high speed digital data communications applica­tions. This product has 32 dat a inp uts and 32 data output s. An y inpu t c an be mul tiple x ed to any, some, or all out­puts. High speed digital data up to 1.6Gb/s can be switched with less than 150pS pulse width distortion. In broadcast mode, any two outputs will exhibit less than 250pS of skew relative to one another. Signals in data paths are fully differential to minimize duty cycle distortion. The V SC851 requir es both -2V and 3.3V power supplies.
The address signals that control traf f ic pat terns for data pa ths are double b uffered. the LSTROBE signal load individual addresses for each output. The GSTROBE signal is used to update addresses for all 32 outputs simul- taneously. This method allows users to configure any, som e or all switches indepen dently without disrup ting data flow of the data paths. Broadcast and flow through function ality are controlled via BROADCAST and FLOWTHRU inputs.
This product is ideal for high speed digital applications including Gigabit Ethernet and ATM switch cores, data distribution for telecommunica tions, fiber channel networkin g, computer networking, mu ltiprocessor switching, and test equipment. In a telecommunications SONET application, for example, the VSC851 can be used as an STS-12 protection switch.
The VSC851 is packaged in a 256 pin thermally enhanced LDCC package. This product is fabricated using Vitesse’s E/D GaAs MESFET process which achieves high speed coupled with low power dissipation.
Functional Description
The VSC851 may be used t o conn ect any one of 32 inputs t o any one or combination of 32 output channel s, according to a user defined bit pattern stored in each output channel’s control latches (see Figure 1). For data path operation, signals flow transparently from inputs I+/I-[0:31] to output channels Z+/Z-[0:31] thro ugh thirty-two 32:1 multiplexers. The traffic pattern is controlled by data previously stored in thirty-two 5-bit con­trol latches each corresponding to an output channel. Value of these 5-bit control latches is a binary numerical representation of the input channel selected. D[4:0] = 00000 corresponds to I[0], D[4:0] = 00001 corresponds to I[1], etc. Similarly, A [4:0] = 00000 selects path to output Z [0], A [4:0] = 00001 to Z [1], etc. To configure the switch, at rising edge of LSTROBE, the bank of holding registers for a particular ch annel i s upd at ed by input addresses D[4:0] which describes a new path for that channe l. After some or all ho lding registers are pro­grammed, a high pulse is applied to GSTROBE to transfer the in fo rmation from holding registers into all control latches. By this method, the entire crosspoint switch can be reconfigured simultaneously.
• 1.6Gb/s Operation
• Non-blocking Architecture
• Duty-cycle Distortion: ≤ 150pS
• ≤ 2nS Propagation Delay for Data Path
• ≤ 250pS Output to Output Skew in Broadcast Mode
• Power Supply: -2 V and 3.3 V
• ECL Differential Data Paths
• 3.3 V TTL Control Signals
• Low Power Dissipation
• Package: 256-pin LDCC
VITESSE
SEMICONDUCTOR CORPORATION
Data Shee
t
VSC851
.6 Gb/s 32x32
rosspoint Switch
Page 2
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 10/21/99
G52167-0 Rev. 4.1
32 x 32
Switch Matrix
GSTROBE
Input
Buffers
Output
Buffers
32 x 32
Control Latches
32 x 5
Holding Registers
LSTROBE
A [4:0]
5 to 32
Decode
BROADCAST
FLOWTHRU
D [4:0]
0,1......31
160
64
64
32
32
5
Z + [0:31]
Z - [0:31]
I + [0:31]
I - [0:31]
The VSC851 can be configured in Broadcast mode. In Broadcast Mode, at the rising edge of LSTROBE, all holding registe rs are up dat ed b y input addresses D[4:0]. If a high pulse is appli ed to GSTROBE, the entire cros­spoint is configured and the selected data are broadcasted to all of the outputs.
In FlowThru mode, at the rising edge of LSTROBE, all holdin g re g isters are set to t he n umerical represent a- tion of the output which th ey control, (i.e., 00000 is loaded for outp ut Z[0], 00001 is loaded for output Z[1] etc.). If a high pulse is then applied to GSTROBE, these values are passed to the contro l latch es. In this mode , data from I[0] is switched to Z[0] da ta from I[1] is switched to Z[1] , etc. The input address values at D[4:0] and the output address values at A[4:0] are ignored in FlowThru Mode. All data input and output signals (I+/I- [0:31], Z+/Z-[0:31]) are differential ECL levels. All other signals are TTL levels. If both BROADCAST and FLOWTHRU inputs are asserted, the FlowThru Mode overrides the Broadcast Mode.
VSC851 Block Diagram
VITESSE SEMICONDUCTOR CORPORATION
Page 3
10/21/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
SC851
1.6 Gb/s 32 X 32
Crosspoint Switc
h
G52167-0 Rev. 4.1
AC Characteristics
(Over recommended operating conditions. ECL Output load 50Ω to V
TT.
)
Table 1: Data Flow Mode.
(1) Duty cycle distortion = duty cycle out - duty cycle in (pS). With 8B/10B encoded data.
AC Timing Waveforms
Figure 1: Normal Data Flow Timing
Parameters Description Min Typ Max Units Conditions
T
PW
Minimum input pulse width 640 pS Worst case 60/40 input duty cycle
T
DLY
Propagation delay 600 2000 pS
Tduty Duty cycle distortion 150 p S at 1.6 Gb/s Note(1)
Tskew Output to output skew 250 pS On a given part broadcast mode
Tpskew Data path skew 500 pS
For any 2 paths from I+/I- to Z+/Z- on a given part
Minimum Input Pulse Width & Propagation Delay
T
DLY
T
PW
I+ [0:31] I-[0:31]
Z+ [0:31] Z-[0:31]
T
DLY
T
SKEW
T
SKEW
VITESSE
SEMICONDUCTOR CORPORATION
Data Shee
t
VSC851
.6 Gb/s 32x32
rosspoint Switch
Page 4
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 10/21/99
G52167-0 Rev. 4.1
Table 2: Configuration, Broadcast, FlowThru Mode.
Figure 2: Configuration Mode Timing
Parameters Description Min Typ Max Units Conditions
T
LSW
LSTROBE pulse width 5 ——nS—
T
GSW
GSTROBE pulse width 5 nS
T
GSZ
GSTROBE to Z+/Z- Outputs Delay 1.5 5.0 nS
T
LSZ
LSTROBE to Z+/Z- Outputs Delay 2 6.0 nS GSTROBE high
T
ALSSU
A[4:0] to LSTROBE setup time 3.5 nS
T
ALSH
A[4:0] to LSTROBE hold time 1 nS
T
DLSSU
D[4:0] to LSTROBE setup time 3.5 nS
T
DLSH
D[4:0] to LSTROBE hold time 1 nS
T
GLSU
GSTROBE to LSTROBE setup time 2.5 nS
T
GLH
GSTROBE to LSTROBE hold time 2 nS
T
BLSSU
BROADCAST to LSTROBE setup time 4 nS
T
BLSH
BROADCAST to LSTROBE hold time 1 nS
T
FLSSU
FLOWTHRU to LSTROBE setup time 4 nS
T
FLSH
FLOWTHRU to LSTROBE hold time 1 nS
I+ [0:15] I- [0:15]
Z+ [0:31] Z- [0:31]
A[0:4]
T
LSW
T
DLSSU
T
DLSH
T
ALSSU
T
ALSH
T
GLSU
T
GSZ
T
GLH
(Output Address )
D[0:4]
(Input Address)
LSTROBE
GSTROBE
T
LSW
T
LSZ
T
DLY
T
GSW
VITESSE SEMICONDUCTOR CORPORATION
Page 5
10/21/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
SC851
1.6 Gb/s 32 X 32
Crosspoint Switc
h
G52167-0 Rev. 4.1
Figure 3: Broadcast and FlowThru Timing
DC Characteristics
(Over recommended operating conditions. ECL Output load 50W to V
TT.
)
Parameters Description Min Typ Max Units Conditions
V
ODIF
Differential ECL Output Voltage 600 —1100mV50 to VTT
V
OCM
Common Mode ECL Output Voltage -1.5 -1.0 V 50Ω to VTT
V
IDIF
Differential ECL Input Voltage 20 0 1200 mV
V
ICM
Common Mode ECL Input Voltage -1.5 -0.5 V
I
IHE
Input HIGH ECL Current +200 µAV
IN =
-0.7V
I
ILE
Input LOW ECL Current -50 µAV
IN =
-2.0V
V
IHT
Input HIGH voltage (TTL) 2.0 4.3 V
V
ILT
Input LOW voltage (TTL) 0 0.8 V
I
IHT
Input HIGH current (TTL) 50 µA 2.0V < VIN < 4.3V
I
ILT
Input LOW current (TTL) -500 µA -0.5V < VIN < 0.8V
I
VTTL
VTTL Supply Current 20 mA
I
VTT
VTT Supply Current 3600 mA Outputs open
P
D
Power dissipation 7500 mW
T
BLSSU
T
BLSH
FLOWTHRU
GSTROBE
BROADCAST
LSTROBE
T
FLSSU
T
FLSH
T
GLSU
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