VITESSE SEMICONDUCTOR CORPORATION
Page 1
10/21/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
G52167-0 Rev. 4.1
Features
General Description
This VSC851 is a 32 x 32 crosspoint switch intended for high speed digital data communications applications. This product has 32 dat a inp uts and 32 data output s. An y inpu t c an be mul tiple x ed to any, some, or all outputs. High speed digital data up to 1.6Gb/s can be switched with less than 150pS pulse width distortion. In
broadcast mode, any two outputs will exhibit less than 250pS of skew relative to one another. Signals in data
paths are fully differential to minimize duty cycle distortion. The V SC851 requir es both -2V and 3.3V power
supplies.
The address signals that control traf f ic pat terns for data pa ths are double b uffered. the LSTROBE signal load
individual addresses for each output. The GSTROBE signal is used to update addresses for all 32 outputs simul-
taneously. This method allows users to configure any, som e or all switches indepen dently without disrup ting
data flow of the data paths. Broadcast and flow through function ality are controlled via BROADCAST and
FLOWTHRU inputs.
This product is ideal for high speed digital applications including Gigabit Ethernet and ATM switch cores,
data distribution for telecommunica tions, fiber channel networkin g, computer networking, mu ltiprocessor
switching, and test equipment. In a telecommunications SONET application, for example, the VSC851 can be
used as an STS-12 protection switch.
The VSC851 is packaged in a 256 pin thermally enhanced LDCC package. This product is fabricated using
Vitesse’s E/D GaAs MESFET process which achieves high speed coupled with low power dissipation.
Functional Description
The VSC851 may be used t o conn ect any one of 32 inputs t o any one or combination of 32 output channel s,
according to a user defined bit pattern stored in each output channel’s control latches (see Figure 1). For data
path operation, signals flow transparently from inputs I+/I-[0:31] to output channels Z+/Z-[0:31] thro ugh
thirty-two 32:1 multiplexers. The traffic pattern is controlled by data previously stored in thirty-two 5-bit control latches each corresponding to an output channel. Value of these 5-bit control latches is a binary numerical
representation of the input channel selected. D[4:0] = 00000 corresponds to I[0], D[4:0] = 00001 corresponds
to I[1], etc. Similarly, A [4:0] = 00000 selects path to output Z [0], A [4:0] = 00001 to Z [1], etc. To configure
the switch, at rising edge of LSTROBE, the bank of holding registers for a particular ch annel i s upd at ed by input
addresses D[4:0] which describes a new path for that channe l. After some or all ho lding registers are programmed, a high pulse is applied to GSTROBE to transfer the in fo rmation from holding registers into all control
latches. By this method, the entire crosspoint switch can be reconfigured simultaneously.
• 1.6Gb/s Operation
• Non-blocking Architecture
• Duty-cycle Distortion: ≤ 150pS
• ≤ 2nS Propagation Delay for Data Path
• ≤ 250pS Output to Output Skew in Broadcast Mode
• Power Supply: -2 V and 3.3 V
• ECL Differential Data Paths
• 3.3 V TTL Control Signals
• Low Power Dissipation
• Package: 256-pin LDCC