VITESSE VSC837 Datasheet

3.2Gb/s Crosspoint Switch with Input Signal Activity Monitoring
Physical
Layer
Products
Features:
Input Signal Monitoring (ISA)
Integrated Signal Equalization
(ISE) for Deterministic Jitter Reduction
Selectable On-Die I/O
Termination
VSC837
Product Brief
Hard and Soft Power Down
Modes for Unused Channels
TTL/2.5V CMOS Control I/O
(3.3V Tolerant)
Non-Blocking Architecture
with Broadcast and Multicast Capabilities
Specifications:
68 Input by 68 Output
Crosspoint Switch
3.2Gb/s NRZ Data Bandwidth
66MHz Multi-Mode
Programming Port
Differential CML Output Driver
11W typ/14W max (low drive
mode),13W typ/16W max (high drive mode)
Single 2.5V Supply
High Performance 37.5mm,
480 TBGA Package
Supporting Forward Error Correction at data rates to 3.2Gb/s, the VSC837 completes the industry’s broadest Crosspoint switch family . In addition to leading edge performance, the VSC837 provides enhanced flexibility with mul­tiple programming modes, user select­able input and output termination con­figurations, programmable output lev­els and Input Signal Activity monitoring to allow in-system diagnostics.
The VSC837 is a monolithic 68x68 asynchronous crosspoint switch, de­signed to carry broadband data streams. The non-blocking switch core is programmed through a triple-mode port interface that allows random ac­cess programming of each input/output port. A high degree of signal integrity is
maintained throughout the chip via fully differential signal paths. The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 68:1 multi­plexer that can be programmed to one and only one of its 68 inputs. The sig­nal path is unregistered and fully asyn­chronous, so there are no restrictions on the phase, frequency , or signal pat­tern at each input.
Each high-speed output is a fully dif­ferential switched current driver with switchable on-die terminations for maxi­mum signal integrity. Data inputs are terminated on die through 100W resis­tors between true and complement in­puts.
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3.2Gb/s Crosspoint Switch with
68x69 Switch Core
Core Program Registers
Program Memory
Program Interface
Y, YN[0:67]A, AN[0:67]
Act. Mon.
SERIAL
SDOUT
BURST
CSB
LOAD
ALE_SCN
ACTCLK
ACTIVITY
CONFIG
69
th
OUTPUT
INITB
OUTCHAN
[18:0]
INCHAN [6:0]
Input Signal Activity Monitoring
VSC837
Product Brief
VSC837 Jitter Performance
Vitesse continues its history of adding innovative features to its extensive Crosspoint Switch prod­uct family. Vitesses new crosspoint switches will incorpo­rate novel, proprietary functional­ity called Integrated Signal Equal­ization switching matrix
ISE switch to reduce or eliminate the effects of Inter-Symbol Interfer­ence (ISI) that can occur in appli­cations that use long, narrow PCB traces to route the incoming sig­nal. This jitter eating capability results in less output jitter when the incoming jitter is deterministic in nature. ISE also facilitates the development of three stage CLOS switch fabrics by improving the three pass performance of the crosspoint switch.
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(ISE) on every input to the
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enables the crosspoint
A triple-mode programming inter­face is provided that allows pro­gramming commands to be sent as serial data or one of two forms of parallel data. The input-re­ferred mode (burst mode) allows an input port to be routed to all outputs in only 4 program cycles. Core programming can be ran­dom for each port address, or multiple program assignments can be queued and issued simul­taneously. The programming may be initialized to a straight­through configuration (A0 to Y0, A1 to Y1, etc.) using the INITB pin.
Physical
Layer
Products
OutputInput
VSC837 Block Diagram
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An activity monitor is provided to allow in-system diagnostics. The activity monitor can observe any high-speed input via an internal 69th multiplexer.
For more information on Vitesse Products visit the Vitesse web site at www.vitesse.com or contact Vitesse Sales at (800) VITESSE or
sales@vitesse.com
© Copyright 2000 Vitesse Semiconductor Corporation
and the Vitesse logo
of Vitesse Semiconductor Corp;oration
are all registered trademarks
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