VITESSE VSC834UB Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

with Input Signal Activity (ISA) Monitoring

2.5Gb/s 17x17 Crosspoin t Switch

Features

• 17 Input by 17 Output Crosspoint Switch

• 2.5Gb/s NRZ Data Bandwidth

• 42 Gb/s Aggregate Bandwidth

• TTL Compatible µP Interface

• Differential PECL Data Inputs

• On-chip 50Ω Input Terminations

• 50Ω Source Terminated PECL Output Drivers

• Single 3.3V Supply

• 9W Maximum Power Dissipation

• High Performance 256 Pin BGA Package

General Description

The VSC834 is a monolithic 17x17 asynchron ous crosspoint switch design ed to carry broadband data streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor interface that allows random access programming of each output port. A high degree of signal integrity is maintained through the chip through fully differential signal paths.

The crosspoint function is based on a mu ltiplexer tr ee architecture . Each data o utput is driven by a 17:1 multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be programmed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An interrupt pin is provid ed to signal LOA, af ter which an external controller can query the chip to determi ne the channel(s) on which the fault occurred.

Each output driver is a fully differential switched current driver with on-die back-termina tions for maximum signal integrity. Data inputs are terminated on die through 50

The parallel interface uses TTL levels, and provides address, data, and control pins th at are compatible with a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and programming. Program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command.

Ω resistors connected to V

TERM

VSC834 Block Diagram

A16

Control Logic

µP Interface

G52247-0, Rev 4.2 Page 1 02/09/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitess e.com

Internet: www.vitesse.com

Y16

VITESSE

SEMICONDUCTOR CORPORATION

2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring

Figure 1: Detailed Block Diagram:

A, AN[16:0]

LOA

Monitor

Switch Core

Program Memory

Control Interface

17x17

Datasheet

VSC834

Y , YN[16:0]

Output Drivers

DATA[4:0], ADDR[5:0]

ALE, CSB, WRB, RDB INTB,

MONCLK, CONFIG

Functional Description

Data Paths

All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a nominal impedance of 50

Data outputs are provided through di fferential current switches with on-chip term inations that produc e a PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels when terminated in 50 age level of the output swing will be shifted from its nominal value. The common-mode voltage of the output swing can be adjusted using the VCOM pin. The adjustment range is not calibrated, but typically allows for about +

200mV of adjustment in the output common-mode voltage.

Output channels can be powered off in pairs if fewer than 17 outputs are required. By connecting the VEE pin associated with a given pair of outputs to V reduced by roughly 200mW.

Ω. All input termination resistors are tied to V

TERM

Ω to 2.0V. Other termination voltages are possible, such as to V

, the output pa irs will pu ll to V

or 1.3V, but the volt-

and chip power will be

Page 2 G52247-0, Rev 4.2

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

02/09/01

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

Programming Interface

with Input Signal Activity (ISA) Monitoring

2.5Gb/s 17x17 Crosspoin t Switch

The switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. The program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate.

The program data is composed of two parts: output address and input address. The output address, denoted by ADDR[5:0], specifies which output channel is to be p rogrammed. The input ad dress, denot ed by DAT A[4:0], specifies which input port the switch slice should connect to. The format of the program data is simple binary, where the binary value maps directly to the switch slice position and/or input port number. For example: ADDR[5:0] (000100) / DATA[4:0] (001 10) would di rect output channel Y4 to connect to inpu t channel A6. T he programming state may be verified (read back) by applying the add ress of the des ired output and asser ting RDB. The programming state is unknown at power-on. Additional address space is provided for access to the monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL (see Tab le 6).

Table 1: Signal Table

Pin I/O Description

D[5:0] B Bidirectional data bus to transfer data to/from internal program registers A[5:0] I Address bus to select internal program registers for read-write operations

ALE I CSB I Chip Select (Active Low): assert this pin whenever the part is being read or programmed.

WRB I

RDB I

INTB O Interrupt (Active Low): this signal is asserted when an LOA condition is found

CONFIG I

MONCLK I

Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally when low.

Write (Active Low): program data will be transferred to the first level internal registers on the rising edge of this signal (when CSB is also low).

Read (Active Low): program data from the internal pro gram or monitor re gisters will be read out on the data bus when this signal goes low (with CSB also low).

Configure (Active High): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. This signal may be tied high to leave the second-level registers transparent so all programmi ng will take effect immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a highorder bit of the addr ess bus

Monitor states are transferred to mon itor registers on the rising edge of this signal. MONCLK is not expected to exceed 3MHz.

Loss of Activity (LOA) Monitoring

The LOA function consists of an activity monitor on each in put channel, conn ected directly to the pads. The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address (See Table 2) of the monitor register cor respondi ng to the si gnal of int erest an d assertin g RDB. Each monitor register is four bits in leng th, covering the state of four inp uts or output s. There is one extra o ne-bit monitor for each of the 17

input and 17th output. The state of each moni t or is t ransferred to the register period-

ically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected.

G52247-0, Rev 4.2 Page 3 02/09/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring

If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrup t will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read.

The LOA circuitry requires a min imum signal level of 30- 150 mV peak-peak to recognize an input as active. This is requi r ed to di sti ngu ish noise on an unconnected signal (where both inputs float to the terminat i on voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level can be adjusted with the VHYS pin, which can set the threshold from zero to the maximum allowed input swing. The VHYS pin will self-bias to a nomial value that will be appropriate for most ap plicati ons (30-150mV p-p input level). Although uncalibrated for nominal level, gain and linearity, the VHYS pin can be externally set to adjust the threshold lev el over the entire rang e of the input signal, from z ero to the maximum l evel allowed at the input.

Table 2: Memory Map

Address Access Description

00h R/W Output Y0’s programmed input channel ( write and then assert CONFIG to program) 01h R/W Output Y1’s programmed input channel

... ... ...

10h R/W Output Y16’s programmed input channel 11h R/W Internal output Y17’s programmed input channel

... ... ...

20h R/W Internal output Y32’s programmed input channel 21h R/O Rx Activity monitor for inputs A0, A1,A2,A3 ( Logic ‘1’=No activity) 22h R/O Rx Activity monitor for inputs A4, A5,A6,A7 23h R/O Rx Activity monitor for inputs A8, A9,A10,A11 24h R/O Rx Activity monitor for inputs A12, A13,A14,A15 25h R/O Rx Activity monitor for input A16

Datasheet

VSC834

Page 4 G52247-0, Rev 4.2

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

02/09/01

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

with Input Signal Activity (ISA) Monitoring

2.5Gb/s 17x17 Crosspoin t Switch

AC Characteristics

Table 3: Data Path

Parameter Description Min Typ Max Units

RATE

ISKW

OSKW

tR, t

, t

Note: Unless otherwise stated, all specifications are guaranteed but not tested. Note 1: Skew between any two input channels to a given output. Note 2: Skew between any two output channels from the same input channel. Note 3: Required for high-speed output rise/fall spec at F Note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data

Data rate - - 2.5 Gb/s Input channel delay skew (1) - 300 - ps Output channel delay skew (2) - 300 - ps High-speed input rise/fall times, 20% to 80% (3) - - 150 ps High-speed output rise/fall times, 20% to 80% - - 150 ps Output data eye jitter, peak-peak, 223 PRBS (4) - - 100 ps

=2.5 Gbits/s. For lower rate signals, use 0.375/F

RATE

Figure 2: Interrupt Timing (Change in Monitor State Registers)

RATE

MONCLK

Monitor State

Monitor State Reg

INTB

CSB RDB

ADDR[5:0]

DATA[4:0]

Figure 3: Interrupt Timing (No Change in Monitor State Registers)

MONCLK

Monitor State

Monitor State Reg

sRDB

hRDB

tsDATA

INTB

G52247-0, Rev 4.2 Page 5 02/09/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

+ 11 hidden pages