VITESSE VSC8164QR Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

SC8164

2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux

Features

• 2.488Gb/s 1:16 Demultiplexer

• Tar geted for SONET OC-48 / SDH STM-16
Applications

• Supports FEC rates up to 2.7Gb/s

• Differential LVPECL Low Speed Interface

• Single +3.3V Supply

• 128 Pin 14x20mm PQFP Package

General Description

The VSC8164 is a 1:16 demultiplexer for use in SONET/SDH systems operating at a standard 2.488Gb/s
data rate or forward error correction (FEC) data rate up to 2.7Gb/s. The device operates using a single 3.3V
power supply, and is packaged in a thermally enhanced plastic package. The thermal performance of the
128PQFP allows the use of the VSC8164 without a heat sink under most thermal conditions.

VSC8164 Block DIagram

Output Register

DI+

DI-

D0+
D0-

HSCLKI+
HSCLKI-

Divide by
16

Divide by
2

D15+
D15-

CLK16O+
CLK16O-

CLK32O+
CLK32O-

Functional Description

Low Speed Interface

The demultiplexed serial stream is made available by a 16 bit differential LVPEC L interface D[15:0] with
accompanying differential LVPECL divide by 16 clock CLK16O
speed LVPECL output drivers are designed to drive a 50
terminated with a spli t end terminat ion scheme (see Figur e 1), or DC ter minate d b y 50
(see Figure 2). At any time, the equivalent split-end termination technique can be substituted for the traditional
50

Ω to V

coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the
downstream device were to have internal termination, the line to line 100
divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.

-2V on each line. AC coupling can be a chi eved by a number of methods. Figure 3 illustrat es an AC

CC

Ω transmission line. The transmission line can be DC

± and divide by 32 clock CLK32O±. The low

Ω to V

Ω resistor may not be necessary. The

-2V on each line

CC

G52239-0, Rev. 3.3  VITESSE SEMICONDUCTOR CORPORATION Page 1
5/17/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

2.488 Gbit/sec to 2.7Gbit/sec

Preliminary Datasheet

1:16 SONET/SDH Demux

Figure 1: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

VCC

VSC8164

R1||R2 = Zo , R1 = 125Ω R2 = 83Ω

VCCR2 + VEER1

R1+R2

Figure 2: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

= V

Z

Z

o

o

Term

VEE

R1

R2

R1

downstream

R2

downstream

VSC8164

Z

o

VSC8164

R1 =50Ω
VCC-2V

Figure 3: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

VSC8164

Z

o

Z

o

50Ω

50Ω

V

CC

100nF

100nF

-2V

R1 =50

Ω

VCC-2V

downstream

bias point
generated
internally

Page 2  VITESSE SEMICONDUCTOR CORPORATION G52239-0, Rev. 3.3

741 Calle Plano, Camarillo, CA 93012 • 805/38 8-37 00 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

SC8164

High Speed Interface

2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux

The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high
speed inputs DI and HSC LKI. The da ta and clock inputs are in ternally te rminated by a ce nter-tapped resi stor
network. For differential input DC coupling, the network is terminated to the appropriate termination voltage

V

(pins HSDREF, HSCLKREF) providing a 50Ω to V

Term

For differential input AC coupling, the network is terminated to

termination for both true and complement inputs.

Term

V

via a blocking capacitor.

Term

In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial dat a and clock inputs ha ve the same circuit
topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input sig­nal is driven differentially and DC-coupled to the part, the mid-point of the input signal sw ing should be cen­tered about this reference voltage and not exceed the maximum allowable amplitude (

∆V

CMI

, ∆V

IHSDC

single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage
which has better temperature and power supply nois e rejection than the on-chip r esistor divider. The external
reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal,
and can be connected to either side of the differential gate.

Figure 4: High Speed Serial Clock and Data Inputs

Chip Boundary

). For

VCC = 3.3V

Z

Supplies

C

TYP = 100 nF

IN

TYP = 100 nF

C

AC

O

V

Term

Z

O

C

IN

C

AC

C

IN

50Ω

50Ω

= 0V

V

EE

This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
use the device in a ECL environment with a negative 3.3V supply, t hen VCC will be ground and VEE w ill be -

3.3V.

G52239-0, Rev. 3.3  VITESSE SEMICONDUCTOR CORPORATION Page 3
5/17/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux

Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
on each V
also be placed in parallel with the 0.1
low inductance ceramic SMT X7R devices. For the 0.1

0.01

µF and 0.001µF capacitors can be either 0603 or 0402 packages.

For low frequency decoupling, 47

board’s main +3.3V power supply and placed close to the C-L-C pi filter.

If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V

must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.

CC

power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should

CC

power supply be decoupled using a 0.1µF and 0.01µF capacit or placed in parallel

CC

µF and 0.01µF capacitors mentioned above. Recommended capacitors are

µF capacitor, a 0603 package should be used. The

µF tantalum low inductance SMT caps should be sprinkled over the

AC Characteristics

Figure 5: AC Timing Waveforms

CLK16O+

Parallel data clock output

t

Preliminary Datasheet

VSC8164

pdd

D(0...15)+

Parallel data outputs

CLK32O+

Parallel data clock output

DI+

High speed differential serial data input

HSCLKI+

High speed differential clock input

VALID DATA (1) VALID DATA (2)

t

pd32

Figure 6: High Speed Input Timing

D0

D1 D2

D4 D5 D6 D7 D8 D9 D10 D11 D12

D3

t

dsu

D13D14 D15

t

dh

Page 4  VITESSE SEMICONDUCTOR CORPORATION G52239-0, Rev. 3.3

741 Calle Plano, Camarillo, CA 93012 • 805/38 8-37 00 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

SC8164

Figure 7: Differential and Single Ended Input and Output Voltage Measurement

2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux

b

Single

= α

Ended

a

b

Swing

Differential
Swing

= α

a

* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing.

Differential swing is specified as equal in magnitude to single ended swing.

Table 1: AC Characteristics

Parameters Description Min Max Units Conditions

t

pdd

t

pd32

tDR, t

t

, t

CLKR

CLK16O

t

dsu

t

dh

HSCLKI

DF

CLKF

D

D

Data valid from falling
edge of CLK16O+

CLK32O transition from
falling edge of CLK16O+

D[15:0]+/- rise and fall
times

CLK16O+/- rise and fall
times

CLK16O+/- duty cycle
distortion

DI+ setup time with respect
to falling edge of
HSCLKI+

DI+ hold time with respect
to falling edge of
HSCLKI+

HSCLKI+/- duty cycle
distortion

0800ps.

01.0ns.

—

—

45 55

100 — ps

75 — ps

40 60

400 ps

250 ps

% of
clock
cycle

% of
clock
cycle

20% to 80% into 50 Ohm load.
See Figure 7

20% to 80% into 50 Ohm load.
See Figure 7

High speed clock input at 2.488GHz

G52239-0, Rev. 3.3  VITESSE SEMICONDUCTOR CORPORATION Page 5
5/17/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]