VITESSE VSC8161 Datasheet



VITESSE

SEMICONDUCTOR CORPORATION

Page 1

8/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

SC8161

2.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

G52208-0, Rev.2.1

Features

General Description

The VSC8161 combines a Laser Driver and a clock multiplier with a 16:1 multiplexer to provide a single­chip solution. The 16-bit data word is latched by an internal version of the reference clock, and is bit-multi­plexed up to 2.488GHz. The on-chip PLL generates the internal 2.488GHz clock, which remains locked to the

155.52 MHz reference clock. The on-chip laser driver pro vides up to 60 mA modulation current and 50 mA bias
current.

VSC8161 Functional Block Diagram

• 16:1 Multiplexer Integrated with Clock
Multiplier and Laser Driver

• Monolithic Phase Locked Loop

• Laser Driver Provides up to 110 mA Current

• Differential 16-bit Parallel Data

• 100 pin 14x14 Plastic Quad Flat Package

• Jitter Generation Meets SONET OC-48 and
SDH STM-16 Requirements

• Companion to the VSC8162 1:16 Demulti­plexer with Clock Recovery

• Supports Parity Checking at the 16-bit
Parallel Interface

D0+

D0-

D15+

D15-

PARITY+

PARITY-

CLK16+

CLK16-

REFCK+

REFCK-

DINVERT
VIP
VIB

IOUT+
IOUT-

MIP

MIB

DINVALID+
DINVALID-

Output
Retime

Parity

Register

2.5GHz
PLL

Divide

by 16

Input Register

Page 2



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8161

.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

G52208-0, Rev.2.1

Functional Description

Multiplexer

The VSC8161 takes incoming 16-bit wide data at 155 MHz, D0 through D15, and converts it into a serial
data stream, with D0 transmitted first. CLK16 is the 155MHz low-speed clock output which is created by divid­ing the internally generated 2.488 GHz clock by 16. The upstream device should use the CLK16 as its internal
reference and to register its low-speed data and parity output signals (See Fig 1). Care needs to be taken to meet
the data setup and hold timing on the parallel data.

Figure 1: VSC8161 Parallel Data Interface

The timing relationship between the VSC8161 and the upstream device is described by the waveforms in
Fig. 5 and the associated parameters: t

D

, t

DSU

, and t

DH

appearing in Table 1.

The polarity of the serialized data can be inverted by the assertion of the DINVERT input. In either case,
however, the signal is retimed prior to the Laser Driver section of the VSC8161.

Clock Multiplier

The clock multiplier is fully integrated. No external components are needed. Jitter Generation of the clock
multiplier meets the requirement of Bellcore’s GR-253 (SONET) document. As in all of the frequency synthe­sizers that employ a PLL, it is important to choose REFCK to be as

jitter-free as possible.

In Out

CK

In Out

CK

"upstream device"

D [0:15]

VSC8161

CLK16

16

16

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VITESSE

SEMICONDUCTOR CORPORATION

Page 3

8/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

SC8161

2.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

G52208-0, Rev.2.1

Figure 2: Single-ended AC-Coupling for REFCK+, REFCK– Inputs

A differential input buffer is used to supply the reference clock to the clock multiplier. Internal biasing will
position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can
either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 2 shows the
configuration for single-ended, AC-coupled operation. In the case of direct coupled and single-ended input, it is
recommended that a stable V

REF

for ECL levels be used for the complementary input if the input common mode

voltage is not -1.32V.

Parity

Systems employing internal parity are supported by the VSC8161. A parity check is performed between the
PARITY input and the 16 data bits. Even parity is expected. In other words, the DINVALID output is the XOR
of all 16 parallel data bits and the PARITY input. If the Exclusive-OR gate fails to confirm even parity, the DIN­VALID output will be asserted. DINVALID becomes available t

DV

after the falling edge of CLK16. DINVALID
is a NRZ pulse that is updated every 6.4 ns, i.e., the period of CLK16. The timing relationship of DINVALID to
CLK16 is shown in Figure 6.

The DINVALID pins may be left open if parity is unused.

Laser Driver

The laser driver contained in the VSC8161 provides up to 50mA of DC bias current and 60 mA of modula­tion current. Direct control of the laser bias and modulation current is provided. Laser bias and modulation cur­rent levels are monitored and controlled using external components.

A schematic representation of the laser driver output stage showing the relationship between the the exter­nal controls signals and the internal circuitry is provided in Figure 3.

V

TT

REFCK-

V

CC

= GND

V

TT

= -2V

-1.32V

-1.32V

R

| |

= 1kΩ (Min.)

C

IN

C

SE

V

TT

Chip Boundary

CIN TYP = 0.1µF
C

SE

TYP = 0.1µF for single ended applications. (Capacitor values are

Z

O

RT = Z

O

selected for REFCK = 155.52 MHz)

REFCK+

Page 4



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8161

.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

G52208-0, Rev.2.1

Figure 3: Laser Driver Output

IOUT+, IOUT- Outputs

The IOUT+ and IOUT- pins are designed to interface to a laser diode. A logic “0” appears as less current
(higher voltage) at the IOUT+ pin, and less light from a series laser diode. A logic “1” appears as more current
(lower voltage) at the IOUT+ pin, and more light from a series laser diode. The polarity can be reversed through
use of the DINVERT signal pin. The current difference depends upon the voltage (VIP - MIP) applied at the
VIP pin. Applying (VIP - MIP) = 0V will turn off the modulation current. Applying (VIP - MIP) = approxi­mately 2V will maximize the modulation current. Applying (VIP - MIP) up to 5.2V is allowed, but not likely to
be useful. Use caution to avoid exceeding the absolute maximum current ratings (see table). Operation of the
bias current is independent of, and similar to, the operation of the modulation current. Pins MIB and VIB are
used to monitor and control the bias current.

It is recommended that feed back circuits be utilized to regulate the desired modulation and bias currents.
This is illustrated with examples in figure 4. Separate circuits are used, since the modulation and bias currents
are independent.

X X

IOUT– IOUT+

OUTPUT
DIFF
PAIR

X

MIB

X

VIP

X

MIP

I

MOD

I

BIAS

X

VIB

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VITESSE

SEMICONDUCTOR CORPORATION

Page 5

8/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

SC8161

2.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

G52208-0, Rev.2.1

Figure 4: Recommended Modulation and Bias Current Control Circuits

Supplies

The VSC8161 is designed to operate with V

EE

= -5.2V, V

TT

= -2.0V and V

CC

= GND (0.0V). However, the

part can be operated in an all positive supply en vironment, or a mix ed positi ve and ne gati v e supply en vironment.

To operate in an all positive supply environment, each of the supply voltages must be shifted up by 5.2V
such that V

EE

will now be GND, V

TT

= +3.2V and V

CC

= +5.2V. To operate in a mixed positive and negative

supply environment, each of the supply voltages must be shifted up by 2.0V such that V

TT

will now be GND,

V

EE

= -3.2V and V

CC

= +2.0V

.

Bear in mind that termination voltages must be adjusted to reflect any shift in supply voltages.

X

VIP

X

MIP

–

+

1Ω

–

+

V

EE

V

P

(0-60mV)

X

VIB

X

MIB

–

+

1Ω

–

+

V

EE

V

B

(0-50mV)

Bias Current Control Circuit

Modulation Current Control Circuit

For Example to get 40mA of modulation current, VP is set to 40mV (40mA x 1Ω = 40mV)