VITESSE VSC8131 Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC8131

32:1 SONET/SDH Mux with Clock Generator

2.488 Gbit/sec

Features

• 2.488Gb/s 32:1 Mux with Clock Generator

• SONET ST S-48/SDH STM- 16

• LVPECL Differential High Speed Serial Data
and Clock Outputs

• 32 TTL Parallel Data Inputs with Odd/Even
Parity Check

• 128 Pin, 14x20x2 mm Enhanced-PQFP

• Single 3.3V Supply

• 2.15W Max Power Dissipation

General Description

The VSC8131 multiplexes 32 TTL compatible 77.76Mb/s Parallel Data Inputs (D0-D31) into a single
LVPECL 2.488 Gb/s serial output (DO+
Clock Multiplier Unit (CMU) generates a LVPECL 2.488 GHz clock signal (CO+

LVPECL compliant 77.76MHz referen ce clock (REFCLK+
A Divide-by-32 TTL clock output (CK78OUT) is used as a clock input (CK78IN) for timing of the parallel data
inputs. Parity Checking (PARBIT) is performed on the incoming data with a selectable even or odd TTL parity mode
input (PARMODE) and a TTL P arity Erro r (PARERR) output. A TTL Loss Of Lock (LOL) output indicator is used to
report the loss of the REFCLK+

or for conditions resulting in the CMU losing lock to incom ing clock.

) for use in SONET S TS-48/SDH STM -16 system s. An in tegrated

) from an externally supplied

) which is used to retime the transmitted serialized data.

VSC8131 Block DIagram

CK78IN

PARMODE

PARBIT

D0

Parallel Data
Receivers

D31

CK78OUT

REFCLK+
REFCLK-

Input

Registers

Clock/32

32:1

Multiplexer

Timing

Generator

CMU

x32

Bit Rate Clock

Parity

Register

Output

Register

PARERR

DO+
DO-

CO+

CO-

LOL



G52249-0, Rev. 3.0

11/9/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 1

VITESSE

t

SEMICONDUCTOR CORPORATION

2.488 Gbit/sec
32:1 SONET/SDH Mux with Clock Generator

Preliminary Datashee

VSC8131

Functional Description

Low Speed Interface

The timing for the low speed parallel interface is based upon the CK78OUT output signal. The intent is to
have the device upstream from the VSC8131 use the CK78OUT clock signal as the timing source for its final
output stage latch. CK78IN is to be driven by CK78OUT, refer to Figure 1. This reduces the setup time of the
VSC8131. The maximum propagation delay permitted from CK78OUT to CK78IN is specified by
the AC Characterist ics. The setup and hold time of th e data i nputs are specif ied wit h respect to t he rising edg e of
CK78IN. D0-D31, CK78OUT, and CK78IN are TTL compatible inputs.

Figure 1: Low Speed System Interface

33

D[0:31], PARBIT

CK78IN

33

Upstream

Device

CK78OUT

VSC8131

t

CKPROP

in

REFCLK

2.488 GHz
PLL

Parity

A parity check is performed between the parity bit input (PARBIT) and the 32 parallel data inputs (D0­D31). Even versus odd parity checking is selected with PARMODE. Set PA RMODE low to test for odd parity.
Set PARMODE high to test for even parity. The parity error output (PARERR) is set to a logic high when a par­ity error has occurred. The PA RERR signal can be changed from an active high to active low signal by comple­menting the PARMODE input. PARE RR is re-calculated each time new parallel data is clocked in. The newly
calculated PARERR result is clocked out on the rising edge of CK78IN 2 cycles after the data is loaded. PAR­BIT, PARMODE, and PARERR conform to TTL output levels.

Divide by 32

Page 2 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52249-0, Rev. 3.0

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC8131

High Speed Data Output

The high speed data wil l be mu ltipl exed in the seq uenc e D0, D1 up to D31 with D0 being tran smitt ed first.
The high speed data output driver consists of a differential pair designed to drive a 50Ω transmission line. The
transmission line should be terminated with a 100Ω resistor at the load between the true and complement out­puts, refer to Figure 2. No connection to a termination voltage is required. The output driver is back terminated
to 50Ω on-chip, providing snubbing of any reflections. If used single-ended, the high speed output driver must
still be terminated differentially at the load with a 100Ω resistor between the true and complement output sig­nals.

High Speed Clock Output

The high speed clock output driver consists of a differential pair designed to drive a 50Ω transmission line.
The transmission line should be terminated with a 100Ω resistor at the load between the true and complement
output, refer to Figure 2. No connectio n to a termination voltage is required . The o utput driver is back termi­nated to 50Ω on-chip, providing a snubbing of any reflections. I f used single -ended, the high speed outpu t
driver must still be terminated differentially at the load with a 100Ω resistor between the true and complement
output signals.

Figure 2: Termination for High Speed Clock and Data Output Drivers

32:1 SONET/SDH Mux with Clock Generator

2.488 Gbit/sec

Pre-Driver

50Ω

V

V

CC

50Ω

100Ω

Z0 = 50Ω

EE



G52249-0, Rev. 3.0

11/9/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

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VITESSE

t

SEMICONDUCTOR CORPORATION

2.488 Gbit/sec
32:1 SONET/SDH Mux with Clock Generator

Clock Generator

An on-chip Phase Locked L oop (PLL ) generate s the 2.488 GHz t ransmit cl ock fro m the e xternal ly pro vid ed
REFCLK input. The on-chip PLL uses a low phase noise reactance based Voltage Controlled Oscillator (VCO)
with an on-chip loo p filter. The loop bandwidth of the P LL is wit hin the S ONET spec ified limit o f 2MHz. Th e
REFCLK is 77.76MHz and should be of high quality. Noise on the REFCLK below the loop band width of the
PLL will pass through the PLL and appear as jitter on the out put. Pr econ di ti oning of the REFCLK signal with a
VCXO may be required to a void passing REFCLK noise wi th gr eat er th an 4p s RM S of j i tter t o t he o ut put. Such
a condition would create an output from the VSC8131 which has the REFCLK noise in addition to the intrinsic
jitter from the VSC8131 itself . REFCLK is a LVPECL level and is requi red to be a dif fer enti al signal in order to
meet the 4pS RMS jitter spec. The true and complement inputs of the differential PECL receiver are internally
biased to VCC/2 so that the REFCLK signal ca n be AC coupled without using external bias resistors, re fer to
Figure 3. REFCLK can be DC coupled by simply over-driving the internal bias voltage.

Figure 3: REFCLK Internal Bias Configuration

V

= +3.3V

CC

Preliminary Datashee

VSC8131

V

INPUT

INPUT

VEE = 0V

Loss of Lock

The Loss Of Lock (LOL) o utput is used t o indicate if the CMU is locked. A loss of l ock conditio n is
reported when the CMU does not lock to the REF CLK frequency or when the REFCLK input signa l is not
present. LOL is high when the CMU is locked. LOL is low when the REFCLK in put sign al is not pr esen t ( input

floating due to cut line or input s tuck high or low). The LOL sig nal will appear as a pulse trai n of 1’s and 0’s
when the REFCLK is presen t, but the CMU is not locke d to the REFC LK’s frequency. The frequency of the
LOL pulse train can be anywhere from 500Hz to 50MHz.

2

V

2

CC

CC

All Resistors

3.3K

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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52249-0, Rev. 3.0

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC8131

Supplies

This device is specified as a LVPE CL device with a single +3.3V supply. Normal operation is to have

=+3.3V and VEE=ground. Should the user desire to use the device in an ECL environment with a negative

V

CC

3.3V supply, then V
are still referenced to V

Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
each V
also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are
low inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The

0.01µF and 0.001µF capacitors can be either 0603 or 0403 packages.

maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8131, the analog
power supply pins should be filtered from the main power supply with a 10µH C-L-C pi filter. If preferred, a
ferrite bead may be used to provide the isolation. The 0.1µF and 0.01µF decoupling capacitors are still required
and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).

main +3.3V power supply and placed close to the C-L-C pi filter.

pling V

power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should

CC

Extra care needs to be taken when decoupling the analog power supply pins (labeled V

For low frequency decoupling, 47µF tantalum low inductance SMT caps are sprinkled over the board’s

If the device i s being use d in an ECL environment wi th a ne gat i v e 3.3V sup ply, then all references to decou-

must be changed to VEE, and all references to decoupling +3.3V must be changed to -3.3V.

CC

will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL I/O signal s

CC

.

EE

power supply be d ecoup led using a 0.1µF and 0.01µF capacitor placed in parallel on

CC

32:1 SONET/SDH Mux with Clock Generator

2.488 Gbit/sec

). In order to

CCANA



G52249-0, Rev. 3.0

11/9/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 5