VITESSE VSC8115YA1, VSC8115YA, VSC8115YA2 Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Features

• Performs clock and data recovery for

622.08Mb/s (STS-12/OC-12/STM-4) or

155.52Mb/s (STS-3/OC-3/STM-1) NRZ data

• Meets Bellcore, ITU and ANSI Specifications
for Jitter Performance

• 19.44MHz reference frequency LVTTL Input

• Lock Detect output pin monitors data run length
and frequency drift from the reference clock

• Data is Retimed at the Output

• Active High Signal Detect LVPECL Input

• Low-jitter high speed outputs can be configured
as either LVPECL or low power LVDS

• Low power - 0.188 Watts Typical Power

• +3.3V Power Supply

• 20 Pin TSSOP Package

• Requires One External Capacitor

• PLL bypass operation facilitates the board
debug process

General Description

The VSC8115 functions as a clock and data recovery unit for SONET/SDH-based equipment to derive high
speed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s
(STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed
using an output flip-flop. Both recovered clock and retimed data outputs can be configured as LVDS or
LVPECL signals to facilitate a low-jitter and low power interface.

VSC8115 Block Diagram

STS12

BYPASS

DATAIN+/-

SD
LOCKREFN

REFCLK

G52272-0, Rev. 1.1

9/29/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

2

Divider

CAP+

Phase/

Freq

Detector

 VITESSE SEMICONDUCTOR CORPORATION Page 1

Loop Filter

CAP-

VCO

0

1

2

2

LOCKDET
DATAOUT+/-

CLKOUT+/-±

VITESSE

VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

Functional Description

The VSC8115 contains an on-chip PLL consisting of a phase/frequency detector, a loop filter using one
external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency divider.
The phase/frequency detector compares the phase relationship between the VCO output and an external

19.44MHz LVTTL reference clock to make coarse adjustment to the VCO block so that its output is held within
+500ppm of the reference clock. The use of reference clock minimizes the PLL lock time during power up and
provides a stable output clock source in the absence of serial input data. The phase/frequency detector also com­pares the phase relationship between the VCO output and the serial data input to make fine adjustment to the
VCO block. The loop filter converts the phase detector output into a smooth DC voltage. This DC voltage is
used as the input to the VCO block whose output frequency is a function of the input voltage. A programmable
frequency divider down converts the VCO output signal and provides two modes of operation: 622.08Mb/s
mode if STS12 is HIGH, or 155.52Mb/s mode if STS12 is LOW.

Lock Detection

The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to
indicate that the PLL is locked to the serial data inputs and that valid data and clock are present at the high speed
differential outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or
the VCO has drifted away from the local reference clock by more than 500 ppm.

Target Specification

Signal Detection

The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a
LVPECL input, and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate a loss
of signal condition and they are connected inside the part as shown in Figure 1. If either one of these two inputs
goes LOW and BYPASS is LOW, the VSC8115 will enter the loss of signal (LOS) state, and it will hold the
DATAOUT+/- output at logic LOW state. During the LOS state, the VSC8115 also will hold the output clock
CLKOUT+/- to within +500ppm of the REFCLK. See Table 1.

Most of the optical module has a signal detect output. This signal detect output indicates that there is suffi­cient optical power, and it is typically active HIGH. If the signal detect output on the optical module is
LVPECL, it should be connected directly to the SD input on the VSC8115, and the LOCKREFN input needs to
be tied HIGH. If the signal detect output is LVTTL, it should be connected directly to the LOCKREFN input,
and the SD input needs to be tied HIGH.

The SD and LOCKREFN inputs also can be used for other applications when the users need to hold the
CLKOUT+/- output to within +500ppm of the reference clock and to force the DATAOUT+/- output to the
logic LOW state.

PLL Bypass Operation

The BYPASS pin is intended for use in production test, and it should be set at logic LOW in the normal
operation. If both BYPASS and MODE pins are set at logic HIGH, the VSC8115 will bypass the PLL and will
present an inverted version of the REFCLK to the clock output CLKOUT+/-. The REFCLK’s rising edge is
used to capture data at DATAIN+/- and transmit data at DATAOUT+/-. This bypass operation can be used to
facilitate the board debug process.

Page 2  VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

G52272-0, Rev. 1.1

9/29/00

VITESSE

SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation

DATAIN+/-

REFCLK

STS12

BYPASS

LOCKREFN

SD

Table 1: Signal Detection and PLL Bypass Operation Control

2

PLL Clock
(on-chip)

0

1

LOS

(on-chip)

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

2

DATAOUT+/-

2

CLKOUT+/-±

STS12 BYPASS LOCKREFN SD LOS DATAOUT CLKOUT

1 0 1 1 0 DATIN PLL Clock
1 0 1 0 1 LOW PLL Clock
1 0 0 1 1 LOW PLL Clock
1 0 0 0 1 LOW PLL Clock
1 1 X X 0 DATIN REFCLK
0 0 1 1 0 DATIN PLL Clock
0 0 1 0 1 LOW PLL Clock
0 0 0 1 1 LOW PLL Clock
0 0 0 0 1 LOW PLL Clock
0 1 X X 0 Not Allowed Not Allowed

G52272-0, Rev. 1.1

9/29/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 3

VITESSE

VSC8115

500

±

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

AC Characteristics

Table 2: Performance Specifications

Parameters Min Typ Max Units Conditions

VCO Center Frequency

CRU’s Reference Clock Frequency

Tolerance

OC-12/STS12 Capture Range

Clock Output Duty Cycle

Acquisition Lock Time OC-12/STS-12

LVDS Output Rise & Fall Times

CLKOUT+/- Jitter Generation

OC-12/STS-12 Jitter Tolerance

— 622.08 — MHz

-250 — +250 ppm

— — ppm

45 — 55 % of UI

— — 16 µs

— — 600 ps

— 0.005 0.01 U.I.

0.5 — — U.I.

Target Specification

With respect to the fixed
reference frequency

20% Minimum transition
density

Valid REFCLK and device
already powered up

10% to 90%, with 100Ω & 5pF
capacitive equivalent load

No more than 14ps rms jitter on
DATAIN+/-

Sinusoidal input jitter of
DATAIN+/- from 250KHz to
5MHz

Page 4  VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

G52272-0, Rev. 1.1

9/29/00