VITESSE VSC8062QH, VSC8061FC, VSC8061FI Datasheet

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8061/VSC8062

Multiplexer/Demultiplexer Chipset

Features

VITESSE

2.5Gb/s 16-Bit

• Serial Data Rate up to 2.5Gb/s

• 16-Bit Wide ECL 100K Compatible Parallel Data
Interface

• Differential High-Speed Data Outputs

• Differential or Single-Ended High-Speed Data and
Clock Inputs

• On-Chip Phase Detector (VSC8061 Multiplexer)

• Power Dissipation: VSC8061:2.0W(max),
VSC8062: 1.7W(max)

• Standard ECL Power Supplies: V
V

= -2.0V

TT

• Commercial (0oC to +70oC) or Industrial (-40oC
to +85o C) Temperature Range

• Available in 52-Pin Ceramic Leaded Chip Carrier
or 52-Pin Plastic Quad Flat Pack Packages

= -5.2V,

EE

Functional Description

The VSC8061 and VSC8062 are high-speed interface devices capable of data rates up to 2.5Gb/s. The
devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve high­speed and low power dissipation. For ease of system design using these products, both devices use industry­standard -5.2V and -2V power supplies, and have ECL-compatible I/O for parallel data interfaces. Typical
applications include telecommunication transmission and instrumentation.

VSC8061 Multiplexer

The VSC8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates
a divide-by-16 clock from the high-speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended
ECL compatible inputs (D0...D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial
output (DO/DON). The internal timing of the VSC8061 is referenced to the negative going edge of the high­speed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The
setup and hold time of the parallel inputs (D[0:15]) are specified with respect to the falling edge of CLK16, so
that CLK16/CLK16N can be used to clock the data source of D[0:15]. The on-chip phase detector monitors the
phase relationship between the internally generated divide-by-16 clock and an externally supplied low-speed
reference clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or
down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase
Locked Loop (PLL) to implement a clock multiplication function.

In applications where a 2.5GHz system clock is provided, and the phase detector function is not required, it
is recommended to connect one side of the DCLK/DCLKN input to VTT through a 50Ω resistor. The U and D
output can be left open and unused.

VSC8062 Demultiplexer

The VSC8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock
from the high-speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s
and deserializes it into 16 parallel single-ended ECL compatible outputs (D[0:15]) at data rates up to 156 Mb/s.
The internal timing of the VSC8062 is referenced to the negative going edge of the high-speed clock true input
(CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the
parallel data outputs (D[0:15]) are specified with respect to the falling edge of CLK16, so that CLK16/CLK16N
can be used to clock the destination of D[0:15].

G52069-0, Rev 4.3 Page 1
05/11/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

VSC8061/VSC8062

SEMICONDUCTOR CORPORATION

2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset

Figure 1: VSC8061 Block Diagram

D

0

D

1

Parallel Data
Receivers

D

15

Input

Registers

CLK

CLKN

16:1

Multiplexer

Timing

Generator

Bit Rate Clock

Output

Register

Data Sheet

DO
DON

CLK16
CLK16N

DCLK

DCLKN

DI

DIN

CLK

CLKN

Figure 2: VSC8062 Block Diagram

Input

Register

De-

Multiplexer

1:16

Timing

Generator

Phase

Detector

Output

Registers

D

D

Parallel Data
Outputs

D

CLK16
CLK16N

U
D

0

1

15

Page 2 G52069-0, Rev 4.3

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

05/11/01

VITESSE

SEMICONDUCTOR CORPORATION

VSC8061/VSC8062

Multiplexer/Demultiplexer Chipset

Data Sheet

VSC8061 Multiplexer AC Characteristics (Over recommended operating range)

Figure 3: VSC8061 Multiplexer Waveforms

t

CLK

2.5Gb/s 16-Bit

High-speed differential clock input

CLK (CLKN)

t

D

CLK16 (CLK16N)

Parallel data clock output

D[0:15]

Parallel data inputs

t

DSU

VALID DATA (1)

t

DH

VALID DATA (2)

DCLK (DCLKN)

Parallel data clock input

DO (DON)

High-speed differential serial data output

NOTE:

Table 1: VSC8061 AC Characteristics

Parameter Description Min Typ Max Units Conditions

t

CLK

t

D

t

DSU

t

DH

t

DC

tR, t

F

tR, t

F

tR, t

F

tR, t

F

NOTE: (1) Devices are guaranteed to operate to a maximum frequency of 2.5GHz.

Clock period
CLK16, DCLK period (t
Parallel data set-up time with respect to CLK16

falling edge
Data hold time with respect to CLK16 falling

edge
CLK16 duty cycle 40 60 %
DCLK (DCLKN) rise and fall times 1.5 ns 10% to 90%
D[0:15] rise and fall times 2.0 ns 10% to 90%
CLK16 (CLK16N) rise and fall times 0.5 1.0 ns 10% to 90%
DO (DON) rise and fall times 150 165 ps 20% to 80%

=Don’t care

(1)

x 16) 6.4 15.6 ns

CLK

t

D

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12 D13 D14 D15

Serialized Data

t

D

400 ps

2.0 ns

0.5 ns

G52069-0, Rev 4.3 Page 3
05/11/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

VSC8061/VSC8062

SEMICONDUCTOR CORPORATION

2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset

Data Sheet

VSC8061 Phase Detector Logic Diagram

The internal phase detector of the VSC8061 compares the phase difference between the internally gener­ated divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in
phase, the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses
with pulse widths proportional to the phase difference will be present at the U output. Conversely, if DCLK pre­cedes CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D
output. The other output will remain low. The Phase Detector ignores phase differences for falling edges. This
circuitry is useful for implementing a Clock Multiplier Unit (CMU) function with the VSC8061. For example,
the DLCK can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator
(VCO) at 16x the frequency of the reference clock can be used as the CLK input for the VSC8061. The phase
detector outputs (U and D) can then be used by an external integrator to generate an output that controls the
VCO. The generated 16x clock from the VCO will be phase-locked to the reference clock.

Figure 4: VSC8061 Phase Detector Logic Diagram

CLK16

RSQ

U

CLK16

DCLK

S
R Q

DCLK

Figure 5: Phase Detector Input and Output Waveforms

~

~

~

~

U

D

~

~
~

~

D

Page 4 G52069-0, Rev 4.3

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

05/11/01

VITESSE

SEMICONDUCTOR CORPORATION

VSC8061/VSC8062

Multiplexer/Demultiplexer Chipset

Data Sheet

VSC8062 Demultiplexer AC Characteristics (Over recommended operating range)

Figure 6: VSC8062 Timing Diagram

t

High-speed differential clock input

CLK (CLKN)

DI (DIN)

High-speed serial data input

Parallel data clock output

CLK16

D0
D1

CLK

t

D

t

BD

t

D

2.5Gb/s 16-Bit

Data Outputs

Demultiplexed Parallel

D15

Table 2: VSC8062 AC Characteristics

Parameter Description Min Typ Max Units Conditions

t

CLK

t

D

t

DSU

t

DH

NOTES: (1) If t

(2) t

SU

(3) At t

Clock period
BYTE CLK16 period (t
CLK16 falling edge output to valid data 1.0 3.0 ns

Phase Margin =

Serial data phase timing margin with respect to
high-speed clock

changes, all remaining parameters change as indicated by the equations.

CLK

and t

are setup and hold times of the serial data input register.

H

= 400ps.

CLK

(1)

x 16) 6.4 ns

CLK

tSUtH+



1

-------------------–



t

CLK

(2)

360°×

400 ps

(3)

180

degrees

G52069-0, Rev 4.3 Page 5
05/11/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

VSC8061/VSC8062

SEMICONDUCTOR CORPORATION

2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset

DC Characteristics

Table 3: ECL Inputs and Outputs

(Over recommended operating conditions with internal V

REF, VCC

Parameter Description Min Typ Max Units Conditions

V

OH

V

OL

V

IH

V

IL

∆VECL
∆VECL

Note: Differential ECL output pins must be terminated identically.

Output HIGH voltage -1100 -700 mV

Output LOW voltage V

Input HIGH voltage -1040 -600 mV

Input LOW voltage V
Output voltage swing 0.850 V Output load 50Ω to V

OUT

Input voltage swing 0.600 0.800 1.2 V AC-coupled

IN

Table 4: Power Dissipation

(Over recommended operating conditions, VCC= GND, outputs open circuit)

= GND, output load = 50Ω to -2.0V).

TT

TT

-1750 mV

-1600 mV

VIN = VIH (max) or VIL
(min)

VIN = VIH (max) or VIL
(min)

Guaranteed HIGH signal
for all inputs

Guaranteed LOW signal
for all inputs

Data Sheet

TT

Parameter Description Min Typ Max Units Conditions

I

EE

I

TT

P

D

Power supply current from V

Power supply current from V

Power dissipation

VSC8061 260 mV

EE

VSC8062 220 mV
VSC8061 260 mV

TT

VSC8062 230 mV
VSC8061 2.0 W
VSC8062 1.7 W

Table 5: High-Speed Input and Output Specifications

(Over recommended operating conditions, VCC = GND, output load = 50Ω to -2.0V)

Parameter Description Min Typ Max Units Conditions

∆V

HSOUT

∆V

HSIN

tR, t

F

NOTES: (1) Built-in references generator, the high-speed inputs are designed for AC-coupling.

Output voltage swing 0.7 0.9 V Output load, 50Ω to -2.0V
Input voltage swing See Table 6 AC-coupled

Same for all data rates; no

Input voltage rise and fall time (high-speed) 0.2 1.5 ns

(2) If a high-speed input is driven single-ended, a capacitor should be connected between the unused high-speed or complement

input and V

(see Figures 7 and 8).

TT

worse than sine wave at
max speed

Page 6 G52069-0, Rev 4.3

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

05/11/01