VITESSE VSC7217UC Datasheet

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Features

• 4 ANSI X3T11 Fibre Channel and IEEE

802.3z Gigabit Ethernet Compliant Trans­ceivers

• Over 8 Gb/s Duplex Raw Data Rate

• Redundant PECL Tx Outputs and Rx Inputs

• 8B/10B Encoder/Decoder per Channel,
Optional Encoder/Decoder Bypass Operation

• “ASIC-FriendlyTM” Timing Options for
Transmitter Parallel Input Data

• Elastic Buffers for Intra/Inter-Chip Cable
Deskewing and Channel-to-Channel Align­ment

• Tx/Rx Rate Matching via IDLE Insertion/
Deletion

VITESSE

Multi-Gigabit Interconnect Chip

• Compatible with VSC7211/7212/7214

• Fast-Locking CRU: 100-Bit Clock Periods

• Received Data Aligned to Local REFCLK or to
Recovered Clock

• PECL Rx Signal Detect and Cable Equalization

• Per-Channel Serial Tx-to-Rx and Parallel Rx-to­Tx Internal Loopback Modes

• Clock Multiplier Generates Baud Rate Clock

• Automatic Lock-to-Reference

• JTAG Boundary Scan Support for TTL I/O

• Built-In Self Test

• 3.3V Supply, 3.0W Typ, 3.5W Max.

• 256-pin, 27mm BGA Package

VSC7217 Block Diagram

TRANSMITTER

PTXEND

8B/10B

Encode

RTXEND
PTXENC

8B/10B

Encode

RTXENC
PTXENB

8B/10B

Encode

RTXENB
PTXENA

8B/10B

Encode

RTXENA

Tx Clock

REFCLK

10

10

10

10

TBERRA
TBERRB
TBERRC
TBERRD

TD(7:0)

C/DD

WSEND

TC(7:0)

C/DC

WSENC

TB(7:0)

C/DB

WSENB

TA(7:0)

C/DA

WSENA

KCHAR

TBCA

TBCB
TBCC
TBCD
DUAL

REFCLKP
REFCLKN

8 8

D Q

8 8

D Q

8 8

D Q

8 8

D Q

4

x20/x10

Clock Gen

CAP0 CAP1

LBTXD

PTXD+
PTXD­RTXD+
RTXD-

LBTXC

PTXC+
PTXC­RTXC+
RTXC-

LBTXB

PTXB+
PTXB­RTXB+
RTXB-

LBTXA

PTXA+
PTXA­RTXA+
RTXA-

LBEND(1:0)

RXP/RD

PRXD+
PRXD­RRXD+
RRXD-

LBENC(1:0)

RXP/RC

PRXC+
PRXC­RRXC+
RRXC-

LBENB(1:0)

RXP/RB

PRXB+
PRXB­RRXB+
RRXB-

LBENA(1:0)

RXP/RA

PRXA+
PRXA­RRXA+
RRXA-

TMODE(2:0)
RMODE(1:0)

RECEIVER

Clk/Data

Recovery

PSDETD
RSDETD

Clk/Data

Recovery

PSDETC
RSDETC

Clk/Data

Recovery

PSDETB
RSDETB

Clk/Data

Recovery

PSDETA
RSDETA

RESETN

ENDEC

BIST

10

10

10

10

8B/10B

Decode

8B/10B

Decode

8B/10B

Decode

8B/10B

Decode

FLOCK

WSI

TRSTN

TMS
TDI

TCK

8
3

8
3

8
3

8
3

Elastic

Buffer

Elastic

Buffer

Elastic

Buffer

Elastic

Buffer

Channel

Align

JTAG

Boundary

Scan

8

8

8

8

RD(7:0)
IDLED

KCHD
ERRD

RCLKD
RCLKDN

RC7:0)
IDLEC

KCHC
ERRC

RCLKC
RCLKCN

RB(7:0)
IDLEB

KCHB
ERRB

RCLKB
RCLKBN

RA(7:0)
IDLEA

KCHA
ERRD

RCLKA
RCLKAN

WSO

TDO

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 1

VITESSE

Preliminary Datasheet

VSC7217

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

General Description

The VSC7217 is a quad 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high band­width interconnection between busses, backplanes, or other subsystems. Four Fibre Channel and Gigabit Ether­net compliant transceivers provide up to 8.32Gb/s of duplex raw data transfer. Each channel can be operated at
a maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at
98MHz). For the entire chip in duplex mode, the aggregate transfer rate is between 6.3Gb/s and 8.7Gb/s. The
VSC7217 contains four 8B/10B encoders, serializers, de-serializers, 8B/10B decoders and elastic buffers which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as four non-encoded 10-bit transceivers.

Notation

In this document, each of the four channels are identified as channel A, B, C or D. When discussing a signal
on any specific channel, the signal will have the channel letter embedded in the name: TA(7:0). When referring
to the common behavior of a signal which is used on each of the four channels, a lower case “n” is used in the
signal name: Tn(7:0). Differential signals, such as PTXA+ and PTXA-, may be referred to as a single signal,
PTXA, by dropping reference to the “+” and “-”. REFCLK refers either to the PECL/TTL input pair REF­CLKP/REFCLKN, which can be differential PECL (using both REFCLKP and REFCLKN) or single-ended
TTL (using REFCLKP and leaving REFCLKN open).

Clock Synthesizer

Depending on the state of the DUAL input, the VSC7217 clock synthesizer multiplies the reference fre­quency provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud rate
clock between 0.98GHz and 1.36 GHz. The on-chip Phase Lock Loop (PLL) uses a single external 0.1µF
capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer
ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient. NPO
is preferred but X7R may be acceptable. These capacitors are used to minimize the impact of common mode
noise on the Clock Multiplier Unit, especially power supply noise. Higher value capacitors provide better
robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity
will vary with temperature. For best noise immunity, the designer may use a three capacitor circuit with one dif­ferential capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from
CAP1 to ground, C3 (Figure 1). Larger values are better but 0.1µF is adequate. However, if the designer cannot
use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be iso­lated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

C1=C2=C3= >0.1uF
MultiLayer Ceramic
Surface Mount
NPO (Prefered) or X7R
5V Working Voltage Rating

VSC7217

CAP0

CAP1

C2

C1

C3

The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL
input to REFCLKP but leave REFCLKN open. If LVPECL, connect the inputs to REFCLKP and REF-
CLKN. Internal biasing resistors sets the proper DC Level to VDD/2.

Page 2  VITESSE SEMICONDUCTOR CORPORATION

G52325-0, Rev. 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

Transmitter Functional Description

Transmitter Data Bus

Each VSC7217 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control inputs,
C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special “K-character” is

transmitted, and the WSENn input initiates transmission of a 16-character “Word Sync Sequence” used to align
the receive channels. These data and control inputs are clocked either on the rising edge of REFCLK, on the
rising edge of TBCn, or within the data eye formed by TBCn. When not using REFCLK, each channel uses
either its own TBCn input, or the TBCA input. The transmit interface mode is controlled by TMODE(2:0), as
shown in Table1.

When used, the TBCn inputs must be frequency locked to REFCLK. No phase relationship is assumed. A
small skew buffer is provided to tolerate phase drift between TBCn and REFCLK. This buffer is recentered by
the RESETN input, and the total phase drift after recentering must be limited to ±180° (where 360° is one char­acter time). Each channel has an error output, TBERRn, that is asserted HIGH to indicate that the phase drift
between TBCn and REFCLK has accumulated to the point that the elastic limit of the skew buffer has been
exceeded and a transmit data character has been either dropped or duplicated. This error can not occur when
input timing is referenced to REFCLK. The TBERRn output timing is identical to the low-speed receiver out­puts, as selected by RMODE(1:0) in Table 5.

Table 1: Transmit Interface Input Timing Mode

TMODE(2:0) Input Timing Reference

0 0 0 REFCLK Rising Edge
0 0 1

0 1 0
0 1 1

1 0 0 TBCA Rising Edge
1 0 1 TBCn Rising Edge
1 1 0 TBCA Data Eye
1 1 1 TBCn Data Eye

The following figures show the possible relationships between data and control inputs and the selected
input timing source. Figure2 shows how REFCLK is used as an input timing reference. This mode of opera­tion is used in the VSC7211 and VSC7214. Figure3 and Figure4 show how TBCn is used as an input timing
reference. When TBCn is used to define a data eye (see Figure 4), it functions as an additional data input that
simply toggles every cycle.

Note that the REFCLK and TBCn inputs are not used directly to clock the input data. Instead, an internal
PLL generates edges aligned with the appropriate clock. The arrows on the rising edges of these signals define
the reference edge for the internal phase detection logic. An internal clock is generated at 1/10 the serial trans-

Reserved

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 3

VITESSE

Preliminary Datasheet

VSC7217

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

mit data rate that is locked to the selected input timing source. This is an especially important when DUAL is
HIGH and input timing is referenced to REFCLK, since the falling edge is NOT used. The internal clock active
edges are placed coincident with the REFCLK rising edges and halfway between the REFCLK rising edges in
this mode.

A similar situation exists when TBCn is used to define a data eye. Only the rising edges of TBCn are used
to define the external data timing. The internal clock active edges are placed at 90° and 270° points between
consecutive TBCn rising edges (which are assumed to be 360° apart).

Figure 2: Transmit Timing, TMODE(2:0) = 000

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1)

Tn(7:0)

WSENn

TBCA

or

TBCn

Tn(7:0)

C/Dn

WSENn

Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing

TBCA or TBCn

Tn(7:0)

C/Dn

WSENn

C/Dn

Valid

Figure 3: Transmit Timing, TMODE(2:0) = 10X

Valid

o

0

Valid

Valid Valid

Valid Valid

o

90

Valid Valid

180

o

270

o

360

o

Page 4  VITESSE SEMICONDUCTOR CORPORATION

G52325-0, Rev. 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

8B/10B Encoder

Each channel contains an 8B/10B encoder which translates the 8-bit input data on Tn(7:0) into a 10-bit
encoded data character. C/Dn inputs are also provided in each channel which, along with KCHAR , allow the
transmission of special Fibre Channel Kxx.x characters (see Table2). Note that KCHAR is a static input, and
does NOT have the same input timing as Tn(7:0), C/Dn and WSENn. Normally, C/Dn is LOW in order to
transmit data. If C/Dn is HIGH and KCHAR is LOW, a Fibre Channel defined IDLE Character (K28.5 =
‘0011111010’ or ‘1100000101’ depending on disparity) is transmitted and Tn(7:0) is ignored. If C/Dn is HIGH
and KCHAR is HIGH, a Kxx.x character is transmitted as determined by the data pattern on Tn(7:0). See
Table3. Data patterns other than those defined in Table3 produce undefined 10B encodings.

Table 2: Transmit Data Controls

WSENn C/Dn KCHAR Encoded 10-bit Output

0 0 X Data Character
0 1 0 IDLE Character (K28.5)
0 1 1 Special Kxx.x Character
1 X X 16-Character Word Sync Sequence

Table 3: Special Characters (Selected when C/Dn and KCHAR are HIGH)

Code Tn(7:0) Comment Code Tn(7:0) Comment

K28.0 000 11100 User Defined K28.5- 101 01101 User Defined
K28.1 001 11100 User Defined K28.6 110 11100 User Defined
K28.2 010 11100 User Defined K28.7 111 11100 Test Only
K28.3 011 11100 User Defined K23.7 111 10111 User Defined
K28.4 100 11100 User Defined K27.7 111 11011 User Defined
K28.5 101 11100 IDLE K29.7 111 11101 User Defined

K28.5+ 101 01100 User Defined K30.7 111 11110 User Defined

Encoder Bypass Mode

When ENDEC is LOW, the 8B/10B encoders are bypassed and a 10-bit input character Tn(7:0) is serial­ized directly in each channel, with bit Tn0 transmitted first. The C/Dn input becomes Tn8 and WSENn
becomes Tn9. The KCHAR input becomes ENCDET which is not used in the transmitter but, when HIGH,
enables Comma detection in all four receivers. Refer to the “Decoder Bypass Mode” section for a description of
this mode of operation in the receiver. The latency through the transmitter is reduced by one character time
when ENDEC is LOW. This mode of operation is similar to a 10-bit interface commonly found in serializer/
deserializers for the Fibre Channel (VSC7125) and Gigabit Ethernet (VSC7135) markets.

Word Sync Generation

The VSC7217 can perform channel alignment (also referred to as “word alignment” or “word sync”). In
other words, the four receive data output streams are aligned such that the same 4-byte word presented to the

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 5

VITESSE

Preliminary Datasheet

VSC7217

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

four transmit channel inputs for serialization will be transferred on the receive channel parallel outputs. The
Word Sync Sequence provides a unique synchronization point in the serial data stream that is used to align the
receive channels. This sequence consists of 16 consecutive K28.5 IDLE characters with disparity reversals on
the second and fourth characters. The Word Sync Sequence is sent either as “I+ I+ I- I- I+ I- I+ I- I+ I- I+ I- I+
I- I+ I-” or as “I- I- I+ I+ I- I+ I- I+ I- I+ I- I+ I- I+ I- I+”, depending on the transmitter’s running disparity at the
time the first IDLE character is serialized.

Transmission of the Word Sync Sequence is initiated independently in each channel when the WSENn
input is asserted HIGH for one character time (see Figure5). When WSENn is HIGH, the C/Dn and Tn(7:0)
inputs are ignored. The WSENn, C/Dn and Tn(7:0) inputs are also ignored for the subsequent 15 character
times. In Figure5 below, the Word Sync Sequence is initiated in cycle W1 and transmitted through cycle W16.
Normal data transmission (or the transmission of another Word Sync Sequence) resumes in cycle D3. Figure 5
is drawn assuming that input timing is referenced to REFCLK (e.g., TMODE(2:0)=000) with the DUAL input
LOW. As long as WSENn remains asserted, another Word Sync Sequence will be generated.

Figure 5: Word Sync Sequence Generation

D2D1 W2W1 W4W3 W6W5 W8W7 W10W9 W12W11 W14W13 W16W15 D4D3

REFCLK

WSENn

C/Dn

Tn(7:0)

TXn+/-

The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a
multiplexer which serializes the parallel data using the synthesized transmit clock. The least significant bit of
the 10B data is transmitted first. Each channel has both primary and redundant serial output ports, PTXn and

RTXn, respectively, which consists of differential PECL output buffers operating at either 10 or 20 times the
REFCLK rate. The primary and redundant transmitter outputs are controllable separately on each channel. The

primary PECL outputs (PTXn) are enabled when the PTXENn input is HIGH, and the redundant PECL outputs
(RTXn) are enabled when the RTXENn input is HIGH. When a PECL output is disabled, the associated output
buffers do not consume power and the attached pins are undriven.

0x020x01 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0x040x03

D2.0+D1.0+ K28.5+K28.5+ K28.5-K28.5- K28.5-K28.5+ K28.5-K28.5+ K28.5-K28.5+ K28.5-K28.5+ K28.5-K28.5+ K28.5-K28.5+ D4.0-D3.0+

Serializer

Receiver Functional Description

Serial Data Source

Each receive channel has both primary (PTXn) and redundant (RRXn) serial input ports, which consists of
differential PECL input buffers. Each channel also has a control input, RXP/Rn, used to select either the pri-

Page 6  VITESSE SEMICONDUCTOR CORPORATION

G52325-0, Rev. 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

mary or redundant serial input as the data source for that channel. When RXP/RC is HIGH, the C channel serial
data source is PRXC. When LBENn(1:0)=10, the channel’s transmitter is looped back and becomes the serial
data source regardless of the state of RXP/Rn (see Table4).

Table 4: Serial Data Source Selection

LBENn(1:0) RXP/Rn Serial Data Source

≠ 1 0 0 RRXn
≠ 1 0 1 PRXn

= 1 0 X

Signal Detection

Each channel’s primary and redundant PECL input buffers have an associated signal detect output,
PSDETn and RSDETn. All eight outputs are available for continuous monitoring of both the selected and non­selected input. Each signal detect output is asserted HIGH when transitions are detected on the associated PECL
input and the signal amplitude exceeds 200 mV. A LOW indicates that either no transitions are detected or the
signal amplitude is below 100mV. The signal detect outputs are considered undefined when the signal ampli­tude is in the 100mV to 200 mV range. The signal detect circuitry behaves like a re-triggerable one shot that is
triggered by signal transitions, and whose time-out interval ranges from 40 to 80 bit times. The transition den­sity is not checked to ensure that it corresponds to a valid Fibre Channel data stream. The PSDETn and
RSDETn output timing is identical to the low-speed receiver outputs, as selected by RMODE(1:0) in Table5.

Loopback fromTransmitters

LBTXn

Receiver Equalization

Incoming data on the PRX/RRX inputs typically contains a substantial amount of Inter Symbol Interfer­ence (ISI) or deterministic jitter which reduces the ability of the receiver to recover data without errors. An
equalizer has been added to each of the receiver’s input buffers in order to compensate for this deterministic jit­ter. This circuit has been designed to effectively reduce the ISI commonly found in copper cables or backplane
traces due to low frequencies traveling faster than high frequencies as a result of the skin effect. The equalizer
boosts high-frequency edge response in order to reduce the adverse effects of ISI.

Clock and Data Recovery

At the receiver, each channel contains an independent Clock Recovery Unit (CRU) that accepts the selected
serial input source, extracts the high-speed clock and retimes the data. Each CRU automatically locks on data
and if the data is not present, will automatically lock to the REFCLK. This maintains a very well-behaved
recovered clock (RCLKn/RCLKNn) which does not contain any slivers and will operate at a frequency of the
REFCLK reference ±200 ppm. The use of an external Lock-to-Reference pin is not needed.

The Clock Recovery Unit must perform bit synchronization which occurs when the CRU locks onto and
properly samples the incoming serial data as described in the previous paragraph. When the CRU is not locked
onto the serial data, the 10-bit data out of the decoder is invalid which results in numerous 8B/10B decoding
errors or disparity errors. When the link is disturbed (the cable is disconnected or the serial data source is
switched), the CRU will require a certain amount of time to lock onto data which is specified in the AC timing
specifications for “Data Acquisition Lock Time.”

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 7

VITESSE

Preliminary Datasheet

VSC7217

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

Deserializer and Character Alignment

The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit
“Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the
10-bit character boundary. Note that this pattern is found in three special characters: K28.1, K28.5 and K28.7.
However, K28.5 is chosen as the unique IDLE character. Only K28.1 and K28.5 should be used in normal oper­ation. The K28.7 character should be reserved for test and characterization use.

Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a
“Comma” pattern in the incoming serial data stream. If the receiver identifies a “Comma” pattern in the incom­ing data stream, which is misaligned to the current framing boundary, the receiver will re-synchronize the
recovered data in order to align the data to the new “Comma” pattern. Re-synchronization ensures that the
“Comma” character is output on the internal 10-bit bus so that bits 0 through 9 equal ‘0011111xxx’ or
‘1100000xxx’. If the “Comma” pattern is aligned with the current framing boundary, re-synchronization will
not change the current alignment. Re-synchronization is always enabled and cannot be turned off when
ENDEC is HIGH. After character re-synchronization the VSC7217 ensures that within a link, the 8-bit data
sent to the transmitting VSC7217 will be recovered by the receiving VSC7217 in the same bit locations as the
transmitter (e.g., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled
only if KCHAR is HIGH.

10B/8B Decoder

The 10-bit character from the deserializer is decoded in the 10B/8B decoder, which outputs the 8B data
byte and three bits of status information. If the 10-bit character does not match any valid value, an Out-of-Band
Error is generated which is output on the receiver status bus. Similarly, if the running disparity of the character
does not match the expected value, a Disparity Error is generated. The decoder also reports when a K-character
is received, and distinguishes the K28.5 (IDLE) character from other K-characters. This status information is
combined with LOS State Machine status and FIFO error status, to produce the prioritized per-character link
status output information (see Table7).

Elastic Buffer and Channel Deskewing

An elastic buffer is included in each of the four receive channels. Decoded data and status information is
written into these buffers on each channel’s recovered clock, and is read on the selected output clock. In addi­tion to allowing decoded data to easily cross from a channel’s recovered clock domain to its output clock
domain, the elastic buffers facilitate channel alignment (the reconstruction of a multi-byte word as presented to
the transmitting devices). In addition, the buffers facilitate rate matching via IDLE character insertion/deletion
when the channel’s recovered clock is not frequency locked to its output clock.

There are three conditions under which a receive channel’s elastic buffer is recentered: (1) the RESETN
input, when asserted, recenters the read/write pointers in each elasticity buffer, (2) whenever a Comma charac­ter is received which changes the receive character’s framing boundary, and (3) whenever the receiver detects
the synchronization point in the Word Sync Sequence. All three of these events are associated with chip initial­ization or link initialization and will not occur during normal data transfer. Note: recentering can result in the
loss or duplication of decoded character data and status information.

When a condition change transmit timing (phase shifts in TBC) or shifts phase/alignment into the receiver,
the user should initial a Word Sync Event to recenter all elasticity buffers. Otherwise, data corruption could
occur.

Page 8  VITESSE SEMICONDUCTOR CORPORATION

G52325-0, Rev. 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

The VSC7217 presents recovered data on Rn(7:0) and status on IDLEn, KCHn and ERRn. These outputs
are timed either to each channel’s own recovered clock (RCLKn/RCLKNn), to Channel A’s recovered clock
(RCLKA/RCLKNA), or to REFCLK. The output timing reference is selected by RMODE(1:0) (see Table5).
The transmitter input skew buffer error outputs TBERRn and the analog signal detect outputs PSDETn and
RSDETn are also synchronized to the selected output timing reference. There are two choices for REFCLK­based timing, which differ in the positioning of the data valid window associated with the output signals timed
to REFCLK. When RMODE(1:0)=00, REFCLK is approximately centered in the output data valid window
as in the VSC7214. When RMODE(1:0)=01, REFCLK slightly leads the data valid window so that output
data appears to have a more typical “Clock-to-Q” timing relationship to REFCLK.

Table 5: Receive Interface Output Timing Mode

RMODE(1:0) Output Timing Reference

0 0 REFCLK (Centered)

0 1 REFCLK (Leading)
1 0 RCLKA/RCLKNA
1 1 RCLKn/RCLKNn

The term “word clock” is used for whichever clock (REFCLK, RCLKA/RCLKNA or RCLKn/

RCLKNn) is selected as the output timing reference. If RMODE(1) is HIGH, each channels’ RCLKn/
RCLKNn outputs are complementary outputs at 1/10th or 1/20th the baud rate of the incoming data depending
upon DUAL. When RCLKA/RCLKNA is selected as the output timing reference, Channel B, C and D
RCLKn/RCLKNn outputs are copies of RCLKA/RCLKNA. If RMODE(1) is LOW, each channels’
RCLKn/RCLKNn outputs are held in a LOW/HIGH state, respectively, and the data and status outputs are

timed to REFCLK. If DUAL is HIGH, all data at the four output ports are synchronously clocked out on both
positive and negative edges of the selected word clock at 1/20th the baud rate. If DUAL is LOW, the data is
clocked out of the VSC7217 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing
waveforms for the output data and status are shown in Figure6, Figure7 and Figure8.

Figure 6: Receive Timing, RMODE(1:0) = 00

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1)

Rn(7:0)

IDLEn

KCHn

ERRn

Valid

Valid Valid

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 9

Preliminary Datasheet

VSC7217

Mutli-Gigabit Interconnect Chip

Figure 7: Receive Timing, RMODE(1:0) = 01

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1)

Rn(7:0)

IDLEn
KCHn

ERRn

Figure 8: Receive Timing, RMODE(1:0) = 1X

RCLKn

(DUAL = 0)

VITESSE

SEMICONDUCTOR CORPORATION

Valid

Valid Valid

RCLKn

(DUAL = 1)

Rn(7:0)

IDLEn
KCHn

ERRn

The data coming from the decoder is clocked into the elastic buffer by the recovered clock from the chan-

nel’s CRU. The data is clocked out of the elastic buffers with word clock. If the transmitting device’s REFCLK
is not precisely frequency locked to a receive channel’s word clock, then the channel’s elastic buffer will tend to
gradually fill or empty as the recovered clock (which is by definition frequency locked to the transmitter’s
REFCLK) steadily drifts in phase relative to the word clock.

To accommodate frequency differences between a transmitter’s REFCLK and the word clock, the

VSC7217 can automatically perform rate matching by either deleting or duplicating IDLE characters. The
FLOCK input must be LOW to enable rate matching which, based on how the WSI input is connected, can
either be performed in each channel individually or can be performed in parallel across a group of channels that
are word-aligned. This is discussed in detail in the following section describing Word Alignment. The user
must ensure that the frequency at which IDLEs are simultaneously transmitted on each channel accommodates
the frequency differences, if any, in their system architecture. Not meeting the IDLE density requirements could
result in Underrun/Overrun Errors.

Valid

Valid Valid

Page 10  VITESSE SEMICONDUCTOR CORPORATION

G52325-0, Rev. 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

∆φ2π

Preliminary Datasheet

Multi-Gigabit Interconnect Chip

The elastic buffer is designed to allow a maximum phase drift of +2 or -2 serial clock bit times between re-

synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This maxi­mum packet length depends on the frequency difference between the transmitting and receiving devices REF-
CLKs. Let represent phase drift in bit times, and let represent one full 10-bit character of phase drift.
Limiting phase drift to two bit times means the following inequality must be satisfied:

(1)
Let L be the number of 10-bit characters transmitted, and let ∆f be the frequency offset in ppm. The total

phase drift in bit times is given by:

(2)
A simple expression for maximum packet length as a function of frequency offset is derived by substituting

Equation (2) in Equation (1) and solving for L:

(3)

As an example, if the frequency offset is 200 ppm, the maximum packet length should not be more than 1K

bytes. To increase the maximum packet length L, decrease the frequency offset ∆f. Please note that if only on
K28.5 is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the
user must have at least one K28.5 between these two packets, then two K28.5s must be transmitted.

Word Alignment

The VSC7217 performs channel-to-channel word alignment. In this mode of operation, if the data from all

four channels on the transmitting VSC7217 (the 4 Tn(7:0) busses) is viewed as a 32-bit word, then the receiv­ing VSC7217 will recover an identical word. For example, if a transmit pattern was ‘ABCD’, ‘EFGH’, ‘IJKL’,
etc., the receiver should not recover data words as ‘ABGD’, ‘EFKH’, ‘IJOL’, etc. This requires the four trans­mit channels to obtain input data on a common clock (TMODE(2:0)=000 or 1X0) and the four receive channels
to present output data on a common word clock (RMODE(1:0)=0X or 10).

There are elastic buffers within the receiver used to deskew the four channels and align them to a common
word clock. An elastic buffer allows the channels’ input to be skewed up to ±6 bit times (12 bit times total skew
between any two channels) to accommodate circuit imperfections, differences in transmission delay and jitter.
Multiple VSC7217 devices can also be used in synchronous operation if the skew between all serial input pairs
is maintained less than ±6 serial clock bit times. This allows easy implementation of robust systems and is dis­cussed in greater detail in the Using Multiple VSC7217s in Parallel section.

In order to perform word alignment, a synchronization point must be seen across all aligned receive chan­nels within the ±6 bit time window. The VSC7217 receiver recognizes the first four characters of the Word
Sync Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the synchronization
point. As a model for understanding, consider the case where a VSC7217 transmitter sends 32 bits of data to the
receiver via copper media, which has small cable length differences, causing a channel-to-channel skew. All
transmit channels that are to be word-aligned transmit the Word Sync Sequence in parallel. On detection of the
synchronization point, the receivers will reposition the recovered data within their elastic buffers in order to
align all four channels and remove any channel-to-channel skew. All normal data characters following the

∆φ 0.22π×()≤

∆φ∆f 106⁄()2π× L=

L 0.210

×()∆f⁄≤

6

G52325-0, Rev. 3.0

6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

 VITESSE SEMICONDUCTOR CORPORATION Page 11