VITESSE VSC7139TW Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Gigabit Ethernet and Fibre Channel

Quad Transceiver for

Features

• Four Complete Transmitter/ Receiver Functions in a Single Integrated Circuit

• Full Fibre Channel (T11) and Gigabit Ethernet (IEEE 802.3z) Compliance

• 1.05Gb/s to 1.36Gb/s Operation per Channel

• Common or Per-Channel Transmit Byte Clocks

• TTL or PECL Reference Clock Input

• 1/10

or 1/20th Baud Rate Recovered Clocks

• Common and Per-Channel, Serial and Parallel Loopback Controls

• Common Comma Detect Enable Inputs

• Per-Channel Comma Detect Outputs

• Cable Equalization in Receivers

• Automatic Lock-to-Reference

• 3.3V Power Supply, 2.67 W Max Power Dissipation

• 208-Pin, 23mm BGA Packaging

General Description

The VSC7139 is a full-spee d Quad Fibre Channel and G igabit Ethernet Transceive r IC. Each of the fou r transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters and serializes the data onto high speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be synchronous to the reference cloc k, a comm on transmit byte clock or a per-channel transmit byte clock. Each receiver samples serial rece ive data, recovers t he clock and data, deserial izes it into 10-bit receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7139 contains on-chip (PLL) circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.

VSC7139 Block Diagram (1 of 4 Channels)

Rx(0:9)

RCM RCx1 RCx0

SYNCx

ENCDET

PLUP SLPN

LPNx

Tx(0:9)

TBCx REFT

REF+

REF-

RFCM

LTCN

Loopback

Q D

Comma

Detect

Control

Clock

Multiply

x10/x20

Serial to

Parallel

SEL

÷10/

÷20

Unit

÷10

Recovery

Parallel

to Serial

Q D

Clock

D QD Q

Rx+ Rx-

Tx+ Tx-

RFCO0 RFCO1

G52196-0, Rev 3.3 Page 1 5/14/01

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VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for Gigabit Ethe rnet and Fibre Channel

Preliminary Datasheet

VSC7139

Functional Description

Notation

In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a sig-

nal on any specific chann el, the si gnal will have t he Channel l etter embedd ed in the name, i .e., “TA(0:9).” When referring to the comm on behavi or of a sign al which is used on e ach of the fo ur channe ls, a lower c ase “x” is used in the signal name, i.e. Tx(0:9). Differential signals, i.e. RA+ and RA-, may be referred to as a single signal, i.e. RA, by dropping reference to the “+” and “-”. “REF” refers to either the TTL input REFT, or the PECL differential inputs REF+/REF-, whichever is used.

Clock Synthesizer

The VSC7139 clock synthesizer multiplies the reference frequency provided on the REF input by 10 or 20 to achieve a baud rate clock between 1.05GHz and 1.36GHz. The REF input can be either TTL or PECL. If TTL, connect the TTL input clock to REFT. If PECL, connect the PECL inputs to REF+ and REF-. The internal clock presented to the Clock Synthesizer is a logical XNOR of REFT and REF+/-. The reference clock will be active HIGH if the unused input is HIGH. The referen ce clock is activ e LOW if th e unused in put is L OW. REFT has an internal pull-up resistor. Internal biasing resistors set the proper DC level on REF+ /- so AC-coupling may be used.

The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency locked to the REF input. This clock is derived from the cloc k synthesizer and is always 1/10 t he baud rat e, regar dless of the st ate of t he RFCM input.

The on-chip PLL uses a single external 0.1µ F capac itor, connected between CAP0 and CAP1, to cont rol the Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These capacitors are used to minimize the impact of common mode noise on the Clock Multiplier Unit (CMU), especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor between CAP0 and CAP 1, C1, a capa citor from CAP0 to ground, C2, an d a capacitor f rom CAP1 to groun d, C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

CAP0

VSC7139

CAP1

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C1=C2=C3= >0.1µF MultiLayer Ceramic Surface Mount NPO (Preferred) or X7R 5V Working Voltage Rating

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VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Serializer

The VSC7139 accepts TTL input data as a parallel 10 bit character on the Tx(0:9) bus which is latched into the input register on the rising edge of either REF or TBCx. Three clocking modes are available and automatically detected by the VSC7139. If TBCC is static and RFCM is HIGH, then all four Tx(0:9) busses are latched on the rising edges of REF. If TBCC is static and RFCM is LOW, then REF is multiplied by 20 and the input busses are latched on t he risi ng edge s of R EF an d at the midpoint between rising edges. If T B CC i s t ogg li ng but TBCB is static, then all four Tx(0:9) busses are latched on the rising edges of TBCC. If TBCB and TBCC are both toggling then the rising edge of each TBCx latches the corresponding Tx(0:9) bus.

The active TBCC or TBCx inputs must be frequency-locked to REF. There is no specified phase relationship. Prior to normal data transmission, LTCN must be asserted LOW so that the VSC 7139 can lock to TBCx which may result in corrupted data being transmitted. Once LTCN has been raised HIGH, the transmitters remain locked to REF and can tolerate +

The 10-bit parallel transmission character will be serialized and transmitted on the Tx PECL differential outputs at the baud rate with bit Tx0 (bit a) transmitted first. User data should be encoded using 8B/10B or an equivalent code. The mapping to 10B encoded bit nomenclature and transmission order is shown in Table 1, along with the recognized comma pattern.

Table 1: Transmission Order and Mapping of a 10B Character

2 bit times of drift in TBCx relative to REF.

Gigabit Ethernet and Fibre Channel

Quad Transceiver for

Data Bit

10B Bit Position j h g f i e d c b a

Comma Character x x x 1 1 1 1 1 0 0

Clock Recovery

The VSC7139 accepts differential high speed serial input from the selected source (either the PECL Rx+/ Rx- pins or the internal Tx+ /- data), extrac ts the clock and retim es the data. Equali zers are inclu ded in the receiver to open the data eye and compensate for InterSymb ol Interference (ISI) which may be p resent in the incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no external components. Fo r prop er oper ation, the baud rate of the data stream to be r ecovered should be within +

200 ppm of ten times the REF frequency. For example, Gigabit Ethernet systems would use 125MHz oscilla-

tors with a +

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7139 provides complementary TTL recovered clocks, RCx0 and RCx1, which are at one-twentieth of the serial baud rate (if RCM=LOW) or one-tenth (if RCM=HIGH). The clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data. The serial data is retimed, deserialized and output on Rx(0:9).

If serial input data is not present, or does n ot meet the req uired baud rate , the VSC7139 will c ontinue to produce a recovered clock so that downstream logic may continue to function. The RCx0/RCx1 output frequency under these circumstances will differ from its expected frequency by no more than +

100ppm accuracy resulting in +200 ppm between VSC7139 pairs.

Tx9 Tx8 Tx7 Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0

1%.

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VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for Gigabit Ethe rnet and Fibre Channel

Word Alignment

The VSC7139 provides 7-bit comma character recognition and data word al ig nment . Word synchr oni zat ion is enabled on all channels by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/ 10B coded data character or pair of adjacent characters. It oc curs only within spec ial characters, known as K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is defined as any of the following conditions:

1. The comma is not aligned within the 10-bit transmission character such that Rx(0...6) = “0011111”.

2. The comma straddles the boundary between two 10-bit transmission characters.

3. The comma is properly aligned but occurs in the received character presented during the rising edge of

RCx0 rather than RCx1.

When ENCDET is HIGH and an improperly-aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to Rx(0:9). This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly-aligned comma pattern, data which would have been presented on the parallel output port prior to the comma character, and possibly the comma character itself, may be lost. Possible loss of the comma character is data dependent, according to the relative change in alignment. Data subsequent to the comma character will always be output correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.

On encountering a comma character, SYNCx is driven HIGH. The SYNCx pulse is presented simultaneously with the comma character and has a duration equal to the data. The SYNCx signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCx1. Functional waveforms for synchronization are given in Figure 2. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change in the output data alignment is required. Not e t hat up to th ree charact ers pri or to the comma character may be corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no phase adjustment is necessary. Figure 2 illustrates the positio n of the SYNCx p ulse in relation to the comma character on Rx(0:9).

Preliminary Datasheet

VSC7139

Figure 2: Misaligned and Aligned K28.5 Characters

RCx0

(RCM LOW)

RCx1

RCx0

(RCM HIGH)

RCx1

SYNCx

Rx(0:9)

Page 4 G52196-0, Rev 3.3

Corrupt Corrupt Corrupt K28.5 Data1 Data2 Data3 K28.5Data

Misaligned Comma: Stretched

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Aligned Comma

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SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Loopback Operation

Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNx inputs as shown in Table 2. LPNx enables PLUP/SLPN on a per-channel basis when LOW. If LPNx is HIGH, PLUP/SLPN have no imp act on Cha nnel x. W hen SLPN and PLUP are bot h HIGH the tra nsmitter outp ut is held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the i nput jitter is removed. However, the TXx outputs may not meet jitter spe cifications listed in the “Transmitter AC Specifications” due to low frequency jitter transfer from RXx to TXx.

Table 2: Loopback Selection

LPNx PLUP SLPN Tranmitter Source Receiver Source

LOW LOW LOW Receiver Receiver LOW LOW HIGH Transmitter Receiver LOW HIGH LOW Transmitter Transmitter LOW HIGH HIGH HIGH Transmitter

HIGH X X Transmitter Receiver

Gigabit Ethernet and Fibre Channel

Quad Transceiver for

JT AG Access Port

A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is available in “VSC7139 JTAG Access Port Functionality.”

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VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for Gigabit Ethe rnet and Fibre Channel

AC Characteristics

Figure 3: Transmit Timing Waveforms

REF

TBCx

Tx(0:9)

10 Bit Data

+/-Tx

REF TBCx

Data Valid

RLAT

TLAT

Preliminary Datasheet

VSC7139

Data Valid

Tx0 Tx1 Tx2

Table 3: Transmitter AC Characteristics

Paramete r

SDR,TSDF

RLAT

TLAT

Transmitter Output Jitt er

RJ Random jitter (RMS) — 58ps

Tx(0:9) Setup time to the rising edge of TBCx or REF

Tx(0:9) hold time after the rising edge of TBCx or REF

Tx+/Tx- rise and fall time ——300 ps Latency from rising edge of REF

to Tx0 appearing on TX+/TXLatency from ri si ng ed ge of T BC x

to Tx0 appearing on TX+/TX-

Serial data output deterministic jitter (pk-pk)

Description Min Typ Max Units Conditions

1.5 ——ns

1.0 ——ns

7bc +

0.66ns 5bc +

0.66ns

— 35 80 ps

—

7bc +

1.46ns 11bc +

1.46ns

Measured between the valid data level of Tx(0:9) to the 1. 4V p oin t of TBCx or REF

20% to 80%, 75Ω load to V tested on a sample basis

bc = Bit clocks ns = nanoseconds

Measured at SO+/-, 1 sigma deviation of 50% crossing pointt

IEEE 802.3Z Claus e 38.68, tested on a sample basis

/2,

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