VITESSE VSC7126QX Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

SC7126

1.0625 Gbits/sec Fibre
Channel Transceiver

Features

• ANSI X3T11 Fibre Channel Compatible 1.0625
Gbps Full-duplex Transce ive r

• GLM Compatible (FCSI-301-Rev 1.0)

• 20 Bit TTL Interface For Transmit And Recei ve Data

• Monolithic Clock Synthesis And Clock Recovery ­No External Components

• 53.125 MHz TTL Reference Clock

• Automatic Lock-to-Reference Function

• Suitable For Both Copper And Fiber
Optical Link Applications

• Low Power Operation - 850 mW

• 80 Pin, 14x14 mm PQFP

• Single +3.3V Power Supply

General Description

The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space- con­strained applications. It accepts two 10-bit 8B/10B encoded transmit characters, latches them on the rising edge
of TBC and serializes the data onto the TX+/- PE CL dif ferenti al output s at a baud rate which is twent y times the
TBC frequency. It also samples serial re ceive data o n the RX+/- PE CL differen tial inputs, re covers the clo ck
and data, deserializes it onto two 10-bit receive characters, outpu ts a recovered clocks at one twe ntieth of the

incoming baud rate and detects Fibre Channel “Comma” characters. The VSC7126 contains on-chip PLL cir­cuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream.
These circuits are fully monolithic and require no external components.

VSC7126 Block Diagram

EWRAP

20

R0:19

RBC(0)
RBC(1)

L_UNUSE

COM_DET

EN_CDET

T0:19

TBC

TXEN#

Q D

53.125 MHz

Frame

Logic

20

D Q

53.125 MHz

PLL Clock

Multiply (x20)

Serial to

Parallel

÷ 20

Comma

Detect

Parallel

to Serial

Retimed

Data

Recovered

Clock

Q D

Clock

Recovery

Serial Data

Synthesized

Clock

D Q

2:1

RX+
RX-

TX+
TX-



G52148-0, Rev. 4.3

3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

.0625 Gbits/sec Fibre

hannel Transceiver

Datasheet

VSC7126

Functional Description

Clock Synthesizer:

The VSC7126 clock synthesizer multiplies the 53.125 MHz reference frequency provided on the TBC pin
by 20 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic
PLL which does not require any external components.

Serializer:

The VSC7126 accepts TTL input data as tw o parallel 10 bit c haracters o n the T0:19 bus which is latched
into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL dif­ferential outputs at a baud rate of twenty times the frequency of the TBC inp ut, with bit T0 transmitted first.
User data should be encoded for tr ansmissi on usin g the 8B/ 10B block code descr ibed in th e Fibre C hannel spec­ification, or an equivalent, edge rich, DC-balanced code. If either EWRAP or TXEN# is HIGH the transmitter
will be disabled with TX+ HIGH and TX- LOW. If both EWRAP and TXEN# are LOW, the transmitter outputs
serialized data.

Transmission Character Interface

In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20 bit inter­face on the VSC712 6 corresponds to two transmission characters. This mapping is illustrated in Figure 1.

Figure 1: Transmission Order and Mapping to Fibre Channel Character

Parallel Data Bits 191817161514131211100908070605040302010

8B/10B Bit Position
Valid Comma Position

Last Data Bit Transmitted

Clock Recovery:

The VSC7126 accepts differential high speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW),
extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and lim­ited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7126 clock recovery
circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of
the data stream to be recovered should be within 200 ppm of twenty times the TBC frequency. This allows
oscillators on either end of the link to be 53.125 MHz +/- 100ppm.

Deserializer:

The retimed serial bit stream is converted into two 10-bit parallel output charact ers. The VSC7126 provides
a TTL recovered clock, RBC(0) and its complement RBC(1), at one-twentieth of the serial baud rate. The
clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial
data is retimed by the internal high-speed clock, and deserialized. The resulting parallel data will be captured

j hgfi edcbaj hgf i edcba

1111100

First Data Bit Transmitted

0

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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52148-0, Rev. 4.3

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

SC7126

by the adjoining protocol logic on the falling edge of RBC(0). In order to maximize the setup and hold times
available at this inte rface, the paral lel data is loaded into the outp ut register at a po int nomina lly midway
between the falling edges of RBC(0).

If serial input data is not pres ent, or does no t meet the requ ired baud rate, th e VS C7126 will continue to
produce a recovered clock so that downstream logic ma y continue to function. In the absence of a signa l, the
RBC(0)/RBC(1) output clocks will immediately lock to the TBC reference clock.

Word Alignment:

The VSC7126 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word
synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7126

constantly examines the se rial data for the p resence of the Fibre Channel “c omma” char acter. This pattern is
“0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not con­tained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special
characters, known as K28.1, K28.5 and K28.7, which are define d specifically for synchro nization in Fibre
Channel systems. Improper alignment of the comma character is defined as any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = “0011111”

2) The comma straddles the boundary between two 10-bit transmission characters.

When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in
such a manner that the comma character is aligned properly in R0:6 as shown in Figure 1. This resul ts in proper
character and word alignment. When the parallel data alignment changes in response to an improperly aligned
comma pattern, some data which would have been presented on the parallel output port may be lost. However,
the synchronization chara cter and subsequent data will b e output correctly and pro perly aligned. When
EN_CDET is LOW, the current alignment of the ser ial dat a is maint ained indef initel y, regardless of data pattern.

On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the
parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma char­acter and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the
adjoining protocol logic on the falling edge of RBC(0). Functional waveforms for synchronization are given in
Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is
necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:6.
Figure 3 shows the case where the K28.5 is det ect ed, b ut it i s o ut of phase and a change in the ou tp ut dat a al i gn­ment is required. Note that up to three characters prior to the comma character may be corrupted by the realign­ment process.

1.0625 Gbits/sec Fibre
Channel Transceiver

Signal Detection:

An output, LUNUSE, is provided to signal when the link is open or down. This signal is asserted if R0:19

are all either LOW or HIGH and EWRAP is LOW.



G52148-0, Rev. 4.3

3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

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VITESSE

SEMICONDUCTOR CORPORATION

.0625 Gbits/sec Fibre

hannel Transceiver

Figure 2: Detection of a Properly Aligned Comma Character

RBC(0)

COM_DET

R0:9

R10:19

Datasheet

VSC7126

K28.5 TChar TChar TChar

TChar TChar TChar TChar

TChar: 10 bit Transmission Character

Figure 3: Detection and Resynchronization of an Improperly Aligned Comma

Receiving Two Consecutive K28.5+TChar Transmission Words

RBC(0)

COM_DET

R0:9

R10:19

PC

PC = Potentially Corrupted

K28.5 TChar TChar TChar K28.5 TChar

PCPC

TChar TChar TChar TChar TChar TChar

Page 4 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52148-0, Rev. 4.3

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

SC7126

AC Characteristics

TBC

T0:19

20 Bit Data

Data Valid

Figure 4: Transmit Timing Waveforms

T

1

Data Valid

T

2

1.0625 Gbits/sec Fibre
Channel Transceiver

Data Valid

Table 1: Transmit AC Characteristics

Parameters Description Min Max Units Conditions

T

T

T

SDR,TSDF

T

LAT

1

2

T0:19 Setup time to the
rising edge of TBC

T0:19 hold time after the
rising edge of TBC

TX+/TX- rise and fall time — 300 ps.
Latency from rising edge

of TBC to T0 appearing on
TX+/TX-

1.5 —ns.

2.5 — ns.

20 bc - 4 ns ns. bc = Bit Clock Period s

Measured between the valid data level of
T0:19 to the 1.4V point of TBC

20% to 80%, 75 Ohm load to Vdd-2V
Tested on a sample basis

Transmitter Output Jitter Allocation

T

RJ

T

DJ

Serial data output random
jitter (RMS)

Serial data output
deterministic jitter (p-p)

—20ps.

— 120 ps.

RMS, tested on a sample ba s i s
(refer to Figure 8)

Peak to peak, tested on a sample basis
(refer to Figure 8)



G52148-0, Rev. 4.3

3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

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