VITESSE VSC7123RD, VSC7123QN, VSC7123QU Datasheet

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7123

10-Bit Transceiver for Fibre

Channel and Gigabit Eth er net

Features

• 802.3z Gigabit Ethernet-Compliant

1.25 Gb/s Transceiver

• ANSI X3T11 Fibre Channel-Compliant

1.0625 Gb/s Transceiver

• 0.98 to 1.36 Gb/s Full-Duplex Operation

• 10-Bit TTL Interface for Transmit and
Receive Data

• Automatic Lock-to-Reference

• RX Cable Equalization

• Analog/Digital Signal Detection

• JTAG Access Port for Testability

• Single +3.3V Supply, 650mW Typical

• Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP

General Description

The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.

VSC7123 Block Diagram

R(0:9)

RCLK

RCLKN

COMDET

ENCDET

EWRAP
SIGDET

T(0:9)

REFCLK

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10

10

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Q D

Comma

Detect

x10 Clock

Multiply

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Serial to

QD

Parallel

÷10
÷20

Parallel

to Serial

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Q D

Clock

Recovery

2:1

Signal
Detect

D QD Q

NOT SHOWN: JTAG Boundary Scan

RX+
RX-

TX+
TX-

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VITESSE

SEMICONDUCTOR CORPORATION

10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet

Data Sheet

VSC7123

Functional Description

Clock Synthesizer

The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase Lock Loop (PLL) uses a single
external 0.1

Serializer

The VSC7123 accepts TTL input data as a parallel 10-bit character on the T(0:9) bus, which is latched into
the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL
differential outputs at a bau d rate that is 10 ti mes the frequenc y of the REFCLK , with bit T0 tra nsmitted first.
User data should be encoded using 8B/10B block code or equivalent.

Transmission Character Interface

An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7123 corresponds to a transmission character. This mapping is illustrated in Figure 1.

µF capacitor to control the Loop Filter.

Figure 1: Transmission Order and Mapping of an 8B/10B Character

Parallel Data Bits

8B/10B Bit Position

Comma Character

Last Data Bit Transmitted

Clock Recovery

The VSC7123 accepts differential high-speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference which may be present in the incoming data. The serial bit stream should be encoded to provide DC
balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit is completely
monolithic an d requires no ex ternal componen ts. For proper ope ration, the baud ra te of the data stream to be
recovered should be within +
systems would use 125MHz oscillators with a +
pairs.

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7123 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are 1/20
are generated by dividing down the high-speed recovered clock, which is phase-locked to the serial data. The

200 ppm of 10 times the REFCLK frequency. For example, Gigabit Ethernet

T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

j

hgf iedcba

XXX1111100

First Data Bit Transmitted

100ppm accuracy resulting in +200 ppm between VSC7123

th

of the serial baud rate. The clocks

Page 2 G52212-0, Rev 4.3

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Data Sheet

VSC7123

serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining
protocol logic on the rising edges of RCLK and RCLKN.

If serial input data is not present or does not meet the required baud rate, the VSC7123 will continue to
produce a recovered clock, allowing downstream logic functionality to continue. Under these circumstances,
the RCLK/RCLKN output frequency differ from its expected frequency by no more than +

Word Alignment

The VSC7123 provides 7-bit comma character recognition and data word al ig nment . Word synchr oni zat ion
is enabled by asserting ENCDET HIGH. When synchronization is enabled, t he recei ve r exami nes the recov ered
serial data for the presence of the “Comma” character. This pattern is “0011111XXX”, where the leading zero

corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data
character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and
K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined
as any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that R0...R6 = “0011111.”

2) The comma straddles the boundary between two 10-bit transmission characters.

3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.

When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is
stretched (never slivered) so that the comma character and recovered clocks are properly aligned to R(0:9). This
results in proper character and word alignment. When the parallel data alignment changes in response to a
improperly aligned comma p a tter n, some data which would have been present ed o n t he par al le l output port may
be lost. Additionally, the first Comma pattern may also be lost or corrupted. Subsequent data will be output
correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained
indefinitely, regardless of data pattern.

When encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented
simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The
COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of
RCLKN. Functional waveforms for syn chr oni zati on are given in Figure 2 and F ig ure 3 . Fig ure 2 shows the case
when a comma character is detected and no phase adjustment is necessary. Figure 2 illustrates the position of
the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is
detected, but it is misaligned so a change in the output data alignment is required. Note that up to three
characters prior to the comma character may be corrupted by the realignment process.

10-Bit Transceiver for Fibre

Channel and Gigabit Eth er net

1%.

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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

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Internet: www.vitesse.com

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VITESSE

SEMICONDUCTOR CORPORATION

10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet

Figure 2: Detection of a Properly Aligned Comma Character

RCLK

RCLKN

COMDET

R(0:9)

Data Sheet

VSC7123

K28.5 TChar TChar TChar

TChar: 10-bit transmission character

Figure 3: Detection

RCLK

RCLKN

COMDET

R(0:9)

Receiving Two Consecutive K28.5+TChar Transmission Words

Clock Stretching

K28.5 TChar T Char TChar K28.5 TChar

Potentially Corrupted

TChar: 10-bit transmission character

Page 4 G52212-0, Rev 4.3

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Data Sheet

VSC7123

Signal Detection

The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre
Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determi ne
if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period,
all the four criteria are met, SIGDET will be HIGH during th e next 4 RCLK perio d. If during t he current per iod,
any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.

1) Analog transition detection is performed on the input to verify that the signal swings are of adequate

amplitude. The RX+/- input buffer contains a differential voltage comparator which will go HIGH if the

differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is

between 200mV and 400mV, the output is indeterminate.

2) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current

RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.

3) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current

RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.

4) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which

a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data

will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the

monitoring period, SIGDET will go LOW during the next period.

The behavior of SIGDET is affected by EWRAP and ENCDET as shown in Table 1.

10-Bit Transceiver for Fibre

Channel and Gigabit Eth er net

Table 1: Signal Detect Behavio r

EWRAP ENCDET COMDET

0 0 Disabled Enabled Enabled Enabled Normal
0 1 Enabled Enabled Enabled Disabled SIGDET ignores commas
1 0 Disabled Enabled Disabled Disabled Rollback
1 1 Enabled Enabled Disabled Disabled Loopback

Note: COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.

JT AG Access Port

A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in “VSC7123/VSC7133 JTAG Access Port Functionality.”

Transition

Detect

All Zeros/

All Ones

K28.5

Presence

Mode

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SEMICONDUCTOR CORPORATION

10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet

Figure 4: Transmit Timing Waveforms

REFCLK

T

T(0:9)

Data Valid

T a ble 2: Transmit AC Characteristics

Parameters Description Min Typ Max Units Conditions

T

T

T

SDR,TSDF

T

LA T

1

2

T(0:9) Setup time to the rising
edge of REFCLK

T(0:9) hold time after the rising
edge of REFCLK

TX+/TX- rise and fall time ——300 ps
Latency from r ising edge of

REFCLK to T0 appearing on
TX+/TX-

Transmitter Output Jitter Allocation

RJ Random jitter (RMS) — 58ps.

DJ

Serial data output deterministic
jitter (pk-pk)

T

1

Data Valid

1.5 ——ns

1.0 ——ns

8bc —

2

Data Valid

8bc+

4ns

— 30 80 ps.

Measured between the valid data
level of T(0:9) to the 1.4V point
of REFCLK.

20% to 80%, 50Ω load to

-2.0.

V

DD

bc = Bit clocks

ns

ns = Nano second

Measured at SO+/-, 1 sigma
deviation of 50% cro s si ng poin t.

IEEE 802.3Z Clause 38.68,
tested on a sample basis.

Data Sheet

VSC7123

Page 6 G52212-0, Rev 4.3

© VITESSE SEMICONDUCTOR CORPORATION • 741 Ca l le Pl an o • Camarillo, CA 93012

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Internet: www.vitesse.com

03/25/01