VITESSE VSC6250QW Datasheet

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6250

Features

• High-Speed Operation:
1 Gb/s Data Rate
500ps min Output Pulse Width
750ps min Input Pulse Width

• Excellent Overall Timing Accuracy:
Ultra-Stable Timing Delays
Minimum Pattern Dependence
Very Fine Timing Resolution (1 LSB = 8ps)

• High Level of Integration Reduces Board Area:
16 Independently Adjustable Delay Lines in a
Single Package

• Configurable as 2 1:8 or 1:16

1Gb/s 16-Channel

Drive-Side Deskew IC

• Wide Span: > 4ns Usable Range

• Pulse Width Adjustment to Compensate for
Dispersion in Pin Electronics:
± 2ns Independent Adjustment of Rising and
Falling Edges

• Fully Digital Single-Chip Solution:
No Off-Chip DACs Required
No DAC-Induced Timing Errors from Analog
Crosstalk, Reference Noise, Temperature, or
Voltage Drift

• Single Power Supply: -2V @ 5W

• 128-Pin PQFP, 14x20mm Thermally­Enhanced Package

Applications

• Drive-Side Deskew in High-Speed Memory
Testers

• Direct RAMBUS DRAM, SLDRAM, DDR
SDRAM, Fast SSRAM

• High-Speed Instrumentation: Pulse Generators,
Timing Margin Testers for Datalink, Interface,
and Disk Drive Applications

• Telecom, Datacom, and Computer Deskew

General Description

The VSC6250 is intended for use in the next generation o f high-speed, high-accurac y memory testers for

devices such as Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, and fast SSRAM.

The VSC6250 provides ultra-precise timing to allow next genera tion memory tes ters to achieve excellent
overall timing accuracy. Timing delays of the VSC6250 are extremely stable with r espect to temperatu re and
voltage. Proprietar y circuit desi gn and process te chnology red uce pattern, data, frequency, and duty-cycle
dependencies to an absolute minimum. The VSC6250 requires no external DACs, which eliminates errors due
to DAC reference noise and analog crosstalk, and DAC temperature and voltage drift. The VSC6250 is avail­able in a 128-pin PQFP, 14x20mm thermally-enhanced package.

G52197-0, Rev. 4.0 
8/19/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

1Gb/s 16-Channel

Drive-Side Deskew IC

VSC6250 Block Diagram

DINA

DIN

DINB

Data Sheet

VSC6250

S
R

S
R

S
R

Output 0

Output 7

Output 8

Reference

Clock

(250MHz)

Stability

Control

Parallel Data Interface

S
R

Output 15

Page 2 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52197-0, Rev. 4.0

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6250

1Gb/s 16-Channel

Drive-Side Deskew IC

Functional Description

The VSC6250 is a 1Gb/s 16- channel drive-path deskew IC desi gned for deske wing differences in path
delay between multiple DUTs in a high-speed memory test system. The VSC6250 can be used as two indepen­dent 1:8 fanout and deskew sections or as a single 1:16 fanout and deskew. When used as two 1:8 deskews,
input signals are applied to inputs DINA and DINB. When used as a single 1:16 deskew, the input is applied to
input DIN.

The VSC6250 is designed to operate with a conventional 500MHz timing generator which outputs format­ted pulses to the VSC6250 deskew IC. See Figure 1. The waveform at the input of the VSC6250 is the same as
that presented to the DUT pin. In a memory tester, such a 500MHz timing generator IC may be designed:

• Using one edge to output a single 500Mb/s data stream

• Using two edges to output a single 500Mb/s data stream preceded its complement

• Using three edges to output a single data stream at 500Mb/s surrounded by its complement

• Using two edges to output two interleaved 500Mb/s data streams for an aggregate bandwidth of 1Gb/s.

Formatting is performed inside the timing generator IC. An example interface between the timing generator
IC and the deskew is shown in Figure 1. This configuration is capable of supporting the four different data out­put choices, with appropriate design of the formatting logic.

The VSC6250 can handle pulses with a data rate up to 1Gb/s or a pulse repetition rate up to 2ns. A timing
diagram for the VSC6250 is shown in Figure 2.

Figure 1: VSC6250 Interface to Timing Generator IC

Timing Generator VSC6250

Timeset/Dataset

RAM

Format

Logic

DINx

DOUTx

S
R

Figure 2: VSC6250 AC Timing Diagram

t

REFIRE

t

PDR

t

PWI

t

PDF

t

S
R

S
R

PWO

G52197-0, Rev. 4.0 
8/19/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 3

VITESSE

SEMICONDUCTOR CORPORATION

1Gb/s 16-Channel

Drive-Side Deskew IC

The delay of each of the deskewed outputs can be adjusted separately to compensate for differences in path
length between DUTs on a single test head. The maximum delay is 7ns. Delay span is 5ns. Usable range is a
minimum of 4ns
and falling edges can be adjusted independently.

To ensure timing performance, delay of the VSC6250 is measured in product ion at every time ste p of every
vernier. Figure 3 shows measured output waveforms of the VSC6250. Figure 3 (a) shows a measured minimum
output pulse width. The specified mimi mum outpu t pulse wi dth is 500ps, but this measu rement shows operat ion
down to 300ps. Figure 3 (b) shows typical timing resolution of 8ps.

(1).

Resolution is 8ps. To compensate for pulse dispersion in pin electronics, delay of the rising

Figure 3: VSC6250 Measured Output Waveforms

Data Sheet

VSC6250

a) Mininum output pulse width of 300ps (b) Typical timing resolution of 8ps

With next generation testers required to test more DUTs per testhead in the same footprint, board area is a
critical design parameter. Providing 16 deskew channels in a 14mmx20mm thermally-enhanced 128-pin PQFP
package, the VSC6250 consumes less than 1/2 the total board area of the bipolar alternative.

Page 4 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52197-0, Rev. 4.0

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6250

1Gb/s 16-Channel

Drive-Side Deskew IC

The 32 delays (rising and falling edges for 16 channels) in the VSC6250 are programmed using a parallel
interface. Verniers are selected by a 5-bit address word and controlled by two function enable bits. Each vernier
requires 11 bits to set the delay value.

Power dissipation of the VSC6250 is less than 5W from a single -2V supply.

Table 1: Operational Mode Truth Table

Mode # Mode Name CALENN Mode Description

1Cal Mode 0
2 User Mode 1 Generates timing delays as set by data in Cal Mode.

Figure 4: CAL Mode Timing Diagram

ADR[4:0]

CALENN

Sets timing delays with each vernier selected with ADR [3:0] Serial Data
Input.

D[10:0]

MSB LSB

Load Calibration Register

Data Latch Transparent

1 CAL Cycle

Don’t Care

Latch Data into Data Latch

Measure Delay

10 9

G52197-0, Rev. 4.0 
8/19/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

Page 5

VITESSE

SEMICONDUCTOR CORPORATION

1Gb/s 16-Channel

Drive-Side Deskew IC

Figure 5: CAL Mode: Pre-Calibration Delay Range

32 Coarse Vernier Steps +

64 Fine Vernier Steps

Delay

000 Delay[0:10]

Figure 6: CAL Mode: Post-Calibration Delay Range

(1)

~275ps Fine Vernier Range

Data Sheet

VSC6250

32 Coarse Vernier Steps +

64 Fine Vernier Steps

Delay

000 Delay[0:10]

NOTE: (1) There are 32 coarse vernier codes and 64 fine vernier codes. Not all of the codes are used to reach
maximum delay. The current design utilizes 22 coarse cod es and 47 fine vern ie r code s. Fu tu re de sign s will utilize 22
course designs and 59 fine vernier codes. These numbers must be used whe n calculating INL and DNL. S yst em cal­ibration should be performed with the maximum usable codes. When a code is programmed beyond the maximum
utilized code, the delay will toggle between maximum delay and maximum delay minus 1LSB. Please contact your
local Vitesse sales representative to determine when the future design will be available.

(1)

= Unused Codes

Page 6 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE SEMICONDUCTOR CORPORATION

G52197-0, Rev. 4.0