Vishay VS-P400 Series Data Sheet

VS-P400 Series
PACE-PAK (D-19)
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Vishay Semiconductors
Power Modules,
Passivated Assembled Circuit Elements, 40 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 V
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
• Material categorization: For definitions of compliance please see www.vishay.com/doc?99912
RRM/VDRM
PRODUCT SUMMARY
I
O
Type Modules - Thyristor, Standard
Package PACE-PAK (D-19)
Circuit
Single phase, hybrid bridge common cathode,
Single phase, hybrid bridge doubler connection,
Single phase, all SCR bridge
40 A
DESCRIPTION
The VS-P400 series of integrated power circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simplified giving advantages of cost reduction and reduced size.
Applications include power supplies, control circuits and battery chargers.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL CHARACTERISTICS VALUES UNITS
I
O
,
I
TSM
I
FSM
2
t
I
2
t 7450 A2s
I
V
RRM
V
ISOL
T
J
T
Stg
80 °C 40 A
50 Hz 385
60 Hz 400
50 Hz 745
60 Hz 680
Range 400 to 1200 V
2500 V
-40 to 125 °C
ELECTRICAL SPECIFICATIONS
A
A2s
VOLTAGE RATINGS
TYPE NUMBER
VS-P401, VS-P421, VS-P431 400 500
VS-P402, VS-P422, VS-P432 600 700
VS-P403, VS-P423, VS-P433 800 900
VS-P404, VS-P424, VS-P434 1000 1100
VS-P405, VS-P425, VS-P435 1200 1300
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
V
RRM/VDRM
REPETITIVE PEAK REVERSE AND
PEAK OFF-STATE VOLTAGE
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
, MAXIMUM
V
1
V
, MAXIMUM
RSM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V
I
MAXIMUM
RRM
AT T
MAXIMUM
J
mA
10
Document Number: 93755
VS-P400 Series
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ON-STATE CONDUCTION
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum DC output current at case temperature
Maximum peak, one-cycle non-repetitive on-state or forward current
Maximum I
Maximum I
2
t for fusing I2t
2
t for fusing I2t
Low level value of threshold voltage V
High level value of threshold voltage V
Low level value of on-state slope resistance r
High level value of on-state slope resistance r
Maximum on-state voltage drop V
Maximum forward voltage drop V Maximum non-repetitive rate of rise of
turned-on current
Maximum holding current I
Maximum latching current I
I
I
TSM
I
FSM
T(TO)1
T(TO)2
dI/dt
Full bridge circuits
O
t = 10 ms
t = 8.3 ms 400
,
t = 10 ms
t = 8.3 ms 340
t = 10 ms
t = 8.3 ms 680
t = 10 ms
t = 8.3 ms 480 t = 0.1 ms to 10 ms, no voltage reapplied
2
I
t for time tx = I2t · tx
(16.7 % x x I (I > x I (16.7 % x x I
t1
(I > x I
t2
ITM = x I
TM
IFM = x I
FM
T
= 125 °C from 0.67 V
J
I
= x I
TM
H
TJ = 25 °C anode supply = 6 V, resistive load
L
No voltage reapplied
100 % V reapplied
No voltage
RRM
Sinusoidal half wave, initial T
reapplied
100 % V
reapplied
), TJ = TJ maximum 1.03
T(AV)
), TJ = TJ maximum 7.01
T(AV)
T(AV)
F(AV)
T(AV)
RRM
< I < x I
T(AV)
T(AV)
< I < x I
T(AV)
T(AV)
TJ = 25 °C 1.4 V
TJ = 25 °C 1.4 V
, Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
DRM
Vishay Semiconductors
40 A
80 °C
385
325
= TJ maximum
J
), TJ = TJ maximum 0.83
), TJ = TJ maximum 9.61
745
530
7450 A
200 A/μs
130
250
A
A
2
V
m
mA
2
s
s
BLOCKING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum critical rate of rise of off-state voltage
Maximum peak reverse and off-state leakage current at V
RRM
, V
DRM
Maximum peak reverse leakage current I
RMS isolation voltage V
dV/dt T
I
,
RRM
I
DRM
RRM
ISOL
= 125 °C, exponential to 0.67 V
J
gate open 200 V/μs
DRM
TJ = 125 °C, gate open circuit 10 mA
TJ = 25 °C 100 μA 50 Hz, circuit to base, all terminals shorted,
T
= 25 °C, t = 1 s
J
2500 V
TRIGGERING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum peak gate power P
Maximum average gate power P
Maximum peak gate current I
Maximum peak negative gate voltage -V
Maximum gate voltage required to trigger V
Maximum gate current required to trigger I
Maximum gate voltage that will not trigger V
Maximum gate current that will not trigger I
GM
G(AV)
GM
GM
GT
GT
GD
GD
TJ = - 40 °C
= 25 °C 2
J
T
= 125 °C 1
J
TJ = - 40 °C 90
= 25 °C 60
J
T
= 125 °C 35
J
TJ = 125 °C, rated V
Anode supply = 6 V resistive load
applied
DRM
8
2
W
2A
10 V
3
VT
mAT
0.2 V
2mA
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
2
Document Number: 93755
VS-P400 Series
Maximum Average On-State
Power Loss (W)
Average On-State Current (A)
10 200155
30
25
20
15
10
5
0
93755_02
Ø
Conduction angle
RMS limit
TJ = 125 °C Per junction
180° 120°
90° 60° 30°
Maximum Average On-State
Power Loss (W)
Average On-State Current (A)
20 3503010 15 255
40
25
20
35
30
15
10
5
0
93755_03
RMS limit
TJ = 125 °C Per junction
Conduction period
Ø
DC 180° 120°
90°
60°
30°
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THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum junction operating and storage temperature range
Maximum thermal resistance, junction to case per junction
Maximum thermal resistance, case to heatsink
Mounting torque, base to heatsink
(1)
Approximate weight
Case style PACE-PAK (D-19)
Note
(1)
A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
T
, T
J
Stg
R
thJC
R
thCS
DC operation 1.05
Mounting surface, smooth and greased 0.10
Vishay Semiconductors
-40 to 125 °C
K/W
4Nm
58 g
2.0 oz.
120
100
80
60
40
20
~
+
-
180°
(sine)
Maximum Total Power Loss (W)
0
0
5 10152025
93755_01a
Total Output Current (A)
120
TJ = 125 °C
100
80
60
40
20
1 K/W
1.5 K/W
2 K/W
3 K/W
5 K/W
10 K/W
R
thSA
Maximum Total Power Loss (W)
0
0
4030 35
93755_01b
25 7550 100 125
Maximum Allowable
Ambient Temperature (°C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)
= 0.7 K/W - ΔR
Fig. 2 - On-State Power Loss Characteristics Fig. 3 - On-State Power Loss Characteristics
Revision: 27-Mar-14
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
3
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Document Number: 93755
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Maximum Allowable Case
Temperature (°C)
Total Output Current (A)
10 20 30 405152535
45
0
70
80
90
100
110
120
130
Fully turned-on
180°
(Rect.)
180°
(Sine)
Per module
93755_04
Peak Half Sine Wave
On-State Current (A)
Number of Equal Amplitude Half
Cycle Current Pulses (N)
10 1001
150
175
200
300
250
325
275
225
350
93755_06
Per junction
At any rated load condition and with
rated V
RRM
applied following surge.
Initial T
J
= 125 °C at 60 Hz 0.0083 s at 50 Hz 0.0100 s
Peak Half Sine Wave
On-State Current (A)
Pulse Train Duration (s)
0.1 10.01
150
200
250
300
350
400
93755_07
Maximum non-repetitive surge current
versus pulse train duration. Control of
conduction may not be maintained.
Initial T
J
= 125 °C
No voltage reapplied
Rated V
RRM
reapplied
Per junction
0.01
0.1
1
10
0.0001 0.001 0.01 0.1 1
Square Wave Pulse Duration (s)
Z
thJC
- Transient Thermal Impedance (K/W)
93755_08
Steady state value R
thJC
= 1.05 K/W
(DC operation)
Per junction
VS-P400 Series
Vishay Semiconductors
1000
100
10
Instantaneous On-State Current (A)
1
0.5 1.0 2.0 3.01.5 2.5 3.5 4.0 4.5 5.0
93755_05
Fig. 5 - On-State Voltage Drop Characteristics
Fig. 4 - Current Ratings Characteristics
TJ = 25 °C
TJ = 125 °C
Per junction
Instantaneous On-State Voltage (V)
Fig. 6 - Maximum Non-Repetitive Surge Current
Fig. 7 - Maximum Non-Repetitive Surge Current
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 8 - Thermal Impedance Z
thJC
4
Characteristics
Document Number: 93755
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VS-P400 Series
Vishay Semiconductors
100
Rectangular gate pulse
10
1
Instantaneous Gate Voltage (V)
0.1
0.001
93755_09
(a) Recommended load line for rated dI/dt: 10 V, 20 Ω, t (b) Recommended load line for rated dI/dt: 10 V, 65 Ω, t
V
GD
I
GD
≤ 1 μs
r
≤ 1 μs
r
0.01 0.1 1 10 100
ORDERING INFORMATION TABLE
Device code
VS- 4P02KW
(1) PGM = 10 W, tp = 5 ms (2) P
GM
(3) P
GM
(4) P
GM
(1) (2) (3) (4)
Frequency limited by P
(b)
T
J
J
= 125 °C
T
T
= 25 °C
J
= 40 °C
(a)
Instantaneous Gate Current (A)
Fig. 9 - Gate Characteristics
1 32 4 5 6 7
= 20 W, tp = 25 ms = 50 W, tp = 1 ms = 100 W, tp = 500 μs
G(AV)
1 - Vishay Semiconductors product
2 - Module type
- Current rating
3
1 = 25 A DC (P100 Series) 4 = 40 A DC (P400 Series)
- Circuit configuration
4
0 = Single Phase, Hybrid Bridge Common Cathode 2 = Single Phase, Hybrid Bridge Doubler Connection 3 = Single Phase, all SCR Bridge
- Voltage code
5
1 = 400 V 2 = 600 V 3 = 800 V 4 = 1000 V 5 = 1200 V
6 - K = Optional Voltage Suppression
7 - W = Optional Freewheeling Diode
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 93755
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G1
AC2
AC1
G2
(-) (+)
G1G3
AC2
AC1
(-) (+)
G2G4
AC2
G2-
AC1 G3
G1 G4
+
CIRCUIT CONFIGURATION
CIRCUIT DESCRIPTION
Single phase, hybrid bridge common cathode
Single phase, hybrid bridge doubler connection
CONFIGURATION
CIRCUIT
CODE
0
2
VS-P400 Series
Vishay Semiconductors
SCHEMATIC DIAGRAM TERMINAL POSITIONS
AC1
G1-
AC2 G2+
G2G1
AC2
AC1
(-) (+)
AC1
G1-
AC2 G2+
Single phase, all SCR bridge 3
CODING
CIRCUIT DESCRIPTION
Single phase, hybrid bridge common cathode
Single phase, hybrid bridge doubler connection
Single phase, all SCR bridge 3
(1)
CIRCUIT
CONFIGURATION
CODE
0
2
BASIC
SERIES
WITH VOLTAGE
SUPPRESSION
P40. P40.K
P42. P42.K
P43. P43.K
WITH
FREEWHEELING
VOLTAGE SUPPRESSION
DIODE
P40.W P40.KW
--
--
Note
(1)
To complete code refer to Voltage Ratings table, i.e.: For 600 V P40.W complete code is P402W
LINKS TO RELATED DOCUMENTS
Dimensions www.vishay.com/doc?95335
WITH BOTH
AND FREEWHEELING
DIODE
Revision: 27-Mar-14
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6
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Document Number: 93755
DIMENSIONS in millimeters (inches)
0.9 x 45°
(0.035 x 45°)
4.6 (0.18)
D-19 PACE-PAK
12.7 (0.50)
12.7 (0.50)
Outline Dimensions
Vishay Semiconductors
Ø 1.65 (0.06)
2.5 (0.10) MAX.
23.2 (0.91)
63.5 (2.50)
45 (1.77)
33.8 (1.33)
48.7 (1.91)
15.5 (0.61) MAX.
Fast-on 6.35 x 0.8 (0.25 x 0.03)
5.2 (0.20)
25 (0.98) MAX.
32.5 (1.28) MAX.
Document Number: 95335 For technical questions, contact: indmodules@vishay.com Revision: 24-Jul-08 1
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Revision: 02-Oct-12
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