Vishay VS-P100 Series Data Sheet
VS-P100 Series
PACE-PAK (D-19)
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Vishay Semiconductors
Power Modules,
Passivated Assembled Circuit Elements, 25 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 V
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
RRM/VDRM
PRODUCT SUMMARY
I
O
Type Modules - Thyristor, Standard
Package PACE-PAK (D-19)
Circuit
Single phase, hybrid bridge common cathode,
Single phase, hybrid bridge doubler connection,
Single phase, all SCR bridge
25 A
The VS-P100 series of integrated power circuits consists of
power thyristors and power diodes configured in a single
package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
Applications include power supplies, control circuits and
battery chargers.
MAJOR RATINGS AND CHARACTERISTICS
DESCRIPTION
SYMBOL CHARACTERISTICS VALUES UNITS
I
O
I
TSM
2
t
I
2
t 6365 A2s
I
V
, V
DRM
RRM
V
ISOL
T
J
T
Stg
85 °C 25 A
50 Hz 357
60 Hz 375
50 Hz 637
60 Hz 580
400 to 1200 V
2500 V
Range -40 to 125 °C
-40 to 125 °C
ELECTRICAL SPECIFICATIONS
A
A2s
VOLTAGE RATINGS
TYPE NUMBER
VS-P101, VS-P121, VS-P131 400 500
VS-P102, VS-P122, VS-P132 600 700
VS-P103, VS-P123, VS-P133 800 900
VS-P103, VS-P124, VS-P134 1000 1100
VS-P105, VS-P125, VS-P135 1200 1300
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
V
RRM/VDRM
REPETITIVE PEAK REVERSE AND
PEAK OFF-STATE VOLTAGE
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
, MAXIMUM
V
1
V
, MAXIMUM
RSM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
, DiodesAsia@vishay.com, DiodesEurope@vishay.com
V
I
MAXIMUM
RRM
AT T
MAXIMUM
J
mA
10
Document Number: 93754
VS-P100 Series
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ON-STATE CONDUCTION
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum DC output current at case
temperature
Maximum peak, one-cycle non-repetitive
on-state or forward current
2
Maximum I
Maximum I
t for fusing I2t
2
t for fusing I2t
Maximum value of threshold voltage V
Maximum level value of on-state slope
resistance
Maximum on-state voltage drop V
Maximum forward voltage drop V
Maximum non-repetitive rate of rise of
turned-on current
Maximum holding current I
Maximum latching current I
I
I
TSM
I
FSM
T(TO)
r
dI/dt
Full bridge
O
t = 10 ms
t = 8.3 ms 375
,
t = 10 ms
t = 8.3 ms 315
t = 10 ms
t = 8.3 ms 580
t = 10 ms
t = 8.3 ms 410
t = 0.1 ms to 10 ms, no voltage reapplied
2
I
t for time tx = I2t · tx
No voltage
reapplied
100 % V
reapplied
RRM
No voltage
reapplied
100 % V
reapplied
RRM
Sinusoidal half wave,
initial T
TJ = 125 °C 0.82 V
TJ = 125 °C, average power = V
t1
ITM = x I
TM
IFM = x I
FM
T
J
I
TM
TJ = 25 °C anode supply = 6 V, resistive load, gate open 130
H
TJ = 25 °C anode supply = 6 V, resistive load 250
L
T(AV)
F(AV)
= 125 °C from 0.67 V
= x I
, Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
T(AV)
DRM
T(TO)
TJ = 25 °C 1.35 V
TJ = 25 °C 1.35 V
Vishay Semiconductors
25 A
85 °C
357
300
= TJ maximum
x I
J
T(AV)
+ rt + (I
T(RMS)
637
450
6365 A
2
)
12 m
200 A/μs
A
A
2
mA
2
s
s
BLOCKING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum critical rate of rise of off-state
voltage
Maximum peak reverse and off-state
leakage current at V
RRM
, V
DRM
Maximum peak reverse leakage current I
RMS isolation voltage V
dV/dt T
I
,
RRM
I
DRM
RRM
ISOL
= 125 °C, exponential to 0.67 V
J
gate open 200 V/μs
DRM
TJ = 125 °C, gate open circuit 10 mA
TJ = 25 °C 100 μA
50 Hz, circuit to base, all terminals shorted,
T
= 25 °C, t = 1 s
J
2500 V
TRIGGERING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum peak gate power P
Maximum average gate power P
Maximum peak gate current I
Maximum peak negative gate voltage -V
GM
G(AV)
GM
GM
TJ = - 40 °C
Maximum gate voltage required to trigger V
Maximum gate current required to trigger I
Maximum gate voltage that will not trigger V
Maximum gate current that will not trigger I
GT
GT
GD
GD
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
= 25 °C 2
J
= 125 °C 1
T
J
TJ = - 40 °C 90
= 25 °C 60
J
= 125 °C 35
T
J
TJ = 125 °C, rated V
DRM
Anode supply =
6 V resistive load
applied
2
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8
2
2A
10 V
3
0.2 V
2mA
Document Number: 93754
W
VT
mAT
VS-P100 Series
Maximum Average On-State
Power Loss (W)
Average On-State Current (A)
10 1505
15
10
5
0
93754_02
180°
120°
90°
60°
30°
RMS limit
Ø
Conduction angle
TJ = 125 °C
Per junction
Maximum Average On-State
Power Loss (W)
Average On-State Current (A)
20010155
20
10
15
5
0
93754_03
DC
180°
120°
90°
60°
30°
RMS limit
TJ = 125 °C
Per junction
Conduction period
Ø
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THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum junction operating
and storage temperature range
Maximum thermal resistance,
junction to case per junction
Maximum thermal resistance,
case to heatsink
Mounting torque, base to heatsink
Approximate weight
Case style PACE-PAK (D-19)
Note
(1)
A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
T
, T
J
Stg
R
thJC
R
thCS
(1)
DC operation 2.24
Mounting surface, smooth and greased 0.10
Vishay Semiconductors
-40 to 125 °C
K/W
4Nm
58 g
2.0 oz.
60
~
50
40
30
20
10
+
-
180°
(sine)
Maximum Total Power Loss (W)
0
0
93754_01a
5101520
Total Output Current (A)
60
R
thSA
2 K/W
3 K/W
7 K/W
10 K/W
25 7550 100 125
Maximum Allowable
TJ = 125 °C
50
40
30
5 K/W
20
10
Maximum Total Power Loss (W)
0
25
93754_01b
0
Ambient Temperature (°C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)
= 15 K/W - ΔR
Fig. 2 - On-State Power Loss Characteristics Fig. 3 - On-State Power Loss Characteristics
Revision: 27-Mar-14
For technical questions within your region: DiodesAmericas@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
3
, DiodesAsia@vishay.com, DiodesEurope@vishay.com
Document Number: 93754
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