VISHAY VBUS054B-HS3 Technical data

4-Line BUS-port ESD-protection

Features

• Ultra compact LLP75-6A package

• 4-line USB ESD-protection

• Low leakage current

• Low load capacitance C

= 0.8 pF

D

• ESD-protection to IEC 61000-4-2
± 15 kV contact discharge
TDB air discharge

• Lead (Pb)-free component

• Component in accordance to RoHS 2002/95/EC
and WEEE 2002/96/EC

Marking (example only)

e3

19957

VBUS054B-HS3

Vishay Semiconductors

6

1

1

4

5

3

2

20397

XX

Dot = Pin 1 marking
XX = Date code

YY

21001

YY = Type code (see table below)

Ordering Information

Device name Ordering code

VBUS054B-HS3 VBUS054B-HS3-GS08 3000 15 000

Taped units per reel

(8 mm tape on 7" reel)

Minimum order quantity

Package Data

Device name

VBUS054B-HS3 LLP75-6A U6 5.1 mg UL 94 V-0

Package

name

Marking

code

Weight

Molding compound

flammability rating

Moisture sensitivity level Soldering conditions

MSL level 1

(according J-STD-020)

260 °C/10 s at terminals

Absolute Maximum Ratings

Rating Test conditions Symbol Val ue Unit

Pin 1, 3, 4 or 6 to pin 2

Peak pulse current

Peak pulse power

ESD immunity

Operating temperature Junction temperature

Storage temperature

acc. IEC 61000-4-5; t

acc. IEC 61000-4-5; t

Pin 1, 3, 4 or 6 to pin 2

acc. IEC 61000-4-5; t

acc. IEC 61000-4-5; t

Contact discharge acc. IEC 61000-4-2; 10 pulses

Air discharge acc. IEC 61000-4-2; 10 pulses

= 8/20 µs; single shot

P

Pin 5 to pin 2

= 8/20 µs; single shot

P

= 8/20 µs; single shot

P

Pin 5 to pin 2

= 8/20 µs; single shot

P

I

I

P

P

V

V

T

PPM

PPM

PP

PP

ESD

ESD

T

STG

3A

10 A

45 W

200 W

± 15 kV

TBD kV

J

- 40 to + 125 °C

- 55 to + 150 °C

Document Number 81586

Rev. 1.3, 20-May-08

For technical support, please contact: [e-mail]

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1

VBUS054B-HS3

Vishay Semiconductors

Electrical Characteristics

Ratings at 25 °C, ambient temperature unless otherwise specified

VBUS054B-HS3

Paramete r Test conditions/remarks Symbol Min. Ty p. Max. Unit

Protection paths Number of line which can be protected N lines 4 lines

at I

= 0.1 µA

Reverse stand-off voltage

Reverse current

Reverse breakdown voltage

R

Pin 1, 3, 4 or 6 to pin 2

at V

IN

= V

RWM

= 5 V

Pin 1, 3, 4 or 6 to pin 2

at I

= 1 mA

R

Pin 5 to pin 2

= 1 mA

at I

R

Pin 1, 3, 4 or 6 to pin 2

at I

= 3 A; Pin 1, 3, 4 or 6 to pin 2;

Reverse clamping voltage

Forward clamping voltage

PP

acc. IEC 61000-4-5

at I

= 3 A; Pin 2 to pin 1, 3, 4 or 6;

F

acc. IEC 61000-4-5

Pin 1, 3, 4 or 6 to pin 2

V

(at pin 1, 3, 4 or 6) = 0 V and

IN

(at pin 5) = 5 V; f = 1 MHz

V

Capacitance

BUS

Pin 1, 3, 4 or 6 to pin 2

V

(at pin 1, 3, 4 or 6) = 2.5 V and

IN

(at pin 5) = 5 V; f = 1 MHz

V

BUS

Line symmetry Difference of the line capacitances

Supply line capacitance

Pin 5 to pin 2

= 0 V; f = 1 MHz

at V

R

V

RWM

I

V

V

V

V

C

C

dC

C

R

BR

BR

ZD

5V

< 0.01 0.1 µA

6.3 7.1 8 V

6.9 7.9 8.7 V

C

F

D

D

D

0.8 1 pF

0.5 0.8 pF

15 V

5V

0.05 pF

110 pF

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Document Number 81586

Rev. 1.3, 20-May-08

Typical Characteristics

T

= 25 °C, unless otherwise specified

amb

VBUS054B-HS3

Vishay Semiconductors

8 µs to 100 %

20 µs to 50 %

Time (µs)

PPM

I

100 %

80 %

60 %

40 %

20 %

0 %

010203040

20548

Figure 1. 8/20 µs Peak Pulse Current Wave Form

acc. IEC 61000-4-5

120 %

100 %

ESD

Discharge Current I

20557

80 %

60 %

53 %

40 %

27 %

20 %

0 %

- 10 0 10 20 30 40 50 60 70 80 90 100

rise time = 0.7 ns to 1 ns

Time (ns)

Figure 2. ESD Discharge Current Wave Form

acc. IEC 61000-4-2 (330 Ω/150 pF)

100

Pin 2 to Pin 5

10

1

(mA)

F

I

0.1

0.01

0.001

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

20550

Pin 2 to Pin 1, 3, 4 or 6

VF(V)

Figure 4. Typical Forward Current IF vs. Forward Voltage V

9

8

7

6

5

(V)

R

4

V

3

2

1

0

0.01 0.1 1 10 100 1000 10000

20551

Pin 1, 3, 4 or 6 to Pin 2

Pin 5 to Pin 2

IR(µA)

Figure 5. Typical Reverse Voltage VR vs. Reverse Current I

F

R

1.0
f = 1 MHz; V

0.9

0.8

0.7

0.6

(pF)

0.5

IN

0.4

C

0.3

0.2

0.1

0.0

012345 6

20549

BUS

Pin 1, 3, 4 or 6 to Pin 2

VIN(V)

Figure 3. Typical Input Capacitance C

Input Voltage V

Document Number 81586

Rev. 1.3, 20-May-08

20

(at Pin 5) = 5 V

at Pin 1, 3, 4, or 6 vs.

IN

IN

(V)

C

V

20552

Figure 6. Typical Peak Clamping Voltage VCvs.

Measured acc. IEC 61000-4-5
(8/20 µs - wave form)

15

Pin 1, 3, 4 or 6 to Pin 2

10

Pin 5 to Pin 2

5

Pin 2 to Pin 5

0

- 5
Pin 2 to Pin 1, 3, 4 or 6

- 10
01234

Peak Pulse Current I

For technical support, please contact: [e-mail]

IPP(A)

V

C

PP

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VBUS054B-HS3

Vishay Semiconductors

120

100

acc. IEC 61000-4-2

+ 8 kV

contact discharge

80

(V)

C-ESD

V

60

40

Pin 1, 3, 4, 6 to Pin 2

20

0

- 20

- 10 0 10 20 30 40 50 60 70 8090

20553

t (ns)

Figure 7. Typical Clamping Performance at + 8 kV

Contact Discharge (acc. IEC 61000-4-2)

(V)

C-ESD

V

- 100

- 120

- 140

- 160

20554

20

0

- 20

- 40

- 60

- 80

Pin 1, 3, 4 or 6 to Pin 2

acc. IEC 61000-4-2

- 8 kV

contact discharge

- 10 0 10 20 30 40 50 60 70 8090

t (ns)

Figure 8. Typical Clamping Performance at - 8 kV

Contact Discharge (acc. IEC 61000-4-2)

200

Pin 1, 3, 4 or 6 to Pin 2

150

100

50

(V)

C-ESD

V

- 50

acc. IEC 61000-4-2

0

contact discharge

V

C-ESD

- 100

- 150

- 200
Pin 2 to Pin 1, 3, 4 or 6

- 250

0 5 10 15 20

20555

V

(kV)

ESD

Figure 9. Typical Peak Clamping Voltage at ESD

Contact Discharge (acc. IEC 61000-4-2)

140

acc. IEC 61000-4-2

120

contact discharge

100

80

60

(V)

Pin 5 to Pin 2

40

C-ESD

V

20

0

V

C-ESD

- 20

- 40
Pin 2 to Pin 5

- 60

- 80

0 5 10 15 20

20556

V

(kV)

ESD

Figure 10. Typical Peak Clamping Voltage at ESD

Contact Discharge (acc. IEC 61000-4-2)

Application Note:

With the VBUS054B-HS3 a double, high speed USB-port or up to 4 other high speed signal or data lines can
be protected against transient voltage signals. Negative transients will be clamped close below the ground level
while positive transients will be clamped close above the 5 V working range. An avalanche diode clamps the
supply line (V
to pin 1, 3, 4 and 6. As long as the signal voltage on the data lines is between the ground- and the V
the low capacitance PN-diodes offer a very high isolation to V
soon as any transient signal exceeds this working range, one of the PN-diodes starts working in the forward
mode and clamps the transient to ground or to the avalanche breakthrough voltage level of the Z-diode
between pin 5 and pin 2.

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at pin 5) to ground (pin 2). The high speed data lines, D1+, D2+, D1- and D2-, are connected

BUS

BUS

, ground and to the other data lines. But as

BUS

t

V

BUS

w

D

1+

i

D

n

1-

U
S
B

­ P
o
r
t

D

2+

D

2-

GND

20399

6

4

5

3

2

1

For technical support, please contact: [e-mail]

R
E
C
E

I
V
E
R

IC

Document Number 81586

Rev. 1.3, 20-May-08

-level,

VBUS054B-HS3

Vishay Semiconductors

Background knowledge:

A zener- or avalanche diode is an ideal device for "cutting" or "clamping" voltage spikes or voltage transients
down to low and uncritical voltage values. The breakthrough voltage can easily be adjusted by the chip­technology to any desired value within a wide range. Up to about 6 V the "zener-effect" (tunnel-effect) is
responsible for the breakthrough characteristic. Above 6 V the so-called "avalanche-effect" is responsible. This
is a more abrupt breakthrough phenomenon. Because of the typical "Z-shape" of the current-voltage-curve of
such diodes, these diodes are generally called "Z-diode" (= zener or avalanche diodes). An equally important
parameter for a protection diode is the ESD- and surge-power that allows the diode to short current in the pulse
to ground without being destroyed.
This requirement can be adjusted by the size of the silicon chip (crystal). The bigger the active area the higher
the current that the diode can short to ground.
But the active area is also responsible for the diode capacitance - the bigger the area the higher the
capacitance.
The dilemma is that a lot of applications require an effective protection against more then 8 kV ESD while the
capacitance must be lower then 5 pF! This is well out of the normal range of a Z-diode. However, a Protection
diode with a low capacitance PN-diode (switching diode or junction diode) in series with a Z-diode, can fulfil
both requirements simultaneously: low capacitance AND high ESD- and/or surge immunity become possible!
A small signal (V
Z-diode in series remains "invisible".

< 100 mV) just sees the low capacitance of the PN-diode, while the big capacitance of the

pp

D

C

ZD

TOT

Such a constellation with a Z-diode and a small
PN-diode (with low capacitance) in series (anti-serial)
is a real unidirectional protection device. The
clamping current can only flow in one direction
(forward) in the PN-diode. The reverse path is
blocked.

Another PN-diode "opens" the back path so that the
protection device becomes bidirectional! Because the
clamping voltage levels in forward and reverse
directions are different, such a protection device has
a Bidirectional and Asymmetrical clamping behaviour
(BiAs) just like a single Z-diode.

= 0.4 pF

C

D

I/O

Gnd

I/O

Gnd

CZ

= 110 pF

D

D

1

ZD

ZD

20400

D

20401

D

2

20404

Document Number 81586

Rev. 1.3, 20-May-08

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VBUS054B-HS3

Vishay Semiconductors

One mode of use is,…
in the very first moment before any pulses have
arrived, all three diodes are completely discharged
(so the diode capacitances are empty of charge) the
first signal pulse with an amplitude > 0.5 V will drive
the upper PN-diode (D
"sees" the empty capacitance of the Z-diode (ZD).
Depending on the duration of this pulse and the pause
to the next one the Z-diodes capacitance can be
charged up so that the next pulse "sees" a lower
capacitance. After some pulses the big Z-diode could
be completely charged up so that the following pulses
just see the small capacitance of both PN-diodes.

For some application this can work perfectly.....

) in a forward direction and

1

D

I/O

Gnd

1

D

2

ZD

20405

For others applications the capacitance must be the
same all the time from the first till the last pulse.

For these applications the appropriate mode of use is
to connect the Z-diode to the supply voltage.
In this mode the Z-diode is charged up immediately by
the supply voltage and both PN-diodes are always
used in reverse. This keeps their capacitance at a
minimum.

V

BUS

I/O

Gnd

D

1

D

2

ZD

20406

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Document Number 81586

Rev. 1.3, 20-May-08

Package Dimensions in millimeters (inches): LLP75-6A

VBUS054B-HS3

Vishay Semiconductors

18058

Document Number 81586

Rev. 1.3, 20-May-08

For technical support, please contact: [e-mail]

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VBUS054B-HS3

Vishay Semiconductors

Ozone Depleting Substances Policy Statement

It is the policy of Vishay Semiconductor GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating
systems with respect to their impact on the health and safety of our employees and the public, as well as
their impact on the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are
known as ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs
and forbid their use within the next ten years. Various national and international initiatives are pressing for an
earlier ban on these substances.

Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use
of ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively.

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA.

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.

We reserve the right to make changes to improve technical design

and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or

unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages,

and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated

with such unintended or unauthorized use.

Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

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Document Number 81586

Rev. 1.3, 20-May-08

Legal Disclaimer Notice

Vishay

Notice

Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.

Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.

Document Number: 91000 www.vishay.com
Revision: 08-Apr-05 1