Vishay TP0101K Schematic [ru]

Vishay Siliconix

P-Channel 20-V (D-S) MOSFET, Low-Threshold

TP0101K

PRODUCT SUMMARY

VDS (V) R

- 20

G

S

Ordering Information:

DS(on)

0.65 at V

0.85 at V

TO-236

(SOT-23)

1

2

To p View

GS

GS

TP0101K-T1-E3 (Lead (Pb)-free)
TP0101K-T1-GE3 (Lead (Pb)-free and Halogen-free)

(Ω)

= - 4.5 V

= - 2.5 V

3

FEATURES

I

(A)

D

- 0.58

- 0.5

e

• Halogen-free According to IEC 61249-2-21
Available

• TrenchFET

®

Power MOSFET

• ESD Protected: 3000 V

APPLICATIONS

• Drivers: Relays, Solenoids, Lamps, Hammers, Displays,
Memories

• Battery Operated Systems, DC/DC Converters

• Power Supply Converter Circuits

• Load/Power Switching-Cell Phones, Pagers

D

Marking Code: K4ywl

D

K4 = Part Number Code for TP0101K

y = Year Code
w = Week Code
l = Lot Traceability

G

100 Ω

S

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

Pulsed Drain Current

= 150 °C)

J

a

Continuous Source-Drain (Diode Current)

Power Dissipation

b

b

b

Operating Junction and Storage Temperature Range

TA = 25 °C

= 70 °C

T

A

TA = 25 °C

= 70 °C

T

A

V

DS

V

GS

I

D

I

DM

I

S

P

D

, T

T

J

stg

- 20

± 8

- 0.58

- 0.46

- 2

- 0.3

0.35

W

0.22

- 55 to 150 °C

V

A

Notes:
a. Pulse width limited by maximum junction temperature.
b. Surface Mounted on FR4 board, t ≤ 10 s.

THERMAL RESISTANCE RATINGS

Parameter Symbol Limits Unit

Thermal Resistance, Junction-to-Ambient

b

Notes:
a. Pulse width limited by maximum junction temperature.
b. Surface Mounted on FR4 board, t ≤ 10 s.

Document Number: 72692
S-83053-Rev. B, 29-Dec-08

R

thJA

357 °C/W

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1

TP0101K

Vishay Siliconix

SPECIFICATIONS TA = 25 °C, unless otherwise noted

Limits

Parameter

Static

Drain-Source Breakdown Voltage

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

b

a

a

a

a

Total Gate Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n Ti me

Turn-Off Time

Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Symbol Test Conditions

V

V

GS(th)

I

GSS

I

DSS

I

D(on)

R

DS(on)

V

Q

Q

t

d(on)

t

d(off)

DS

g

fs

SD

Q

g

gs

gd

R

g

t

r

t

f

VGS = 0 V, ID = - 10 µA

V

= VGS, ID = - 50 µA

DS

VDS = - 0 V, VGS = ± 4.5 V

V

= - 20 V, V

DS

V

= - 20 V, V

DS

V

DS

V

DS

V

GS

V

GS

GS

≤ - 5 V, V

≤ - 5 V, V

= - 4.5 V, ID = - 0.58 A

= - 2.5 V, ID = - 0.5 A

VDS = - 5 V, ID = - 0.58 A

IS = - 0.3 A, VGS = 0 V

VDS = - 6 V, VGS = - 4.5 V

≅ - 0.58 A

I

D

V

= - 6 V, RL = 10 Ω

DD

≅ - 0.58 A, V

I

D

GEN

GS

= 0 V, TJ = 55 °C

= - 4.5 V

GS

= - 2.5 V

GS

= - 4.5 V, Rg = 6 Ω

= 0 V

Min. Typ. Max. Unit

- 20

- 0.5 - 0.7 - 1.0

V

± 5

- 1

µA

- 10

- 1.2

- 0.5

0.42 0.65

0.64 0.85

A

Ω

1300 mS

- 0.9 - 1.2 V

1400 2200

300

pCGate-Source Charge

250

150 Ω

25 35

30 45

55 85

ns

38 60

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2

Document Number: 72692

S-83053-Rev. B, 29-Dec-08

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

2.0

VGS = 5 thru 3 V

1.6

2.5 V

TP0101K

Vishay Siliconix

2.0

TJ = - 55 °C

1.6
25 °C

1.2

0.8

- Drain Current (A)

D

I

0.4

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VDS- Drain-to-Source Voltage (V)

Output Characteristics

3.0

2.5

2.0

1.5

- On-Resistance (Ω)R

1.0

DS(on)

0.5

VGS = 2.5 V

VGS = 4.5 V

2 V

1.5 V

1 V

1.2

0.8

- Drain Current (A)I

D

0.4

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

- Gate-to-Source Voltage (V)

V

GS

Transfer Characteristics

200

175

C

150

125

100

75

C - Capacitance (pF)

50

25

C

rss

iss

C

oss

125 °C

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

On-Resistance vs. Drain Current and Gate Voltage

5

VDS = 6 V

I

= 0.6 A

D

4

3

2

- Gate-to-Source Voltage (V)

GS

V

1

0

0.0 0.3 0.6 0.9 1.2 1.5

Document Number: 72692
S-83053-Rev. B, 29-Dec-08

ID - Drain Current (A)

Qg- Total Gate Charge (nC)

Gate Charge

0

048 12 16 20

VDS- Drain-to-Source Voltage (V)

Capacitance

1.7

1.5

1.3

- On-Resistance R

1.1

(Normalized)

DS(on)

0.9

0.7

- 50 - 25 0 25 50 75 100 125 150

VGS = 4.5 V

= 0.6 A

I

D

- Junction Temperature (°C)

T

J

On-Resistance vs. Junction Temperature

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3

TP0101K

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

4

1

0.1

- Source Current (A)I

S

0.01

0.001

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

TJ = 150 °C

-)V( egatloV niarD-ot-ecruoS

V

SD

TJ = 25 °C

Source-Drain Diode Forward Voltage

0.4

0.3

ID = 50 µA

0.2

0.1

Variance (V)V

- On-Resistance (Ω)R

DS(on)

100 000

10 000

3.0

2.5

2.0

1.5

1.0

0.5

0.0
012345

VGS- Gate-to-Source Voltage (V)

ID = 0.6 A

On-Resistance vs. Gate-to-Source Voltage

1000

100

10

TJ = 150 °C

GS(th)

0.0

- 0.1

- 0.2

- 50 - 25 0 25 50 75 100 125 150

TJ- Temperature (°C)

Threshold Voltage

5

4

3

Power (W)

2

1

0

Time (s)

Single Pulse Power, Junction-to-Ambient

100

1

- Gate Current (µA)I

GSS

0.1

0.01

0.001

0 268 10

TJ = 25 °C

4

V

- Gate-to-Source Voltage (V)

GS

Gate Current vs. Gate-Source Voltage

10

R *

Limited

DS(on)

1

I

0.1

- Drain Current (A)I

D

0.01

0061100.10.01

0.001

D(on)

Limited

TA = 25 °C

Single Pulse

BV

Limited

DSS

0.1 1 10 100

* V

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

GS

DS(on)

IDMLimited

1 ms

10 ms

100 ms

1 s
10 s

DC

is specified

Safe Operating Area, Junction-to-Ambient

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Document Number: 72692

S-83053-Rev. B, 29-Dec-08

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

2

1

Duty Cycle = 0.5

TP0101K

Vishay Siliconix

Transient

0.1

Thermal Impedance

Normalized Effective

0.01
10

-4

0.2

0.1

0.05

0.02

Single Pulse

-3

10

-2

10

Square Wave Pulse Duration (s)

-1

Normalized Thermal Transient Impedance, Junction-to-Ambient

100

00601110

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72692

Document Number: 72692

.

www.vishay.com

S-83053-Rev. B, 29-Dec-08

5

SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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1

Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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APPLICATION NOTE

Legal Disclaimer Notice

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Vishay

Disclaimer

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disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.

Revision: 02-Oct-12

1

Document Number: 91000